Datasheet LC72349W, LC72348G, LC72349G, LC72348W Datasheet (SANYO)

Page 1

Ordering number : ENN6472

32700RM (OT) No. 6472-1/14

Overview

The LC72348G/W and LC72349G/W are low-voltage electronic tuning microcontrollers that include a PLL that operates up to 230 MHz and a 1/4 duty 1/2 bias LCD driver on chip. These ICs can contribute to further end product cost reduction than the LC72341 series while providing improved standby current characteristics. Also these ICs can use the application program for the LC72341 series except the IF counter function. These ICs are optimal for use in low-voltage portable audio equipment that includes a radio receiver.

Function

• Program memory (ROM):

— 3072 × 16 bits (6K bytes) LC72348G/W — 4096 × 16 bits (8K bytes) LC72349 G/W

• Data memory (RAM):

— 192 × 4 bits LC72348 G/W — 256 × 4 bits LC72349 G/W

• Cycle time: 40 µs (all 1-word instructions) at 75kHz crystal oscillation

• Stack: 8 levels

• LCD driver: 48 to 80 segments (1/4 duty, 1/2 bias drive)

• Interrupts: One external interrupt

Timer interrupts (1, 5, 10, and 50 ms)

• A/D converter: Three input channels

(5-bit successive approximation conversion)

• Input ports: 7 ports (of which three can be switched for use as A/D converter inputs)

• Output ports: 6 ports (of which 1 can be switched for use

as the beep tone output and 2 are opendrain ports)

• I/O ports: 16 ports (of which 8 can be switched for use

as LCD ports and as mask options)

Continued on next page.

Package Dimensions

unit: mm

3231-QIP64G

10.0

12.0

1.25

0.5

1.25

1.25 0.5 1.250.18

12.0

116

10.0

0.5

1.7max

0.5

0.1

0.15

SANYO: SQFP64

[LC72348W, 72349W]

LC72348G/W, 72349G/W

SANYO Electric Co.,Ltd. Semiconductor Company

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN

Low-Voltage ETR Controller

with On-Chip LCD Driver

CMOS IC

Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft’s control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications.

SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein.

14.0

17.2

1.0

1.6

0.15

0.35

0.1

15.6

0.8

3.0max

116

2.15

14.0

17.2

1.0

1.6

0.8

SANYO: QFP64G

[LC72348G, 72349G]

unit: mm

3190-SQFP64

Page 2

No. 6472-2/14

LC72348G/W, 72349G/W

Parameter Symbol Conditions Ratings Unit

Maximum supply voltage V

max –0.3 to +4.0 V

Input voltage V

All input pins –0.3 to VDD+0.3 V

Output voltage

OUT

(1) AOUT, PE –0.3 to +15 V

OUT

(2) All output pins except V

OUT

(1) –0.3 to VDD+ 0.3 V

OUT

(1) PC, PD, PG, PH, EO 0 to 3 mA

OUT

(2) PB 0 to 1 mA

Output current I

OUT

(3) AOUT, PE 0 to 2 mA

OUT

(4) S1 to S20 300 µA

OUT

(5) COM1 to COM4 3 mA Allowable power dissipation Pdmax Ta = –20 to +70°C 300 mW Operating temperature Topr –20 to +70 °C Storage temperature Tstg –45 to +125 °C

Specifications

Absolute Maximum Ratings at Ta = 25°C, VSS= 0 V

Continued from preceding page.

• PLL: Supports dead zone control (two types)

• Reference frequencies: 1, 3, 3.125, 5, 6.25, 12.5, and 25 kHz

• Input frequencies: FM band: 10 to 230 MHz

AM band: 0.5 to 10 MHz

• Input sensitivity: FM band: 35 mVrms (50 mVrms at 130 MHz or higher

frequency)

AM band: 35 mVrms

• External reset input: During CPU and PLL operations,

instruction execution is started from location 0.

• Built-in power-on reset circuit: The CPU starts execution from location 0 when power is first applied.

• Halt mode: The controller-operating clock is stopped.

• Backup mode: The crystal oscillator is stopped.

• Static power-on function: Backup state is cleared with the PF port

• Beep tone: 1.5 and 3.1 kHz

• Built-in tuner voltage generating circuit:

Cost reduced in tuner-use power supply circuit

• Built-in low-pass filter amplifier

• Optional function switches:

— PH0 to PH3 (general-purpose input, open-drain

output/general-purpose input and output/S13 to S16)

— PG0 to PG3 (general-purpose input, open-drain

output/general-purpose input and output/S17 to S20) — VSENSE circuit (provided/not provided) — FM DC/DC clock (1/256, 75 kHz)

• Memory retention voltage: 0.9 V at least

• Package: SQFP-64 (0.5-mm pitch), QIC-64 (0.8-mm pitch)

Page 3

No. 6472-3/14

LC72348G/W, 72349G/W

Parameter Symbol Conditions

Ratings

Unit

min typ max

(1) PLL operating voltage 1.8 3.0 3.6

Supply voltage

(2) Memory retention voltage 1.0

(3) CPU operating voltage 1.4 3.0 3.6

(4) A/D converter operating voltage 1.6 3.0 3.6

(1)

Input ports other than V

(2), VIH(3), AMIN,

0.7 V

Input high-level voltage

FMIN, and XIN

(2) RES 0.8 V

(3) Port PF 0.6 V

(1)

Input ports other than V

(2), VIL(3), AMIN,

0 0.3 V

Input low-level voltage

FMIN, and XIN

(2) RES 0 0.2 V

(3) Port PF 0 0.2 V

(1) XIN 0.5 0.6 Vrms

Input amplitude V

(2) FMIN, AMIN 0.035 0.35 Vrms

(3) FMIN 0.05 0.35 Vrms

Input voltage range V

(5) ADIO, ADI1, ADI3 0 V

(1) XIN: CI ≤ 35 kΩ 70 75 80 kHz

Input frequency

(2) FMIN: VIN(2), VDD(1) 10 130 MHz

(3) FMIN: VIN(3), VDD(1) 130 250 MHz

(4) AMIN(L): VIN(2), VDD(1) 0.5 10 MHz

Allowable Operating Ranges at Ta = –20 to +70°C, VDD= 1.8 to 3.6 V

Parameter Symbol Conditions

Ratings

Unit

min typ max

(1) XIN: VI= VDD= 3.0 V 3 µA

Input high-level current

(2) FMIN, AMIN: VI= VDD= 3.0 V 3 8 20 µA

PA/PF (without pull-down resistors), the PC,

IIH(3) PD, PG, and PH ports, and RES: VI= V

3µA

= 3.0 V

IIL(1) XIN: VI= VDD= V

–3 µA

Input low-level current

(2) FMIN, AMIN: VI= VDD= V

–3 –8 –20 µA

PA/PF (without pull-down resistors), the PC,

IIL(3) PD, PG, and PH ports, and RES: VI= V

–3 µA

= V

Input floating voltage V

PA/PF (with pull-down resistors) 0.05 V

Pull-down resistor values

(1) PA/PF (with pull-down resistors), VDD= 3.0 V 75 100 200 kΩ

(2) TEST1, TEST2 10 kΩ

Hysteresis V

RES 0.1 V

0.2 V

Voltage doubler reference voltage

DBR4

Referenced to V

, C(3) = 0.47 µF,

1.3 1.5 1.7 V

Ta = 25°C *

Voltage doubler step-up voltage DBR1, 2, 3

C(1) = 0.47 µF

2.7 3.0 3.3 V

C(2) = 0.47 µF, without loading, Ta = 25°C *

VOH(1) PB: IO= –1 mA

– VDD– V

0.7 V

0.3 V

VOH(2) PC, PD, PG, PH: IO= –1 mA

–

0.3 V

VOH(3) EO: IO= –500 µA

–

Output high-level voltage 0.3 V

VOH(4) XOUT: IO= –1 µA

–

0.3 V

VOH(5) S1 to S20: IO= –20 µA *

2.0 V

(6)

COM1, COM2, COM3, COM4:

2.0 V

= –100 µA *

Electrical Characteristics within the allowable operating ranges

Continued on next page.

Page 4

No. 6472-4/14

LC72348G/W, 72349G/W

Parameter Symbol Conditions

Ratings

Unit

min typ max

(1) PB: IO= –50 µA 0.3 V

0.7 V

(2) PC, PD, PE, PG, PH: IO= –1 mA 0.3 V

(3) EO: IO= –500 µA 0.3 V

(4) XOUT: IO= –1 µA 0.3 V

Output low-level voltage V

(5) S1 to S20: IO= –20 µA *

1.0 V

(6)

COM1, COM2, COM3, COM4:

1.0 V

= –100 µA *

VOL(7) PE: IO= 2 mA 1.0 V V

(8) AOUT(AIN = 1.3 V), TU: IO= 1 mA, VDD= 3 V 0.5 V

Output off leakage current

OFF

(1) Ports PB, PC, PD, PG, PH, and EO –3 +3 µA

OFF

(2) AOUT and port PE –100 +100 nA

A/D converter error ADI0, ADI1, ADI3 V

(4) –1/2 +1/2 LSB

Supply voltage drop detection voltage V

SENSE

(1) Ta = 25°C *

1.6 1.75 1.9 V

Supply voltage rise detection voltage V

SENSE

(2) Ta = 25°C *

(1)min (1)max

+0.1 +0.2 IDD(1) VDD(1): FIN(2) 130 MHz, Ta = 25°C 5 15 mA I

(2) VDD(2): In HALT mode, Ta = 25°C *

0.1 mA

Current drain I

(3)

= 3.6 V, with the oscillator stopped,

1µA

Ta = 25°C *

IDD(4)

= 1.8 V, with the oscillator stopped,

0.5 µA

Ta = 25°C *

Note: The halt mode current is due to the CPU executing 20 instruction steps every 125 ms.

Continued from preceding page.

Pin Assignment

616263

DBR3

DBR2

DBR1

RES

VDD

DBR4

PD1

INT/PD0

PE1

BEEP/PE0

ADI3/PF2

ADI1/PF1

ADI0/PF0

VSS

PG3/S20

PG2/S19

PG1/S18

PG0/S17

PH3/S16

PH2/S15

PH1/S14

PH0/S13

AMIN

VSS

AOUT

AIN

AGND

TEST1

XIN

FMIN

64 585960 555657 525354 495051

48 47 46 45 44 43 42 41 40 39 38 37 36 35 3415

16 33

13 14

11 12

7 8

5 6

3 4

COM1XOUT

COM2TEST2 COM3PA3 COM4PA2 S1PA1 S2PA0 S3

PB3

S4PB2

LC72348G, 72348W LC72349G, 72349W

S5PB1 S6

PB0

S7PC3 S8PC2 S9PC1 S10PC0 S11PD3

PD2 S12

Page 5

Note: * C(1), C(2), and C(3) must be connected even if an LCD is not used.

No. 6472-5/14

LC72348G/W, 72349G/W

DBR1 DBR2 DBR3

0.1 to 1 µF

C(C1)

C(C2)

DBR4

C(C3)

Notes: *1. The capacitors C(1), C(2), and C(3) must be connected to the DBR pins.

*2. V

SENSE

When the VDDvoltage drops, the V

SENSE

flag is set when that voltage is 1.75 V (typical). Applications can

check the V

SENSE

flag using the TST instruction. Battery or other power source depletion can be easily measured by monitoring this flag. Note that the voltage for V

SENSE

detection differs for the falling and rising directions. Thus, after the V

SENSE

flag has been set due to a voltage drop, it will not be reset if the voltage rises by under 0.1 V.

1.9 V

1.6 V → SETRESET←

2.1 V

1.7 V →RESETSET←

7 pF 7 pF

FMIN

XIN

AMIN TEST1, 2

XOUT

VDD

DBR2

DBR1

0.1 µF

DBR3 DBR4

RESRES

VSS

PA, PF

AGND

AIN

FMIN

XIN

AMIN TEST1, 2

XOUT VDD

VSS

AGND

AIN

7pF

75 kHz 75 kHz

7pF

DBR2 DBR3

DBR4

SENSE

(1)

For a falling voltage

*3. Halt mode current measurement circuit *4. Backup mode current measurement circuit

With all ports other than those specified above left open. With output mode selected for PC and PD. With segments S13 to S20 selected.

SENSE

(2)

For a rising voltage

Page 6

Block Diagram

No. 6472-6/14

LC72348G/W, 72349G/W

PHASE

DETECTOR

REFERENCE DIVIDER

SYSTEM CLOCK

GENERATOR

PROGRAMMBLE DIVIDER

1/16,1/17

SENSE

SEG

P-ON

RESET

TIME BASE CONTROL

BANK

COUNT

END

ADDRESS DECODER

DATA BUS

TIMER 0

JUDGE

ALU

SKIP

BANK

LATCH

STACK

ADDRESS COUNTER

ADDRESS DECODER

ROM

3k 16bits

(LC72348)

4k 16bits

(LC72349)

RAM

192×

× ×

4bits(LC72348)

256 4bits(LC72349)

BUS

CONTROL

JMP CAL RETURN INTERRUPT RESET

INSTRUCTION

DECODER

PLL DATA LATCH

PLL CONTROL

FM LOCAL 1/256

AM LOCAL 1/2

DATA

LATCH

BUS

DRIVER

DATA

LATCH

BUS

DRIVER

BUS

DRIVER

XIN

XOUT FMIN

PC2

PC1

PC0

PC3

PA3

PA2

PA1

PA0

TEST2

TEST1

RES

AMIN

S16/PH3

S15/PH2

S13/PH0 S14/PH1

LCD

PORT

DRIVER

LCPA/B

LCDA/B

S12

VSS

VDD

PB2

PB1

PB0

PB3

LATCH

BUS

DRIVER

PD2

PD1

INT/PD0

AGND

AOUT

AIN

PD3

LATCH

PE0/BEEP

COM1

COM2

COM3

COM4

DBR4

DBR3

DBR2

DBR1

S20/PG3

S19/PG2

S17/PG0 S18/PG1

LATCH

BUS

DRIVER

ADC

(5bits)

MPX

BEEP TONE

COMMON DRIVER

DOUBLER CIRCUIT

LATCH

BUS

DRIVER

LATCH

BUS

DRIVER

LATCH

BUS

DRIVER

7 80

PF1/ADI1

PF0/ADI0

PE1

PF2/ADI3

75kHz

DIVIDER

1/2

DATA

Page 7

No. 6472-7/14

LC72348G/W, 72349G/W

Pin Functions

Pin No. Pin I/O Function I/O circuit

75 kHz oscillator connections

XIN

XOUT

IC testing. These pins must be connected to ground during normal operation. —

TEST1 TEST2

I I

Special-purpose key return signal input ports designed with a low threshold voltage. When used in conjunction with port PB to form a key matrix, up to 3 simultaneous key presses can be detected. The four pull-down resistors are selected together in a single operation using the IOS instruction (PWn = 2, b1); they cannot be specified individually. Input is disabled in backup mode, and the pull-down resistors are disabled after a reset.

6 5 4 3

PA0 PA1 PA2 PA3

General-purpose CMOS and n-channel open-drain output shared-function ports. The IOS instruction (Pwn = 2) is used for function switching. (b0: PB0, b2: PB1, b3: PB2, PB3) (0: general-purpose CMOS, 1: n-channel open-

drain) Special-purpose key source signal output ports. Since unbalanced CMOS output

transistor circuits are used, diodes to prevent short-circuits when multiple keys are pressed are not required. These ports go to the output high-impedance state in backup mode. These ports go to the output high-impedance state after a reset and remain in that state until an output instruction (OUT, SPB, or RPB) is executed.

*: Verify the output impedance conditions carefully if these pins are used for functions

other than key source outputs.

9 8 7

PB0 PB1 PB2 PB3

General-purpose I/O ports. PD0 can be used as an external interrupt port. Input or output mode can be set

individually using the IOS instruction by the bit (Pwn = 4, 5). A value of 0 specifies input, and 1 specifies output. These ports go to the input disabled high-impedance state in backup mode. They are set to function as general-purpose input ports after a reset.

14 13 12 11

18 17 16 15

PC0 PC1 PC2 PC3

INT/PD0

PD1 PD2 PD3

I/O

General-purpose output ports with shared beep tone output function (PE0 only). The BEEP instruction is used to switch PE0 between the general-purpose output port and beep tone output functions. To use PE0 as a general-purpose output port, execute a BEEP instruction with b2 set to 0. Set b2 to 1 to use PE0 as the beep tone output port. The b0 and b1 bits are used to select the beep tone frequency. There are two beep tone frequencies supported.

*: When PE0 is set up as the beep tone output, executing an output instruction to PE0

only changes the state of the internal output latch, it does not affect the beep tone output in any way. Only the PE0 pin can be switched between the general-purpose output function and the beep tone output function; the PE1 pin only functions as a general-purpose output. These pins go to the high-impedance state in backup mode and remain in that state until an output instruction or a BEEP instruction is executed. Since these ports are open-drain ports, resistors must be inserted between these pins and V

. These ports are set to general-purpose output port

function after a reset.

20 19

BEEP/PE0

PE1

Input with built-in

pull-down resistor

Unbalanced CMOS pushpull/n-channel open-drain

N-channel open-drain

CMOS push-pull

Continued on next page.

Page 8

No. 6472-8/14

LC72348G/W, 72349G/W

Continued from preceding page.

Pin No. Pin I/O Function I/O circuit

General-purpose input and A/D converter input shared function ports. The IOS instruction (Pwn = FH) is used to switch between the general-purpose input and A/D converter port functions. The general-purpose input and A/D converter port functions can be switched by the bit, with 0 specifying general-purpose input, and 1 specifying the A/D converter input function. To select the A/D converter function, set up the A/D converter pin with an IOS instruction with Pwn set to 1. The A/D converter is started with the UCC instruction (b3 = 1, b2 = 1). The ADCE flag is set when the conversion completes. The INR instruction is used to read in the data.

*: If an input instruction is executed for one of these pins which is set up for analog

input, the read in data will be at the low level since CMOS input is disabled. In backup mode these pins go to the input disabled high-impedance state. These ports are set to their general-purpose input port function after a reset. The A/D converter is a 5-bit successive approximation type converter, and features a conversion time of 1.28 ms. Note that the full-scale A/D converter voltage (1FH) is (63.96) V

23 22 21

PF0/ADI0 PF1/ADI1 PF2/ADI3

CMOS input/analog input

LCD driver segment output, general-purpose I/O, and general-purpose n-channel open-drain output shared function ports.

The IOS instruction is used for switching between the segment output and generalpurpose I/O functions.

• When used as segment output ports The general-purpose I/O port function is selected with the IOS instruction (Pwn = 8).

b0 = S17 to 20/PG0 to 3 (0: Segment output, 1: PG0 to 3)

The general-purpose I/O port function is selected with the IOS instruction (Pwn = 9).

b0 = S13 to 16/PH0 to 3 (0: Segment output, 1: PH0 to 3)

• When used as general-purpose I/O ports The IOS instruction (Pwn = 6,7) is used to select input or output. Note that the mode can be set in individual by the bit.

b0 = PG0 b0 = PH0 b1 = PG1 0: Input b1 = PH1 0: Input b2 = PG2 1: Output b2 = PH2 1: Output b3 = PG3 b3 = PH3

In backup mode, these pins go to the input disabled high-impedance state if set up as general-purpose outputs, and are fixed at the low level if set up as segment outputs. These ports are set up as segment outputs after a reset.

Although the general-purpose I/O port/general-purpose n-channel open-drain output/LCD port setting is a mask option, the IOS instruction must be used as described above to set up the port function.

25 26 27 28

29 30 31 32

PG3/S20 PG2/S19 PG1/S18 PG0/S17

PH3/S16 PH2/S15 PH1/S14 PH0/S13

I/O

CMOS push-pull

LCD driver segment output pins. A 1/4-duty 1/2-bias drive technique is used. The frame frequency is 75 Hz. In backup mode, the outputs are fixed at the low level. After a reset, the outputs are fixed at the low level.

33 to

S16 to S1 O

LCD driver common output pins. A 1/4-duty 1/2-bias drive technique is used. The frame frequency is 75 Hz. In backup mode, the outputs are fixed at the low level. After a reset, the outputs are fixed at the low level.

45 46 47 48

COM4 COM3 COM2 COM1

LCD power supply step-up voltage inputs.

49 50 51 52

DBR4 DBR3 DBR2 DBR1

CMOS push-pull

Continued on next page.

Page 9

No. 6472-9/14

LC72348G/W, 72349G/W

Continued from preceding page.

Pin No. Pin I/O Function I/O circuit

System reset input. In CPU operating mode or halt mode, applications must apply a low level for at least

one full machine cycle to reset the system and restart execution with the PC set to location 0. This pin is connected in parallel with the internal power on reset circuit.

53 RES I

Tuning voltage generation circuit outputs. These pins include an n-channel transistor, and a tuning voltage can be generated by

connecting external coil, diode, and capacitor components. FM DC-DC clock switching is a mask option.

54 TU O

N-channel open-drain

FM VCO (local oscillator) input. This pin is selected with the PLL instruction CW1. The input must be capacitor coupled. Input is disabled in backup mode, in halt mode, after a reset, and in PLL stop mode.

56 FMIN I

CMOS amplifier input

AM VCO (local oscillator) input. This pin and the bandwidth are selected with the PLL instruction CW1.

The input must be capacitor coupled. Input is disabled in backup mode, in halt mode, after a reset, and in PLL stop mode.

57 AMIN I

CMOS amplifier input

Main charge pump output. When the local oscillator frequency divided by N is higher than the reference frequency a high level is output, when lower, a low level is output. The pin is set to the high-impedance state when the frequencies match.

Output goes to the high-impedance state in backup mode, in halt mode, after a reset, and in PLL stop mode.

59 EO O

Transistor used for the low-pass filter amplifier. Connect AGND to ground.

60 61 62

AIN AOUT AGND

Power supply pin. This pin must be connected to ground.

This pin must be connected to ground. This pin must be connected to V

—

24 58 55

—

CMOS push-pull

DC-DC clock AM AM local 1/2 FM FM local 1/256 or 75 kHz

CW1 b1, b0 Bandwidth

1 1 0.5 to 10 MHz (MW, LW)

Note 2: When a pin in an I/O switching port is used as an output, applications must first set up the data with an OUT, SPB, or RPB instruction and then set

up output mode with an IOS instruction.

Page 10

Sample Application for Tuning Voltage Generation Circuit

No. 6472-10/14

LC72348G/W, 72349G/W

XIN

XOUT

VDD

FMIN

AMIN

RADIO ON

1/256

1/2

75kHz

Sample Application for Low-Pass Filter Amplifier

10 100 1000 10000

Mask

option

AGND

AOUT

AIN

TU+B

FM mode

mode

Varactor

FM reception mode clock

(75 kHz selected)

AM reception mode

clock frequency range

LC72348 DC-DC converter load: 100 kΩ

VT voltage —V

Clock frequency — kHz

Page 11

LC72340 Series Instruction Set

Terminology

ADDR : Program memory address b : Borrow C : Carry DH : Data memory address High (Row address) [2 bits] DL : Data memory address Low (Column address) [4 bits] I : Immediate data [4 bits] M : Data memory address N : Bit position [4 bits] Rn : Resister number [4 bits] Pn : Port number [4 bits] PW : Port control word number [4 bits] r : General register (One of the addresses from 00H to 0FH of BANK0) ( ), [ ] : Contents of register or memory M (DH, DL) : Data memory specified by DH, DL

No. 6472-11/14

LC72348G/W, 72349G/W

Mnemonic

Operand

Function Operations function

Instruction format

1st 2nd

AD r M Add M to r r ← (r) + (M)

ADS r M Add M to r, then skip if carry r ← (r) + (M), skip if carry

AC r M Add M to r with carry r ← (r) + (M) + C

ACS r M

Add M to r with carry, r ← (r) + (M) + C then skip if carry skip if carry

AI M I Add I to M M ← (M) + I AIS M I Add I to M, then skip if carry M ← (M) + I, skip if carry AIC M I Add I to M with carry M ← (M) + I + C

AICS M I

Add I to M with carry, M ← (M) + I + C, then skip if carry skip if carry

SU r M Subtract M from r r ← (r) – (M)

SUS r M

Subtract M from r, r ← (r) – (M), then skip if borrow skip if borrow

SB r M Subtract M from r with borrow r ← (r) – (M) – b

SBS r M

Subtract M from r with borrow, r ← (r) – (M) – b, then skip if borrow skip if borrow

SI M I Subtract I from M M ← (M) – I SIS M I

Subtract I from M, M ← (M) – I, then skip if borrow skip if borrow

SIB M I Subtract I from M with borrow M ← (M) – I – b

SIBS M I

Subtract I from M with borrow, M ← (M) – I – b, then skip if borrow skip if borrow

fedcba9876543210 010000 DH DL r 010001 DH DL r 010010 DH DL r

010011 DH DL r 010100 DH DL I

010101 DH DL I 010110 DH DL I

010111 DH DL I 011000 DH DL r

011001 DH DL r 011010 DH DL r

011011 DH DL r 011100 DH DL I

011101 DH DL I 011110 DH DL I

011111 DH DL I

Instructions

Continued on next page.

Addition instructionsSubtraction instructions

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Continued from preceding page.

Mnemonic

Operand

Function Operations function

Instruction format

1st 2nd

SEQ r M Skip if r equal to M (r) – (M), skip if zero

SEQI M I Skip if M equal to I (M) – I, skip if zero

SNEI M I Skip if M not equal to I (M) – I, skip if not zero

SGE r M

Skip if r is greater than or (r) – (M), equal to M skip if not borrow

SGEI M I

Skip if M is greater than

(M) – I, skip if not borrow

equal to I

SLEI M I Skip if M is less than I (M) – I, skip if borrow

AND r M AND M with r r ← (r) AND (M)

ANDI M I AND I with M M ← (M) AND I

OR r M OR M with r r ← (r) OR (M)

ORI M I OR I with M M ← (M) OR I

EXL r M Exclusive OR M with r r ← (r) XOR (M)

EXLI M I Exclusive OR M with M M ← (M) XOR I

SHR r Shift r right with carry

LD r M Load M to r r ← (M) ST M r Store r to M M ← (r)

MVRD r M

Move M to destination M

[DH, Rn] ← (M)

referring to r in the same row

MVRS M r

Move source M referring to r

M ← [DH, Rn]

to M in the same row

MVSR M1 M2 Move M to M in the same row [DH, DL1] ← [DH, DL2]

MVI M I Move I to M M ← I

TMT M N

Test M bits, then skip if all bits

if M (N) = all 1s, then skip

specified are true

TMF M N

Test M bits, then skip if all bits

if M (N) = all 0s, then skip

specified are false

JMP ADDR Jump to the address PC ← ADDR CAL ADDR Call subroutine

PC ← ADDR Stack ← (PC) + 1

RT Return from subroutine PC ← Stack

PC ← Stack,

RTI Return from interrupt BANK ← Stack,

CARRY ← Stack

fedcba9876543210 000100 DH DL r 000101 DH DL I 000001 DH DL I

000110 DH DL r

000111 DH DL I 000011 DH DL I

001000 DH DL r 001001 DH DL I 001010 DH DL r 001011 DH DL I 001100 DH DL r 001101 DH DL I

000000001110 r 110100 DH DL r

110101 DH DL r 110110 DH DL r

110111 DH DL r 111000 DH DL1 DL2

111001 DH DL I 111100 DH DL N

111101 DH DL N 1 0 0 ADDR (13 bits)

1 0 1 ADDR (13 bits) 000000001000

000000001001

Bit test

instructions

Jump and subroutine

call instructions

carry

(r)

Comparison instructionsLogic instructionsTransfer instructions

Continued on next page.

Instructions

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Continued from preceding page.

Mnemonic

Operand

Function Operations function

Instruction format

1st 2nd

SS SWR N Set status register (Status W-reg) N ← 1

RS SWR N Reset status register (Status W-reg) N ← 0 TST SRR N Test status register true if (Status R-reg) N = all TSF SRR N Test status register false if (Status R-reg) N = all

TUL N Test Unlock F/F

if Unlock F/F (N) = all 0s, then skip

PLL M Load M to PLL register PLL reg ← PLL data

UCS I Set I to UCCW1 UCCW1 ← I

UCC I Set I to UCCW2 UCCW2 ← I

BEEP I Beep control BEEP reg ← I

DZC I Dead zone control DZC reg ←I TMS I Set timer register Timer reg ← I

IOS PWn N Set port control word IOS reg PWn ← N

IN M Pn Input port data to M M ← (Pn)

OUT M Pn Output contents of M to port P1n ← M

INR M Pn Input port data to M M ← (Pn) SPB P1n N Set port1 bits (Pn)N ← 1 RPB P1n N Reset port1 bits (Pn)N ← 0

TPT P1n N

Test port1 bits, then skip if all bits

if (Pn)N = all 1s, then skip

specified are true

TPF P1n N

Test port1 bits, then skip if all bits

if (Pn)N = all 0s, then skip

specified are false

BANK I Select Bank BANK ← I

LCDA M I

Output segment pattern to LCD

LCD (DIGIT) ← M

LCDB M I

digit direct

LCPA M I

Output segment pattern to LCD

LCD (DIGIT) ← LA ← M

LCPB M I

digit through LA

HALT I Halt mode control

HALT reg ← I, then CPU clock stop

CKSTP Clock stop Stop x’tal OSC

NOP No operation No operation

fedcba9876543210

11111111000

SWR

11111111001

SWR

N 1111111101 SRR N 1111111110 SRR N

000000001101 N 111110 DH DL r

000000000001 I 000000000010 I 000000000110 I 000000001011 I 000000001100 I 11111110 PWn N 111010 DH DL Pn 111011 DH DL Pn 001110 DH DL Pn 00000010 Pn N 00000011 Pn N

11111100 Pn N

11111101 Pn N

000000000111 I

110000 DH DL DIGIT 110001 DH DL DIGIT 110010 DH DL DIGIT 110011 DH DL DIGIT

000000000100 I 000000000101

000000000000

Bank switching

instructions

Status register

instructions

Hardware control

instructions

LCD

instructions

Other

instructions

I/O instructions

Instructions

Page 14

PS No. 6472-14/14

LC72348G/W, 72349G/W

This catalog provides information as of March, 2000. Specifications and information herein are subject to change without notice.

Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer’s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer’s products or equipment.

SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design.

In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law.

No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd.

Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification” for the SANYO product that you intend to use.

Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.