Datasheet LC7215FM, LC7215F, LC7215 Datasheet (SANYO)

Ordering number: EN 3584B

Silicon-gate CMOS LSI

LC7215, 7215F, 7215FM

MW/LW PLL Frequency Synthesizers

Overview

The LC7215, LC7215F and LC7215FM are phase-locked-loop
frequency synthesizer LSIs that provide accurate reference
frequencies over the MW and LW bands, making them ideally
suited for AM tuners.

Features

.

PLL frequency synthesizer LSIs for MW and LW bands.

.

Reference frequencies of 1, 5, 9 and 10 kHz.

.

On-chip transistor for the low-pass filter amplifier.

.

Single output pin (CMOS output)

.

Controller clock output pin.

.

Time-base output pin.

.

All devices can be used for double conversion demodulation.

.

The LC7215F and 7215FM have expanded input frequency
ranges.

LC7215 0.5 to 13 MHz : (DIP14)
LC7215F/FM 0.5 to 20 MHz : (DIP14/MFP14S)

Package Dimensions

unit : mm

3003A-DIP14

[LC7215, 7215F]

SANYO : DIP14

unit : mm

3111-MFP14S

[LC7215FM]

SANYO : MFP14S

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TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN

D2597HA(II)/1291JN/7200JN No.3584-1/7

LC7215, 7215F, 7215FM

Specifications

Absolute Maximum Ratings at Ta = 25°C, VSS=0V

Values in parentheses are for the LC7215F and LC7215FM.

Parameter Symbol Conditions Ratings Unit
Maximum supply voltage V
Input voltage V

Output current I
Output voltage V

Allowable power
dissipation

Operating temperature Topr –40 to +85 °C
Storage temperature Tstg –55 to +125 °C

Note: Voltage that is applied to the resistors when resistors totaling at least 10 kΩ are connected to a pin in series.

Allowable Operating Conditions at VSS=0V

max V

DD

1 All input pins –0.3 to VDD+0.3 V

IN

V

2 CE, CL, DATA (Note) –0.3 to +6.5 V

IN

OUT

1 AOUT –0.3 to +15 V

OUT

V

2 SYC, TB –0.3 to +6.5 V

OUT

V

3 All output pins except V

OUT

DD

AOUT 0 to 5 mA

OUT

1 and V

2 –0.3 to VDD+0.3 V

OUT

–0.3 to +6.5 V

Pd max Ta % 85°C 150 mW

Values in parentheses are for the LC7215F and LC7215FM.

Parameter Symbol Conditions min typ max Unit

V

1V

Supply voltage

DD

V

DD

High-level input voltage V
Low-level input voltage V

V

Output voltage

V

OUT
OUT

f

IN

Input frequency

f

IN

Oscillation guaranteed
crystal oscillator

X’tal XIN, XOUT: CI % 30 Ω 8.00 11.16 12.00 MHz

V

Input amplitude

V

Power supply —

IH
IL

IN

IN

DD

2VDD(Crystal OSC oscillation guaranteed) 3.0 5.5 V

CE, CL, DATA 2.0 VDD1V

CE, CL, DATA 0 0.5 V
1 AOUT 13 V
2 SYC, TB 5.5 V

PIN: Sine wave, capacitive coupling V

1

*S=1

PIN: Sine wave, capacitive coupling V

2

*S=0

PIN: Square wave, capacity connection V

1

*S=1

PIN: Square wave, capacity connection V

2

*S=0

V

: A capacitor of at least 1000 pF

DD,VSS

must be inserted.

DD

DD

(4.5)3.0 (5.5)5.5 V

1,

1,

(2.3)2.3 (20)13 MHz

0.5 2.5 MHz

1,

DD

DD

1,

100 1000 mVrms

100 1000 mVrms

1000 pF

No.3584-2/7

LC7215, 7215F, 7215FM

Electrical Characteristics within the allowable operating ranges

Values in parentheses are for LC7215F and LC7215FM.

Parameter Symbol Conditions min typ max Unit

1 XIN: VI=V

I

High-level input currents

Low-level input currents

High-level output voltages

Low-level output voltages

Output off-state leakage
currents

Tristate output High-level
off-state leakage current

Tristate output Low-level
off-state leakage current

High-level output voltage V
Low-level output voltage V

Supply current

* S, O and P are serial control bits.

IH

I

2 PIN: VI=V

IH

I

3 CE, CL, DATA: VI=V

IH

I

4 AIN: VI=V

IH

1 XIN: VI=V

I

IL

I

2 PIN: VI=V

IL

I

3 CE, CL, DATA: VI=V

IL

I

4 AIN: VI=V

IL

V

1 DOUT: IO=1mA

OH

V

2 PDOUT: IO= 0.5 mA

OH

V

1 DOUT: IO= –1 mA 1.0 V

OL

V

2 PDOUT: IO= –0.5 mA 1.0 V

OL

V

4 SYC, TB: IO= 0.5 mA 1.0 V

OL

V

5 AOUT: IO= 1 mA 1.0 V

OL

I

1 SYC, TB: VO=V

OFF

I

2 AOUT: VO= 13 V 5.0 µA

OFF

I

H PDOUT: VO=V

OFF

I

L PDOUT: VO=V

OFF

3 XOUT: IO= –0.1 mA

OH

3 XOUT: IO= 0.1 mA 1.0 V

OL

I

DD

I

DD

I

DD

V

DD:fIN

1

V

DD:fIN

2

V

DD:VDD

3

DD
DD

DD
DD
SS
SS

SS
SS

DD

DD

SS

1 = 13 MHz, *S = 1 (High speed)

(Note 1)

1 = 20 MHz, *S = 1 (High speed)

f

IN

(Note 1)

1 = 2.5 MHz, *S = 0 (Low speed)

(Note 1)

= 5.5 V, *O = 0, P = 1 (Note 2) 1.2 2.0 mA

V

= 4.5 V, *O = 0, P = 1 (Note 2) 0.7 1.5 mA

DD

V

= 3.0 V, *O = 0, P = 1 (Note 2) 0.4 1.0 mA

DD

V

DD

–1.0
V

DD

–1.0

V

DD

–1.0

20 µA
40 µA

3.0 µA

0.01 1.0 µA
20 µA
40 µA

3.0 µA

0.01 1.0 µA

V

V

3.0 µA

0.01 1.0 nA

0.01 1.0 nA

V

10 mA

(12) mA

5mA

Note 1. V

1=VIN2 = 100 mVms. The 11.16 MHz crystal is connected to XIN and XOUT. All other inputs are connected to V

IN

and all other outputs are open.

2. The 11.16 MHz crystal is connected to XIN and XOUT. All other inputs are connected to V
open. (Backup mode when PLL is halted.)

Pin Assignment

and all other outputs are

DD

No.3584-3/7

SS

Block Diagram

LC7215, 7215F, 7215FM

Pin Description

Name Description

XIN, XOUT 11.16 MHz crystal oscillator connection, feedback

PIN Local oscillator signal input

V

DD,VSS

DATA, CL, CE Data input

DOUT Single bit data output

AIN, AOUT Low-pass filter amplifier

PDOUT Charge pump output

TB

SYC

resistance built-in

Power supply

8 Hz time-base output
60 kHz controller clock output

No.3584-4/7

Data Input

Internal
data

(1) A to N: Divider data

LC7215, 7215F, 7215FM

Input MSB first

(2) O, P: Mode selection

Mode O P DOUT TB Operation
NOR1 0 0 T 8 Hz Normal operation (with PLL operating)

NOR2 0 1 T 8 Hz Normal operation (backup when PLL is halted)
TEST1 1 0 (Device test mode)
TEST2 1 1 (Device test mode)

(3) Q, R: Reference frequency selection

Q R Reference frequency

0 0 9 kHz
0 1 10 kHz
1 0 1 kHz
1 1 5 kHz

(4) S: Programmable divider input sensitivity switch

S = 1: for High speed
S = 0: for Low speed

(5) T: Output to DOUT

T = 1: DOUT = 1
T = 0: DOUT = 0

Example:
Division by 12,420

No.3584-5/7

Data Input Timing

VIH= 2.0 to VDD,VIL=0to0.5V
X’tal = 8.00 to 11.16 (typ) to 12.00 MHz
Data latch: Rising edge of CL

Item Symbol 11.16 MHz crystal Other crystal frequencies Effective value
Enable setup time t
Enable hold time t
Data setup time t
Data hold time t
Clock Low-level time t
Clock High-level time t
Rise time t
Fall time t

ES
EH
SU
HD
LO

HI

R
F

LC7215, 7215F, 7215FM

At least 12 µs At least 2 × (1/fXtal × 62)

↑↑
↑↑
↑↑
↑↑
↑↑

1 µs or less 1 µs or less

↑↑

1/2 of the value

shown at left

No.3584-6/7

(1) Sample Application Circuit

(2) Double-conversion Receiver

LC7215, 7215F, 7215FM

No products described or contained herein are intended for use in surgical implants, life-support systems,
aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like,
the failure of which may directly or indirectly cause injury, death or property loss.

Anyone purchasing any products described or contained herein for an above-mentioned use shall:
1 Accept full responsibility and indemnifyanddefendSANYO ELECTRIC CO., LTD.,its affiliates, subsidiaries and

distributors and all their officers and employees, jointly and severally, against any and all claims and litigation
and all damages, cost and expenses associated with such use:

2 Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on

SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees
jointly or severally.

Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for
volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or
implied regarding its use or any infringements of intellectual property rights or other rights of third parties.

This catalog provides information as of December, 1997. Specifications and information herein are subject to change without notice.

No.3584-7/7