Datasheet LC72147V Datasheet (SANYO)

Ordering number : ENN6675

O1300RM (OT) No. 6675-1/22

Overview

The LC72147V is a PLL frequency synthesizer for car
audio systems. It can implement high-performance
multifunction tuners and features a crystal oscillator
circuit that supports AM up-conversion, a fast locking
circuit, an A/D converter, and an LA1783/1750 IF counter
buffer control pin.

Functions

• High-speed programmable divider
— FMIN: 10 to 180 MHz: Pulse swallower type

• IF counter
— HCTR: 0.4 to 25 MHz: Frequency measurement

• Crystal oscillator: One of the following 4 frequencies

may be selected: 10.35, 10.25, 7.2, and 4.5 MHz

Reference frequency

— One of 12 frequencies may be selected (when a 7.2

or 4.5 MHz crystal is used)
100*1, 50, 30*2, 25, 12.5, 6.25, 3.125, 10, 9*2, 5, 3*2,
1 kHz
Notes: 1.

Cannot be used when a 10.35 or 10.25 MHz
crystal is used

2.

Cannot be used when a 10.25 MHz crystal
is used

• Phase comparator
— Supports dead band control
— Built-in unlock detection circuit
— Sub-charge pump for fast locking
— Built-in deadlock clearing circuit

• Built-in MOS transistor for forming an active low-pass

filter

• I/O ports — General-purpose I/O: 5 pins
— Output: n-channel: 3 pins, CMOS: 2 pins
— IFBC pin (LA1783/1750 IF counter buffer control

pin)

• Serial data I/O
— Supports communication with the controller in the

CCB format.

• Operating ranges
— Supply voltage (VDD): 4.5 to 6.5 V
— Built-in regulator voltage (Vreg): 3.0 V (±10%)
— Operating temperature: –40 to +85°C

• Package
— SSOP-24

Package Dimensions

unit: mm

3175A-SSOP24

112

13

7.6

8.0

0.5

5.6

0.1

1.6max

1.0

24

0.65

0.22

0.43

0.15

SANYO: SSOP24

[LC72147V]

LC72147V

SANYO Electric Co.,Ltd. Semiconductor Company

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN

PLL Frequency Synthesizer for Electronic Tuning

in Car Audio Systems

CMOS IC

Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.

SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.

• CCB is a trademark of SANYO ELECTRIC CO., LTD.

• CCB is SANYO’s original bus format and all the bus
addresses are controlled by SANYO.

Pin Assignment

No. 6675-2/22

LC72147V

I/O-5

HCTR

14 13

12

15161718192021222324

1 2 3 4 5 6 7 8 9 10 11

XOUT

IFBC

I/O-1

I/O-2

ADC0

ADC1

DO

CL

DI

CE

I/O-3

I/O-4

FMIN

XIN

Vreg

XBUF

AIN

PD

V

SS

V

DD

AV

SS

AOUT

Block Diagram

XBUF

PD

ADC1

ADC0

HCTR

AOUT

AIN

AV

SS

CE

FMIN

XOUT

XIN

DI

CL

DO

V

SS

V

DD

14 bits PROGRAMMABLE

REFERENCE

12 bits PROGRAMMABLE

DIVIDER

UNIVERSAL

COUNTER

PHASE DETECTOR

CHARGE PUMP

A/D

CONVERTER

DATA SHIFT REGISTER

LATCH

VOLTAGE

REGULATOR

3 V

POWER ON

RESET

CCB

I/F

SWALLOW COUNTER

1/16, 1/17 4 bits

1

24

12

23

15

7

PDS

10

9

22

21

20

4

6

5

16

17

2

11

13

I/O-5I/O-4I/O-3I/O-2I/O-1Vreg

3

8

18

19

14

IFBC

No. 6675-3/22

LC72147V

Parameter Symbol Pin Conditions Ratings Unit

Supply voltage V

DD

max V

DD

–0.3 to +7.0 V

V

IN

1 max CE, CL, DI, AIN –0.3 to +7.0

Maximum input voltage V

IN

2 max XIN, FMIN, HCTR, I/O-4, I/O-5, ADC0, ADC1 –0.3 to Vreg + 0.3 V

V

IN

3 max I/O-1 to I/O-3 –0.3 to +15

V

O

1 max DO –0.3 to +7.0

Maximum output voltage V

O

2 max XOUT, IFBC, I/O-4, I/O-5, PD, XBUF –0.3 to Vreg + 0.3 V

V

O

3 max I/O-1 to I/O-3, AOUT –0.3 to +15

I

O

1 max IFBC 0 to 1.0

I

O

2 max I/O-4, I/O-5, XBUF 0 to 3.0

Maximum output current I

O

3 max DO 0 to 6.0 mA

I

O

4 max I/O-1 to I/O-3 0 to 10

I

O

5 max AOUT 0 to 35
Allowable power dissipation Pd max Ta ≤ 85°C 150 mW
Operating temperature Topr –40 to +85 °C
Storage temperature Tstg –55 to +125 °C

Specifications

Absolute Maximum Ratings at Ta = 25°C, VSS= 0 V

Note: Power supply VDD- VSS, Vreg - VSS: Capacitors of at least 2000 pF must be inserted between these pins when this device is used.

Parameter Symbol Pin Conditions

Ratings

Unit

min typ max

Supply voltage

V

DD

1V

DD

4.5 6.5
V

V

DD

2V

DD

Serial data retention voltage 2.5

Regulator output voltage Vreg Vreg 4.5 ≤ V

DD

≤ 6.5 V 2.7 3.0 3.3 V

V

IH

1

CE, CL, DI,

2.2 6.5
VHigh-level input voltage

I/O-1 to I/O-3

V

IH

2 I/O-4, I/O-5 2.2 Vreg

Low-level input voltage V

IL

CE, CL, DI,

0 0.8 V

I/O-1 to I/O-5

Output voltage

VO1 DO 0 6.5

V

V

O

2 I/O-1 to I/O-3 0 13

f

IN

1 XIN Sine wave, capacitance coupled 1.0 8.0

Input frequency f

IN

2 FMIN Sine wave, capacitance coupled 10 180 MHz

f

IN

3 HCTR Sine wave, capacitance coupled 0.4 25

Guaranteed crystal oscillator

X’tal1 XIN, XOUT *1 4.0 7.0

MHz

frequency ranges

X’tal2 XIN, XOUT *1 7.1 10.5

V

IN

1 XIN 200 900

V

IN

2-1 FMIN 10 ≤ f < 130 MHz *2 40 900

Input amplitude V

IN

2-2 FMIN 130 ≤ f ≤ 180 MHz *2 70 900 mVrms

V

IN

3-1 HCTR 0.4 ≤ f ≤ 25 MHz *3 70 900

V

IN

3-2 HCTR 8 ≤ f ≤ 12 MHz *4 100 900

Input voltage range V

IN

4 ADC0, ADC1 0 Vreg V

Data setup time t

SU

DI, CL *5 0.45 µs

Data hold time t

HD

DI, CL *5 0.45 µs

Clock low-level period t

CL

CL *5 0.45 µs

Clock high-level period t

CH

CL *5 0.45 µs

CE wait time t

EL

CE, CL *5 0.45 µs

CE setup time t

ES

CE, CL *5 0.45 µs

CE hold time t

EH

CE, CL *5 0.45 µs

Data latch change time t

LC

*5 0.45 µs

Data output time

t

DC

DO, CL

Depends on the value of the pull-up

0.2 µs

t

DH

DO, CE

resistor used.

Allowable Operating Ranges at Ta = –40 to 85°C, VSS= 0 V

Notes:1. Recommended crystal oscillator CI values

CI ≤ 120 Ω (Crystal: 4.5 MHz), CI ≤ 70 Ω (Crystal: 7.2, 10.25, or 10.35 MHz)
Note that the crystal oscillator circuit characteristics depend on the printed circuit board and the particular components used. We recommend
consulting the manufacturer of the crystal when designing this circuit.

2. Refer to the description of the structure of the programmable divider.

3. Serial data: CTC = 0

4. Serial data: CTC = 1

5. See the timing chart for serial data transfers.

No. 6675-4/22

LC72147V

Parameter Symbol Pin Conditions

Ratings

Unit

min typ max

Rf1 XIN 1.0 MΩ

Internal feedback resistance Rf2 FMIN 500

kΩ

Rf3 HCTR 250

Hysteresis V

HIS

CE, CL, DI 0.1 Vreg V

V

OH

1 I/O-4, I/O-5

I

O

= – 0.5 mA Vreg – 0.5

I

O

= – 1 mA Vreg – 1.0

V

High-level output voltage V

OH

2 PD, AIN

I

O

= – 1 mA Vreg – 0.5

I

O

= – 2 mA Vreg – 1.0

V

OH

3 XBUF IO= – 0.5 mA Vreg – 0.5 V

V

OH

4 IFBC IO= – 0.1 mA Vreg – 0.5 V

VOL1 I/O-4, I/O-5

I

O

= 0.5 mA 0.5

V

I

O

= 1 mA 1.0

V

OL

2 PD, AIN

I

O

= 1 mA 0.5

V

I

O

= 2 mA 1.0

V

OL

3 XBUF IO= 0.5 mA 0.5 V

Low-level output voltage

V

OL

4 IFBC IO= 0.1 mA 0.5 V

I

O

= 1 mA 0.2

V

OL

5 I/O-1 to I/O-3

I

O

= 2.5 mA 0.5

V

I

O

= 5 mA 1.0

I

O

= 9 mA 1.8

V

OL

6DO IO= 5 mA 1.0 V

V

OL

7 AOUT IO= 30 mA, AIN = 2.0 V 1.5 V

Mid-level output voltage V

OM

IFBC IO= 20 µA 1.2 1.5 1.8 V

I

IH

1 CE, CL, DI VI= 6.5 V 5.0

I

IH

2 I/O-1 to I/O-3 VI= 13 V 5.0

I

IH

3

I/O-4, I/O-5, ADC0,

VI= Vreg 5.0

µA

High-level input current

ADC1, HCTR

I

IH

4 XIN VI= Vreg 1.3 7

I

IH

5 FMIN VI= Vreg 2.5 14

I

IH

6 HCTR VI= Vreg 5.0 28

I

IH

7 AIN VI= Vreg 200 nA

I

IL

1 CE, CL, DI VI= 0 V 5.0

I

IL

2 I/O-1 to I/O-3 VI= 0 V 5.0

I

IL

3

I/O-4, I/O-5,

VI= 0 V 5.0

µA

Low-level input current

ADC0, ADC1, HCTR

I

IL

4 XIN VI= 0 V 1.3 7

I

IL

5 FMIN VI= 0 V 2.5 14

I

IL

6 HCTR VI= 0 V 5.0 28

I

IL

7 AIN VI= 0 V 200 nA

Output off leakage current

I

OFF

1 I/O-1 to I/O-3 VO= 13 V 5.0

µA

I

OFF

2DO VO= 6.5 V 5.0

High-level 3-state off leakage current

I

OFFH

PD VO= Vreg 0.01 200 nA

Low-level 3-state off leakage current

I

OFFL

PD VO= 0 V 0.01 200 nA

Input capacitance C

IN

FMIN 6PF
A/D converter linearity error Err ADC0, ADC1 –1/2 1/2 LSB
Pull-down transistor on resistance Rpd FMIN 80 200 600 kΩ

X’tal = 10.35 MHz
f

IN

2 = 180 MHz

Supply current I

DD

V

DD

VIN2 – 2 = 70 mVrms 12 mA
f

IN

3 = 25 MHz

V

IN

3 – 1 = 70 mVrms

Electrical Characteristics in the Allowable Operating Ranges

No. 6675-5/22

LC72147V

Pin Functions

Pin No. Symbol Usage Function Pin circuit

• Crystal oscillator connection.
(4.5, 7.2, 10.25, or 10.35 MHz)

1

24

XIN

XOUT

X’tal OSC

• FMIN is selected by setting DVS in the control data to 1.

• Input frequency: 10 to 180 MHz

• The signal is transmitted to the swallow counter.

• The divisor can be set to a value in the range 272 to 65,535.

12 FMIN Local oscillator signal input

• This pin must be set to the high level when inputting serial data to the
LC72147V DI pin and when outputting serial data from the DO pin.

23 CE Chip enable

S

• Data synchronization clock signal used when inputting serial data to
the LC72147V DI pin and when outputting serial data from the DO pin.

21 CL Clock

S

• Serial data input for transferring data from the controller to the
LC72147V.

22 DI Input data

S

• Serial data output for transferring data from the LC72147V to the
controller.

20 DO Output data

• LC72147V power supply. A voltage in the range 4.5 to 6.5 V must be
provided when the PLL circuit is operating.

• The power-on reset circuit operates when power is first applied.

———

———

———

4

V

DD

Power

• Regulator output. A capacitor must be inserted between Vreg and
V

SS

.

• The output voltage (3.0 V ±10%) is supplied to internal circuits.

5 Vreg Regulator output

• LC72147V ground.6

V

SS

Ground

• The LC72147V can control the LA1783/1750 IF buffer output.

• This is a 3-state output. (0 V, Vreg/2 = 1.5 V, and Vreg = 3 V)

14 IFBC IF buffer control

• General-purpose I/O ports.

• The outputs are open-drain circuits.

• After the power-on reset, I/O-1 and I/O-2 function as input ports. I/O­3 functions as an output port fixed at the low level.

• The input/output state of these ports can be set using the I/O-1 to
I/O-3 bits in the serial data sent from the controller.

16
17

2

I/O-1
I/O-2
I/O-3

General-purpose I/O ports

Continued on next page.

No. 6675-6/22

LC72147V

Continued from preceding page.

Pin No. Symbol Usage Function Pin circuit

• General-purpose I/O ports.

• The outputs are complementary output circuits.

• After the power-on reset, these ports function as input ports.

• The input/output state of these ports can be set using the I/O-4 and
I/O-5 bits in the serial data sent from the controller.

11
13

I/O-4
I/O-5

General-purpose I/O ports

• A/D converter input
The A/D converter is a 6-bit successive-approximation circuit.
See the item on the structure of the A/D converter for details.

18
19

ADC0
ADC1

A/D converter input

• PLL charge pump output
When the frequency created by dividing the local oscillator signal

frequency by N is higher than the reference frequency, a high level is
output from the PD pin. When lower, a low level is output. The PD pin
goes to the high-impedance state when the frequencies match.

7 PD Charge pump output

• HCTR is selected by setting CTS in the control data to 1.
Input frequency: 0.4 to 25 MHz
The signal is input to a divide-by-2 circuit and the result is input to a

general-purpose counter. This counter can also be used as an
integrating counter.

The counter value is output as the result of the count, MSB first, from
the DO pin.

See the item describing the structure of the general-purpose counter
for details.

15 HCTR General-purpose counter

• Output buffer for the crystal oscillator circuit

• When XB in the serial data is set to 1, the output buffer operates and
the crystal oscillator signal (a pulse signal) is output.

When XB is 0, XBUF outputs a low level.
(After the power-on reset, XB is set to 0 and the output buffer is fixed

at the low level.)

3 XBUF Crystal oscillator buffer

XOUT

Serial Data I/O Methods

Data is input to and output from the LC72147V using the Sanyo CCB (Computer Control Bus) format, which is the serial
bus format used by Sanyo audio ICs. This IC adopts a CCB format with an 8-bit address.

No. 6675-7/22

LC72147V

I/O mode

Address

Content

B0 B1 B2 B3 A0 A1 A2 A3

• Control data input (serial input) mode.

[1] IN1 (82) 0 0 010010

• 32 bits of data are input.

• See the “DI Control Data (Serial Data Input) Structure” item for details on the content of
the input data.

• Control data input (serial input) mode.

[2] IN2 (92) 1 0 010010

• 32 bits of data are input.

• See the “DI Control Data (Serial Data Input) Structure” item for details on the content of
the input data.

• Data output (serial data output) mode.

[3] OUT (A2) 0 1 010010

• The number of bits output is equal to the number of clock cycles.

• See the “DO Output Data (Serial Data Output) Structure” item for details on the content
of the output data.

CE

CL

DI

DO

I/O mode determined

A3A2A1A0B3B2B1B0

First data

in1/2

First data

out

DI control data (serial data input) structure

(1) IN1

No. 6675-8/22

LC72147V

(5) ADC

(2) PD-C

(4) DO-C

(3) R-CTR

(1) P-CTR

(6) U-CTR

P7

P6

P5

P4

P3

P2

P1

P0

0010100DI 0

First data IN1

Address

P15

P14

P13

P12

P11

P10

P9

P8

R3

R2

R1

R0

PDC1

PDC0

DVS

*

GT1

GT0

CTS

*

CTE

ADS

DT1

DT0

(2) IN2

Address

(5) ADC

(13) PD-L

(8) O-PORT

(6) U-CTR

(10) UNLOCK

(11) XTAL

(4) DO-C

(12) DZ-C

(9) IFB-C

(9) IFB-C

(7) I/O-C

(14) TEST

ADI1

ADI0

I/O-5

I/O-4

I/O-3

I/O-2

I/O-1

IFB0

0010100DI 1

First data IN2

CTC

CTP

OUT5

OUT4

OUT3

OUT2

OUT1

IFB1

XS0

UL1

UL0

ULD

IL1

IL0

*

*

DLC

TEST2

TEST1

TEST0

DZ1

DZ0

XB

XS1

*: Don't care

No. 6675-9/22

LC72147V

DI control data description

No. Control block/data Content Related data

• This data sets the divisor for the programmable divider
P0 is the LSB, and P15 is the MSB of this binary value.
DVS = 0: The FMIN pin is pulled down.

1: Selects the FMIN pin.
Divisor setting (N): 272 to 65,536
Input frequency range: 10 to 180 MHz

*: See the “Programmable Divider Structure” item for details.

(1)

Programmable divider data

P0 to P15

DVS

• This data controls the sub-charge pump.

(* : don’t care)

*: The sub-charge pump output is connected internally to the gate of the transistor used for

low-pass filter formation. The sub-charge pump can be used in conjunction with the PD
pin (main charge pump pin) to form a high-speed locking circuit.

See the “Charge Pump Structure” item for details.

UL0, UL1, DLC(2)

Sub-charge pump control data

PDC0, PDC1

• Reference frequency selection data

Notes: 1. Illegal value when a crystal oscillator frequency of 10.25 or 10.35 MHz is selected.

2. Illegal value when a crystal oscillator frequency of 10.25 MHz is selected.

3. PLL inhibit (backup mode)
The programmable divider block is stopped, the FMIN pin is pulled down to ground, and
the charge pump output is set to the floating state.

(3)

Reference divider data

R0 to R3

PDC1 PDC0 Sub-charge pump state

0 * High impedance
1 0 Charge pump operating (PLL unlocked)
1 1 Charge pump operating (normal operation)

R3 R2 R1 R0 Reference frequency (kHz)

0 0 0 0 100 *

1

0001 50
0010 25
0011 25
0 1 0 0 12.5
0 1 0 1 6.25
0 1 1 0 3.125
0 1 1 1 3.125
1000 10
1001 9 *

2

1010 5
1011 1
1100 3 *

2

1101 30 *

2

1110*3PLL inhibit + X’tal OSC stop
1111*

3

PLL inhibit

Continued on next page.

No. 6675-10/22

LC72147V

Continued from preceding page.

No. Control block/data Content Related data

• Data that determines the output of the DO and I/O-5 pins

end-AD: A/D converter operation completion
end-UC: General-purpose counter operation completion

However, if I/O-1 and I/O-2 are set to output mode, they go to the open state.
Note: 2. Invalid if the I/O-5 pin is set to input mode.

Caution: Cannot be used in crystal oscillator stop mode (The DO pin will not change state.)

[When the reference divider data is R3 = R2 = R1 = 1, and R0 = 0.]

(4)

DO, I/O-5 pin control data

ULD

DT0, DT1

IL0, IL1

OUT5

I/O-1
I/O-2
I/O-5

• A/D converter conversion start data
ADS = 1: Resets and starts the A/D converter
ADS = 0: Resets the A/D converter

If both the ADC0 and ADC1 pins are specified as A/D converter inputs, the levels are
converted sequentially in the order ADC0 first and the ADC1. See the “A/D Converter
Structure” item for details.

(5)

A/D converter control data

ADS
ADI0
ADI1

ULD DT1 DT0 DO pin I/O-5 pin

0 0 0 Low when unlocked
0 0 1 end-AD

OUT5 *

2

0 1 0 end-UC
011 IN *

1

1 0 0 Open
1 0 1 end-AD

Low when unlocked *

2

1 1 0 end-UC
111 IN *

1

IL1 IL0 IN

0 0 Open
0 1 I-1 (pin state)
1 0 I-2 (pin state)
1 1 DO goes low when I-1 changes. *

ADI1 ADI0 A/D converter input pin

1 1 Stopped
1 0 ADC0
0 1 ADC1
0 0 ADC0, ADC1

Continued on next page.

Note: 1.

DO

Completion (I-1 change)Start

CE : Hi

No. 6675-11/22

LC72147V

No. Control block/data Content Related data

• Selects the general-purpose counter input pin (HCTR).
CTS = 1: Selects the HSTR pin.
CTS = 0: Pulls down the HCTR pin.

• General-purpose counter measurement start data
CTE = 1: Starts the counter.
CTE = 0: Resets the counter.

• Determines the measurement time (frequency mode) and number of periods (period
mode).

• CTP = 0: When the counter has been reset (CTE = 0), pulls down the general-purpose

counter input.

CTP = 1: When the counter has been reset (CTE = 0), does not pull down the general-

purpose counter input, and shortens the wait time.

However, immediately after CTP is set to 1, the counter start must be delayed
until the general-purpose counter input pin has been biased.

• The input sensitivity is reduced when CTC is set to 1. (Sensitivity: 10 to 30 mV rms)

(6)

General-purpose counter

control data

CTS, CTE

GT0, GT1

CTP

CTC

• Data that specifies the I/O direction of the I/O ports.
[Data] = 0: Input port

1: Output port

*: After the power-on reset, the I/O-1, I/O-2, I/O-4, and I/O-5 are set up as input ports. I/O-3

is set up as an output port.

OUT1 to OUT5

ULD

(7)

I/O port control data

IO-1 to I/O-5

• Data that determines the output from output ports O-1 to O-5.
[Data] = 1: Open or high level.

0: Low

*: Invalid when the corresponding port is set up as an input port or as the unlock state

indicator output.

I/O-1 to I/O-5

ULD

(8)

Output port data

OUT1 to OUT5

• Determines the 3-value output of the IFBC port.

*: When PLL inhibit and crystal oscillator stop mode (R0 = 0, R1 = R2 = R3 = 1), the IFBC

output is set to the open state. This output goes to the mid level after the power-on reset.

(9)

IFBC port control data

IFB0, IFB1

Continued from preceding page.

Frequency measurement

Period measurement

GT1 GT0

Measurement time

Wait time

mode

CTP = 0 CTP = 1
0 0 4 ms 3 to 4 ms 1 to 2 ms One period
0 1 8 3 to 4 ms 1 to 2 ms One period
1 0 32 7 to 8 ms 1 to 2 ms Two periods
1 1 64 7 to 8 ms 1 to 2 ms Two periods

IFB0 IFB1 IFBC output

0 0 Mid (Vreg/2 = 1.5 V)
0 1 Low (0 V)
1 0 Mid (Vreg/2 = 1.5 V)
1 1 High (Vreg = 3.0 V)

Continued on next page.

No. 6675-12/22

LC72147V

Continued from preceding page.

No. Control block/data Content Related data

• Width selection for the phase error (øE) detection function used to determine the PLL
locked/unlocked state. When a phase error greater than the øE detection width from the
table occurs, the PLL circuit is seen as in the unlocked state. When unlocked, the
detection pin (DO or I/O-5) goes to the low state.

ULD

DT0, DT1

(10)

Unlock state detection data

UL0, UL1

• Crystal oscillator selection data

*: After the power-on reset, 10.25 MHz is selected.

• Crystal oscillator buffer (XBUF) output control data
XB = 0: Buffer output is turned off. (This mode is selected after the power-on reset.)
XB = 1: Buffer output is turned on.

R0 to R3(11)

Crystal oscillator circuit

XS0, XS1

XB

• Controls the phase comparator dead band.

*: The phase comparator operates in DZA mode after the power-on reset.

(12)

Phase comparator control data

DZ0, DZ1

• Bit that forcible sets the charge pump output to the low level.
DLC = 1: Low level
DLC = 0: Normal operation

*: If a deadlock occurs due to the VCO control voltage (Vtune) going to zero and stopping

the VCO oscillator, set the charge pump output to the low level and set Vtune to V

CC

to

escape from the deadlocked state. Normal operation is selected after the power-on reset.

(13)

Charge pump control data

DLC

• IC test control data
These bits must be set as follows during normal operation.
TEST0 = 0
TEST1 = 0
TEST2 = 0

*: After the power-on reset, the test data is all set to zero.

(14)

IC test data

TEST0
TEST1
TEST2

UL1 UL0 øE detection width Detection pin output

0 0 Stopped Open
0 1 0 øE is output directly
1 0 ±0.5 µs øE is extended by 1 to 2 ms.
1 1 ±1 µs øE is extended by 1 to 2 ms.

XS1 XS0 X’tal OSC

0 0 4.5 MHz
0 1 7.2 MHz
1 0 10.25 MHz
1 1 10.35 MHz

DZ1 DZ0 Dead band mode

0 0 DZA
0 1 DZB
1 0 DZC
1 1 DZD

øE

D0

I/O5

1 to 2 ms

Unlocked state output

Extended

Structure of the DO Output Data (serial output data)

(3) OUT

No. 6675-13/22

LC72147V

(1) IN-PORT

(2) U-CTR

(4) ADC1

(3) ADC0

I1

I2

I3

I4

I5

*

*

*

*

*

*

*

*

*

*

*

0010101DI

DO

0

First data out

Address

C12

C13

C14

C15

C16

C17

C18

C19

C4

C5

C6

C7

C8

C9

C10

C11

C0

C1

C2

C3

AD01

AD02

AD03

AD04

AD05

AD14

AD15

AD13

AD10

AD11

AD12

AD00

No. Control block/data Content Related data

• The bits I1 to I5 are set to the latched states of the I/O pins I/O-1 to I/O-5. These states
are latched at the point the IC enters data output mode.

The pin states are latched regardless of the pin mode (input or output).
Pin state =high: 1

low: 0

I/O-1 to I/O-5(1)

I/O port data

I5 to I1

• The bits C19 to C0 are set to the latched content of the 20-bit binary general-purpose
counter.

C19 ← MSB of the binary counter
C0 ← LSB of the binary counter

CTS0
CTS1

CTE

(2)

General-purpose

counter binary data

C19 to C0

• The bits AD05 to AD00 are set to the latched result of the A/D conversion of the ADC0
pin input signal.

AD05 ← MSB
AD00 ← LSB

ADI0
ADI1
ADS

(3)

A/D converter ADC0 data

AD05 to AD00

• The bits AD15 to AD10 are set to the latched result of the A/D conversion of the ADC1
pin input signal.

AD15 ← MSB
AD10 ← LSB

ADI0
ADI1
ADS

(4)

A/D converter ADC1 data

AD15 to AD10

*: Bits that are set to 0.

Serial data input (IN1/IN2) tSU, tHD, tES, tEC, tEH, > 0.45 µs tLC< 0.45 µs

No. 6675-14/22

LC72147V

DI

Internal data

CE

CL

t

LC

t

HD

t

ES

t

EC

t

EH

t

SU

P0 P1 P2 P3

A3A2A1A0B3B2B1B0

*

CTS GT0 GT1

Serial data output (OUT) tSU, tHD, tES, tEC> 0.45 µs tDC, tDH< 0.2 µs

*1

DO

DI

CE

CL

t

DH

t

HD

t

DC

t

ES

t

EC

t

EH

t

SU

I4I5*2

*2

A3A2A1A0B3B2B1B0

AD10AD13 AD12 AD11

Notes: 1. The DO pin is an n-channel open drain output, and thus the data switching time will differ depending on the value of the pull-up resistor used and

the printed circuit board capacitance.

2. The DO pin is normally open.

No. 6675-15/22

LC72147V

Serial data timing

t

CL

t

EH

t

ES

t

HD

t

SU

t

LC

t

EL

t

CH

V

IH

V

IH

V

IH

V

IL

V

IL

V

IH

V

IH

V

IH

V

IL

V

IL

V

IL

Old New

Internal data
latch operation

CL

DI

CE

<When CL is stopped at the low level>

<When CL is stopped at the high level>

t

CL

t

EH

t

ES

t

HD

t

SU

t

LC

t

DH

t

DC

t

EL

t

CH

Old New

Internal data
latch operation

DO

CL

DI

CE

V

IH

V

IH

V

IH

V

IH

V

IL

V

IL

V

IH

V

IL

V

IL

V

IL

V

IH

Programmable divider structure

General-purpose counter structure

The LC72147V’s general-purpose counter is a 20-bit binary counter.
The result of the count operation can be read out MSB first from the DO pin.

The measurement time when the general-purpose counter is used for frequency measurement is set to either 4, 8, 32, or
64 ms by the GT0 and GT1 bits. The frequency of the input to the HCTR pin can be measured by determining how many
pulses were input to the general-purpose counter during this measurement time.

No. 6675-16/22

LC72147V

4 bits 12 bits

Programmable

divider

Swallow

counter

øE

fvco/N

PD

ferf

fvco = ferf × N

FMIN

DVS

0 to 3 4 to 7 8 to 11

12 to 15 16 to 19

(FIF )

GT

GT1, GT0

M

S
B

L
S

B

CT

DO pin

General-purpose counter

(20-bit binary counter)

C = FIF × GT

CTS

HCTR

1
2

4/8/32/64

msec

DVS Set divisor (N)

Input frequency range (f(MHz))

FMIN

Minimum input sensitivity

1 272 to 65535

10 ≤ f < 130 130 ≤ f ≤ 180

Selected

40 mVrms 70 mVrms

0 — — — Pulled down

Check signal frequency

X’tal OSC 4.5 MHz 7.2 MHz 10.25 MHz

10.35 MHz

fref = 30, 9, 3 kHz

fref : other than 30, 9, 3 kHz

Check signal 900 kHz 900 kHz 1025 kHz 1030 kHz 1150 kHz

The CTC data switches the input sensitivity. The input sensitivity is reduced when CTC is set to 1.

CTC

HCTR: Minimum input sensitivity rating

0.4 ≤ f < 8 8 ≤ f < 12 12 ≤ f < 25

0 (Normal mode) 70 mVrms

70 mVrms

70 mVrms

(10 to 20 mVrms)

1

(Reduced sensitivity mode)

—

100 mVrms

—

(30 to 40 mVrms)

—: No sensitivity rating (not guaranteed)
( ): Rated value (reference value)

CTP data: Determines the state of the general-purpose counter input pin (HCTR) when the general-purpose counter is

reset (CTE = 0).
CTP = 0: The general-purpose counter input pin is pulled down.

1: The general-purpose counter input pin is not pulled down, and the wait time is shortened by 1 to 2 ms.
IF CTP is to be set to 1, set CTP to 1 at least 4 ms before the counter is started by setting CTE to 1.
Leave CTP set to 0 if the counter will not be used.

IF counter operation

Reset the general-purpose counter in advance by setting CTE to 0 before starting the counter.
A general-purpose counter count operation is started by setting the CTE bit in the serial data to 1. The serial data takes
effect internally to the LC72147V when the CE pin input level is changed from high to low. The input to the HCTR pin
must be provided before the wait time has elapsed after CE was set low.
Next, the result of the general-purpose counter count after the measurement completes must be read out while CTE is still
set to 1. This is because the general-purpose counter is reset when CTE is set to 0.
Note that the signal input to the HCTR pin is first divided by 2 internally to the IC and then input to the general-purpose
counter. Therefore, the result of the general-purpose counter count is a value that corresponds to 1/2 of the frequency
actually input to the HCTR pin.

When used as an integrating counter

No. 6675-17/22

LC72147V

Frequency measurement mode

GT1 GT0

Measurement time

Wait time

CTP = 0 CTP = 1

0 0 4 ms

3 to 4 ms

0 1 8 ms

1 to 2 ms

1 0 32 ms

7 to 8 ms

1 1 64 ms

CE

HCTR

Frequency
measurement
time

Data with
CTE = 1

Wait time

Measurement time

Input signal

At least 70 mV rms
*: When CTC = 0: 70 mV rms
When CTC = 1: 100 mV rms

Reset

Start

Restart

(Integrates)

• Resets the general-purpose counter

• Starts the general-purpose counter

• Restarts the counter if set to 1 again.

CE

Internal data
latch (CTE)

GT

General-purpose
counter

End of the count operation End of the count operation

end-UC

(DO)

1 →

*CTE: 0 →

CTE = 0*CTE = 1*CTE = 1*

In integrating count mode, the count value of the general-purpose counter is accumulated. Care must be taken to handle
counter overflow correctly. The count value will be in the range 0Hto FFFFFH.
An integrating count operation is performed by sending the serial data (IN1) again with the CTE bit still set to 1. This
restarts the general-purpose counter measurement operation and adds the new counts to the previous counter value.

No. 6675-18/22

LC72147V

A/D converter structure

The LC72147V A/D converter is a 6-bit successive-approximation converter. It features a conversion time of about
17 µs. The full-scale voltage level is the Vreg level, which corresponds to a data value of 3FH.

ADC1

Selector

Comparator

Discrimination
circuit

Selector

Decoder

Do pin

Register

*: These bits are always 0.

ADC0

ADI0 ADI1

ADS

Vref max = Vreg

AD04

*

*

*

*

AD05

Vref

AD02

AD03

AD13

AD14

AD15

AD00

AD01

AD10

AD11

AD12

CE

Conversion

Conversion starts

Conversion completes

ADC1

CTS = 1

ADC0

tWA1 : 0.5 to 2.0 µs
tAW2 : 1.0 to 2.2 µs
tAD : 7.3 to 16.7 µs

end-AD

t

WA

1

t

WA

2

t

AD

t

AD

ADI1 ADI0 Input pin

1 1 Illegal setting
1 0 ADC0
0 1 ADC1
0 0 ADC0/ADC1

Charge pump structure

When the unlocked state is detected when the channel is changed, the PDS (sub-charge pump) operates, R1 goes to
RIM/R1S (R1S = 100 Ω), the low-pass filter time constant is reduced, and PLL locking is accelerated.

*: The unlock state detection bit UL1 must be set to 1. The unlock detection width is set to either ±0.5 µs or ±1.0 µs and

when a phase difference larger than this is detected, the unlocked state is recognized and the sub-charge pump
operates. When the state approaches the locked state and the phase difference becomes less than the amount set as the
unlock detection width, the sub-charge pump stops operating and the pin goes to the high-impedance state.

Other items

(1) Notes on the phase detector dead band

When the charge pump operates in ON/ON mode, the charge pump generates correction pulses even when the PLL is
locked. Here, it is easy for the loop to become unstable, and special care is required in designs that use this mode.
The following problems may occur in ON/ON mode.

• Side bands may be generated due to reference frequency leakage.

• Side bands may be generated due low-frequency leakage due to the envelope of the correction pulses.

No. 6675-19/22

LC72147V

(MAIN)

(SUB)

R1S

PDS

PD0

fvco/N

Phase
Detector

Unlock
detector

and
subcharge
pump cont

fref

Clock

Unlock

DZ0

UL0
UL1

PDC0

PDC1

DO, I/O-5 pin

DLC

DZ1

AIN

AOUT

AV

SS

PD0

PDS

V

CC

R1M

R1S

Vtune

PDC1 PDC0 PDS (Sub-charge pump state)

0 * High impedance
1 0 Charge pump operating (PLL unlocked)
1 1 Charge pump operating (normal operation)

DLC PD1, PD0, PDS

0 Normal operation
1 Forcibly set to the low level

DZ1 DZ0 Dead band mode Charge pump Dead band

0 0 DZA ON/ON – –0 s
0 1 DZB ON/ON –0 s
1 0 DZC OFF/OFF +0 s
1 1 DZD OFF/OFF ++0 s

When a dead band is present (OFF/OFF mode), the loop will be stable, but it will be harder to acquire a good C/N ratio.
On the other hand, with the mode that does not have a dead band (ON/ON mode), it will be easier to acquire a high C/N
ratio, but harder to acquire loop stability.
Therefore, the DZA and DZB modes, in which there is no dead band, can be effective if either a high signal-to-noise ratio
of 90 to 100 dB in FM reception or an increased pilot margin in AM stereo reception is required.
Inversely, if such a high FM signal-to-noise ratio is not required for FM reception, or an adequate pilot margin can be
acquired for AM stereo reception, then the DZC and DZD modes, in which a dead band is present, may be more
effective.

Dead zone (dead band) definition

The phase comparator compares fp with the reference frequency (fr) as shown in figure 1. This circuit outputs a voltage
V (A) that is proportional to the phase difference ø as shown in figure 2. However, due to internal delays and other
factors, the actual IC is unable to compare small phase differences, and thus a dead zone (B) appears in the output. To
achieve a high signal-to-noise ratio in the end product, the dead zone should be as small as possible.

However, in popularly-priced models, there are cases where a somewhat wider dead zone may be easier to work with.
This is because in some situations, such as when a powerful signal is applied to the RF input, in popularly-priced models
there may be RF leakage from the mixer to the VCC. When the dead zone is narrow, outputs to correct this leakage are
output, that output in turn modulates the VCO, and generates a beat signal with the RF.

(2) Notes on the FMIN and HCTR pins
The coupling capacitor must be located as close as possible to these pins. A capacitance of approximately 100 pF is
desirable.
In particular, if the HCTR pin capacitor is over about 1000 pF, the time required to reach the bias level may become
excessive, and incorrect counting may occur due to the relationship with the wait time.

(3) Notes on the IF counting → SD must be used in conjunction with IF counting.
If the general-purpose counter is used to count the IF frequency, the application microcontroller must test the state of the
IF IC SD (station detect) signal, and only if the SD signal is present, turn on the IF counter buffer output and perform an
IF count operation. Methods in which auto-search operations are implemented only using the IF count may incorrectly
stop at frequencies where no station is present due to leakage from the IF counter buffer.

(4) Using the DO pin
At times other than data output mode, the DO pin can also be used to check for general-purpose counter count operation
completion, to output the unlock state detection signal, and to check for changes in the input pins.
Note that the states of the input pins (I/O-1 and I/O-2) can be directly input to the system microcontroller through the DO
pin.

(5) Power supply pins
Capacitors of over 2000 pF must be inserted between the VDD and VSS power supply pins and between Vreg and VSS
to reduce noise. These capacitors must be located as close to the VDD, Vreg, and VSS pins as possible.

No. 6675-20/22

LC72147V

Reference divider

Programmable divider

VCO

LPF

Phase
detector

MIX

RF

Leakage

fr

fp

ø (nsec)

(B)

(A)

Dead zone

Figure 1

Figure 2

(6) Notes on VCO design
The VCO must be designed so that the VCO oscillation does not stop if the control voltage (Vtune) becomes 0 V. If it is
possible for this oscillator to stop, use the charge pump control data (DLC) to forcible set Vtune to VCC temporarily to
prevent the PLL circuit from deadlocking. (This function is called a deadlock clear circuit.)

Pin states during a power-on reset

No. 6675-21/22

LC72147V

AV

SS

I/O-4

XOUT

CE
DI
CL
DO

LC72147V

ADC0

ADC1

FMIN

HCTR

I/O-5

I/O-1

I/O-2

AOUT

IFBC

AIN

PD

V

SS

V

DD

XBUF

Vreg

XIN

I/O-3O-3

I-2
I-1

I-4

I-5

F

F

F

MF

L

State Power-on reset StatePower-on reset

F

F : Floating
L : Low

M : Medium

PS No. 6675-22/22

LC72147V

This catalog provides information as of October, 2000. Specifications and information herein are subject
to change without notice.

Specifications of any and all SANYO products described or contained herein stipulate the performance,
characteristics, and functions of the described products in the independent state, and are not guarantees
of the performance, characteristics, and functions of the described products as mounted in the customer’s
products or equipment. To verify symptoms and states that cannot be evaluated in an independent device,
the customer should always evaluate and test devices mounted in the customer’s products or equipment.

SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all
semiconductor products fail with some probability. It is possible that these probabilistic failures could
give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire,
or that could cause damage to other property. When designing equipment, adopt safety measures so
that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective
circuits and error prevention circuits for safe design, redundant design, and structural design.

In the event that any or all SANYO products (including technical data, services) described or contained
herein are controlled under any of applicable local export control laws and regulations, such products must
not be exported without obtaining the export license from the authorities concerned in accordance with the
above law.

No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system,
or otherwise, without the prior written permission of SANYO Electric Co., Ltd.

Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification”
for the SANYO product that you intend to use.

Information (including circuit diagrams and circuit parameters) herein is for example only; it is not
guaranteed for volume production. SANYO believes information herein is accurate and reliable, but
no guarantees are made or implied regarding its use or any infringements of intellectual property rights
or other rights of third parties.

Sample Application Circuit

24
23
22
21
20
19
18
17

13

1
2
3
4
5
6
7
8

9
10
11
12

16
15
14

2nd MixerVCC (6 V)

XIN

I/O-3

XBUF

V

DD

V

SS

Vreg

LC72147V

AOUT

3 V

GND

AV

SS

GND

PD

AIN

I/O-4

10.25 MHz

XOUT

CE

Microcontroller

DI

FMIN

IF-Buffer

VCO (LO)

Vtune

Signal level

CL
DO
ADC1
ADC0

I/O-2
I/O-1

I/O-5

HCTR
IFBC

1st IF: 10.7 MHz
Second mixer input: 10.25 MHz
2nd IF: 450 kHz