Datasheet LC65E1104 Datasheet (SANYO)

Overview

The LC65E1104 is an on-chip UVEPROM version of
Sanyo’s LC651104N/F/L and LC651102N/F/L CMOS
4-bit single-chip microcontrollers. The LC65E1104 has
the same functions and pin assignment as the
LC651104N/F/L and LC651102N/F/L mask ROM
products, although the A/D characteristics and certain
other characteristics differ somewhat. It includes a 4-KB
on-chip EPROM.
The LC65E1104 is provided in DIC30S and MFC30S
window packages and is ideal for program development
and evaluation since program data can be rewritten
multiple times.

Features

• EPROM data option switching
The following four LC65E1104 functions can be
specified by EPROM data:
— Port C and D output levels at reset
— Clock oscillator option
— Clock predivider option
— Watchdog reset option
However, note that the port output circuit type cannot be
changed. These circuits are always open-drain outputs.

• Internal UVEPROM capacity: 4096 bytes

• The LC65E1104 on-chip UVEPROM can be
programmed and verified using a general-purpose
EPROM programmer.
Sanyo provides special-purpose 30-to-28-pin adapters
(the W65EP1104D for the DIC package and the
W65EP1104M for the MFC package) to allow
commercial EPROM programmers to be used with the
LC65E1104.

• Data security function

• Pin compatible with the LC651104/1102 mask ROM
devices

• Instruction cycle time: 0.92 µs to 20 µs (A/D converter
cycle time: 0.98 µs to 12 µs)

• Factory shipment: DIC-30S (with window), MFC-30S
(with window)

Package Dimensions

unit: mm

3212-MFC30S

unit: mm

3215-DIC30S

Note: These figures are provided for reference purposes and do not include

tolerance specifications. Official drawings are available on request
from your Sanyo representative.

CMOS LSI

73096HA (OT) No. 5221-1/19

Preliminaly

SANYO: MFC30S

[LC65E1104]

SANYO: DIC30S

[LC65E1104]

SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN

On-Chip UVEPROM

4-Bit Single-Chip Microcontroller

LC65E1104

Ordering number : EN*5221

No. 5221-2/19

LC65E1104

LC651104/1102 series organization

Pin Assignment

Common to DIC/MFC

Usage Notes

The LC65E1104 was designed for developing and evaluating programs for the LC651104/1102 series microcontrollers.
Keep the following points in mind when using the LC65E1104.

1. Protecting EPROM data from UV exposure

Keep the LC65E1104’s package window covered with an opaque seal when using the device.

2. The LC65E1104 differs from the LC651104N/F/L and LC651102N/F/L as listed in the table below.

Model name Pins ROM capacity RAM capacity Package
LC651104N/F/L, LC651102N/F/L 30 4 k/2 k 256 W DIP30S, DIP30S-D, MFP30S
LC65E1104 30 4 k 256 W DIC30S, MFC30S
LC65P1104 30 4 k 256 W DIP30S-D, MFP30S

Note: A/D converter operating supply voltage range: 4.7 to 5.3 V

Item LC65E1104 LC651104F/1102F LC651104N/1102N LC651104L/1102L
I/O circuit configuration Open drain (N channel) Open drain or pull-up resistor-provided output selectable bit by bit (user mask option)
Port C and D output High or low selected in 4-bit High or low selected in 4-bit units

levels at reset units (by EPROM data) (user mask option)

Resonator

RC/ceramic RC/ceramic

Oscillator

(by EPROM data) (user mask option)

Predivider option

1/1, 1/3, 1/4 1/1 only 1/1, 1/3, 1/4

(by EPROM data) (user mask option) (user mask option)

Watchdog reset Available/not available Available/not available

(by EPROM data) (user mask option)

Operating supply

3.0 to 6.0 V* 4.0 t 6.0 V 3.0 to 6.0 V 2.5 to 6.0 V

voltage range (V

DD

)
Normal mode current drain Mask version + about 3 mA (typical) 2 mA (typical) 1.5 mA (typical) 1.5 mA (typical)
Low-level input current

–50 µA (typical) –10 µA (typical)

(RES terminal)
Operating temperature range +10 to +40°C –40 to +85°C
Package DIC30S (with window) DIP30S, DIP30S-D

MFC30S (with window) MFP30S

Pin Names

System Block Diagram

No. 5221-3/19

LC65E1104

OSC1, OSC2 RC or ceramic oscillator
RES Reset
PA0 to PA3 Shared-function I/O ports A0 to A3
PC0 to PC3 Shared-function I/O ports C0 to C3
PD0 to PD3 Shared-function I/O ports D0 to D3
PE0 to PE1 Shared-function I/O ports E0 to E1
PF0 to PF3 Shared-function I/O ports F0 to F3
PG0 to PG3 Shared-function I/O ports G0 to G3

TEST Test
INT Interrupt request pin
SI Serial input pin
SO Serial output pin
SCK Serial clock input/output pin
AD0 to AD7 AD converter input pin
AV+, AV– AD converter reference voltage input
WDR Watchdog reset pin

Note: The SI, SO, SCK, and INT pins are shared function pins that are also used as the PF0 to PF3 pins, respectively.

RAM Data memory
F Flag
WR Working register
AC Accumulator
ALU Arithmetic and logic unit
DP Data pointer
E E register
CTL Control register
OSC Oscillator
TM Timer

ROM Program memory
PC Program counter
INT Interrupt control
IR Instruction register
I.DEC Instruction decoder
CF, ZSF Carry flag, Carry save flag
ZF, ZSC Zero flag, zero save flag
EXTF External interrupt request flag
TMF Internal interrupt request flag
STS Status register

No. 5221-4/19

LC65E1104

Pin Description

Symbol Pins I/O Function Option At reset PROM mode

• Address inputs A9
to A11

• EPROM control
signal TA

Identical to PE0 to
PE1
Serial port: Disabled
Interrupt source: INT

Identical to PE0 to
PE1

• I/O ports F0 tp F3
Identical to PE0 to PE1*

• Shared with the serial interface and INT
input.
Program-selectable
SI Serial input port
SO Serial output port
SCK Serial clock input/output
INT Interrupt request input
The serial I/O function can be switched
between 4-bit and 8-bit operation under
program control.
Note: * No burst pulse output function is

provided.

I/O4

PF0/SI/A9
PF1/SO/A10
PF2/SCK/A11
PF3/INT/TA

• EPROM control
signal CE

• Address input A0

High-level output
(Output Nch
transistor: Off)

1. Open drain type
output

• I/O port: E0 and E1
Input in 4-bit units (IP instruction)
Output in 4-bit units (OP instruction)
Setting or clearing in single-bit units (SPB,
RPB instructions)
Testing in single-bit units (BP and BNP
instructions)

• PE0 provides a continuous burst (64·Tcyc)
function.

I/O2

PE0/CE
PE1/WDR/A0

Data lines D4 to D7

Identical to PC0 to
PC3

Identical to PC0 to
PC3

I/O port: D0 to D3
Identical to PC0 to PC3

I/O4

PD0/D4
PD1/D5
PD2/D6
PD3/D7

Data lines D0 to D3

• High-level output

• Low-level output
(Option-selectable)

1. Open drain type
output

2. Output at reset:
high

3. Output at reset:
low

2., 3.: Specified in a

group of 4 bits

• I/O port: C0 to C3
Identical to PA0 to PA3*

• Option permits output at reset to be high or
low.
Note: * No standby control function is

provided.

I/O4

PC0/D0
PC1/D1
PC2/D2
PC3/D3

Address inputs A1 to
A4

High-level output
(Output Nch
transistor: Off)

Open drain type
output

• I/O port: A0 to A3
Input in 4-bit units (IP instruction)
Output in 4-bit units (OP instruction)
Testing in single-bit units (BP and BNP
instructions)
Setting or clearing in single-bit units (SPB
and RPB instructions)

• Standby is controlled by PA3

• The PA3 pin must be free from chattering
during the halt instruction execution cycle.
Each of these four pins has two functions as
listed below.
PA0/AD0: AD converter input pin AD0
PA1/AD1: AD converter input pin AD1
PA2/AD2: AD converter input pin AD2
PA3/AD3: AD converter input pin AD3

I/O4

PA0/AD0/A1
PA1/AD1/A2
PA2/AD2/A3
PA3/AD3/A4

EPROM control signal
DASEC

—

1. Pin 2: RC oscillator
external clock

2. Pin 2: Ceramic
oscillator

3. Predivider option

• No predivider

• 1/3 predivider

• 1/4 predivider

• Connections for the external RC or ceramic
oscillator circuit used as the system clock
oscillator.

• If external clock input is used, leave the
OSC2 pin open.

I

O

1

1

OSC1/DASEC

OSC2

———Power supply

—
—

1
1

V

DD

V

SS

Continued on next page.

No. 5221-5/19

LC65E1104

Continued from preceding page.

Symbol Pins I/O Function Option At reset PROM mode

EPROM control signal
EPMOD

——

LSI test pin
Normally connected to V

SS

1TEST/EPMOD

EPROM control signal
VPP/OE

——

• System reset input

• Connect an external capacitor for power on
reset.

• Apply a low level for at least 4 clock cycles
for the power-on reset.

1RES/VPP/OE

———

Reference voltage input pin for A/D
conversion.

—
—

1
1

AV+
AV–

Address inputs A5 to
A8

Identical to PE0 to
PE1

Identical to PE0 to
PE1

• I/O ports G0 to G3
Identical to PE0 to PE1*
Note: * No burst pulse output function is

provided.

• Each of these four pins has two functions as
listed below.
PG0/AD4: AD converter input pin AD4
PG1/AD5: AD converter input pin AD5
PG2/AD6: AD converter input pin AD6
PG3/AD7: AD converter input pin AD7

I/O4

PG0/AD4/A5
PG1/AD5/A6
PG2/AD6/A7
PG3/AD7/A8

Oscillator circuit option

Option Circuit Conditions and notes

1. External clock

2. 2-pin RC OSC

3. Ceramic oscillator

Leave the OSC2 pin open.

Predivider option

Option Circuit Conditions and notes

1. No predivider (1/1)

2. 1/3 predivider

3. 1/4 predivider

• Applicable to all 3 oscillator options.

• The oscillator or external clock frequency must
not exceed 1444 kHz. (LC651104N,
LC651102N)

• The oscillator or external clock frequency must
not exceed 4330 kHz. (LC651104F,
LC651102F)

• The oscillator or external clock frequency must
not exceed 1040 kHz. (LC651104L,
LC651102L)

• Applicable to the external clock and ceramic
oscillator options.

• The oscillator or external clock frequency must
not exceed 4330 kHz.

• Applicable to the external clock and ceramic
oscillator options.

• The oscillator or external clock frequency must
not exceed 4330 kHz.

Note: The oscillator and predivider options are summarized in the LC651104/1102 semiconductor news.

Port C and D reset output level options

Either of the following two options may be selected for the C and D I/O ports. Note that these options are specified in 4­bit units.

Port output configuration option

All shared-function I/O ports have an open-drain output circuit in the LC65E1104.

Watchdog reset option

This option specifies the use of the PE1/WDR pin. This pin can be specified to function either as the normal port PE1 or
as the WDR watchdog reset pin.

Usage Notes

1. Option specification
The SU60K.EXE program is used for option specification. The option code for the option specification area
(addresses 1000 to 100A (hexadecimal)) is created by assembling the output of the SU60K.EXE program using the
Sanyo M60K.EXE macro assembler and then linking the macro assembler output with the Sanyo L60K.EXE linker.
It is also possible to load data directly into the option specification area. Specify options according to the option code
creation table on page 8.

2. PROM programming
LC65E1104 can be programmed with a general-purpose EPROM programmer using either the W65EP1104D or
W65EP1104M adapter.

• Recommended EPROM programmers

• The Intel 27512 (VPP: 12.5 V) high-speed programming method must be used to program this device. The address

range must be set to 0 to 100A (hexadecimal) and the DASEC jumper must be set to the off position.

3. Using the data security function
The data security function prevents data already written to the microcontroller's PROM from being overwritten.
LC651104 data security function procedure

• Move the DASEC jumper on the EPROM programming pin adapter to the on position. This enables the data

security function.

• Attempt to reprogram the EPROM.

Since the data security function is enabled, the EPROM programmer will display an error. Note that this error is not
due to an error in either the programmer or the LSI.

No. 5221-6/19

LC65E1104

Option name Conditions

1. Output at reset: high All 4 bits of the selected port(s) (C or D or both)

1. Output at reset: low All 4 bits of the selected port(s) (C or D or both)

Option Circuit Conditions and notes

1. Open drain output Ports A, C, D, E and F

Manufacturer EPROM programmer
Advantest R4945, R4944, R4943 or equivalent programmer
Ando AF-9704
AVAL —
Minato electronics —

Note: 1. At step 2, the data security function will not operate if all the data at the addresses to be programmed have

the value FF (hexadecimal).

Note: 2. At step 2, the data security function will not apply to (i.e., will not prevent) programming using the

sequence BLANK Æ PROGRAM Æ VERIFY.

Note: 3. Return the jumper to the off position after executing the data security function.

DASEC jumper setting

No. 5221-7/19

LC65E1104

Option specification area

No. 5221-8/19

LC65E1104

ROM area Bit Option specified Option/data relationship

7 Unused 0 (fixed)
6 Watchdog reset 0: Disabled, 1: Enabled
5 PD

Output level at reset 0: Low level, 1: High level

1000H

4 PC
3

OSC predivider (XX = bits 3, bit 2) 00: 1/1, 01: 1/3, 10: 1/4,. 11: unused

2
1

OSC resonator (XX = bits 1, bit 0) 00: unused, 01: unused, 10: (2RC, EXT), 11: Ceramic

0
7 PC3
6 PC2

Output configuration 0: OD, 1: PU*

5 PC1

1001H

4 PC0
3 PA3
2 PA2

Output configuration 0: OD, 1: PU*

1 PA1
0 PA0
7

Unused 0 (fixed)

6
5 PE1

Output configuration 0: OD, 1: PU*

1002H

4 PE0
3 PD3
2 PD2

Output configuration 0: OD, 1: PU*

1 PD1
0 PD0
7 PG3
6 PG2

Output configuration 0: OD, 1: PU*

5 PG1

1003H

4 PG0
3 PF3
2 PF2

Output configuration 0: OD, 1: PU*

1 PF1
0 PF0
7
6

1004H

5

to

4

Unused 0 (fixed)

100AH

3
2
1
0

Note: Since all LC65E1104 ports are open-drain output circuits, the pull-up resistor options are ignored. However, the port options must be selected when

using the LC651104/1102 mask ROM products.
PU: Built-in pull-up resistor output circuit, OD: Open-drain output circuit

No. 5221-9/19

LC65E1104

Parameter Symbol Conditions Ratings Unit

Maximum supply voltage V

DD

max V

DD

–0.3 to +7.0 V

Output voltage V

O

OSC2

Allowable up to the

V

generated voltage

Input voltage

V

I

1 OSC1

*1

–0.3 to VDD+ 0.3 V

V

I

2 TEST, RES, AV+, AV– –0.3 to VDD+ 0.3 V

Input/output voltage

V

IO

1 PC0 to PC3, PD0 to PD3, PE0, PE1, PF0 to PF3 –0.3 to +15 V

V

IO

2 PA0 to PA3, PG0 to PG3 –0.3 to VDD+ 0.3 V

Peak output current I

OP

I/O port –2 to +20 mA

I

OA

I/O port: Per pin over a 100 ms period –2 to +20 mA

ΣIOA1

PC0 to PC3, PD0 to PD3, PE0, PE1:Total current for

–15 to +100 mA

Average output current PC0 to PC3, PD0 to PD3, and PE0, PE1

*2

ΣIOA2

PF0 to PF3, PG0 to PG3, PA0 to PA3: Total current for

–15 to +100 mA

PF0 to PF3, PG0 to PG3, and PA0 to PA3

*2

Allowable power dissipation

Pd max1 Ta = +10 to +40°C (DIC package) 250 mW

Pd max2 Ta = +10 to +40°C (MFC package) 150 mW
Operating temperature Topr +10 to +40 °C
Storage temperature Tstg –55 to +125 °C

Specifications

For LC651104N, 651102N
Absolute Maximum Ratings at Ta = 25°C, VSS= 0 V

Parameter Symbol Conditions

Ratings

Unit

min typ max

Operating supply voltage V

DD

V

DD

3.0 6.0 V

Standby supply voltage V

ST

VDD: RAM, register hold

*3

1.8 6.0 V

V

IH

1 Port C, D, E, F: Output Nch Tr. off 0.7 V

DD

+13.5 V

V

IH

2 Port A, G: Output Nch Tr. off 0.7 V

DD

V

DD

V

High level input voltage V

IH

3 INT, SCK, SI: Output Nch Tr. off 0.8 V

DD

+13.5 V

V

IH

4 RES: VDD= 1.8 to 6 V 0.8 V

DD

V

DD

V

V

IH

5 OSC1: External clock mode 0.8 V

DD

V

DD

V

V

IL

1 Port: Output Nch Tr. off, VDD= 4 to 6 V V

SS

0.3 V

DD

V

V

IL

2 Port: Output Nch Tr. off, VDD= 3 to 6 V V

SS

0.25 V

DD

V

V

IL

3 INT, SCK, SI: Output Nch Tr. off, VDD= 4 to 6 V V

SS

0.25 V

DD

V

V

IL

4 INT, SCK, SI: Output Nch Tr. off, VDD= 3 to 6 V V

SS

0.2 V

DD

V

Low level input voltage

V

IL

5 OSC1: External clock mode, VDD= 4 to 6 V V

SS

0.25 V

DD

V

V

IL

6 OSC1: External clock mode, VDD= 3 to 6 V V

SS

0.2 V

DD

V

V

IL

7 TEST: VDD= 4 to 6 V V

SS

0.3 V

DD

V

V

IL

8 TEST: VDD= 3 to 6 V V

SS

0.25 V

DD

V

V

IL

9 RES: VDD= 4 to 6 V V

SS

0.25 V

DD

V

V

IL

10 RES: VDD= 3 to 6 V V

SS

0.2 V

DD

V

Operating frequency fop When the 1/3 or 1/4 predivider option is selected, 200 1444 kHz
(cycle time) (Tcyc) clock must not exceed 4.33 MHz. VDD= 3 to 6 V (20) (2.77) (µs)

[External clock conditions]
Frequency text

OSC1: Fig 1, when clock exceeds 1.444 MHz,

200 4330 kHz
Pulse width textH, textL the 1/3 or 1/4 predivider option must be selected. 69 ns
Rise/fall time textR, textF

V

DD

= 3 to 6 V

50 ns

[Oscillator guaranteed constants]

Cext OSC1, OSC2: Fig 2, V

DD

= 3 to 6 V 270 ± 5% pF

2-pin RC oscillator

Cext OSC1, OSC2: Fig 2, V

DD

= 4 to 6 V 270 ± 5% pF

Rext OSC1, OSC2: Fig 2, V

DD

= 3 to 6 V 12 ± 1% kΩ

Rext OSC1, OSC2: Fig 2, V

DD

= 4 to 6 V 4.7 ± 1% kΩ

Ceramic Fig 3 Table 1

Allowable Operating Conditions at Ta = +10 to +40°C, VSS= 0 V, VDD= 3.0 to 6.0 V

No. 5221-10/19

LC65E1104

Parameter Symbol Conditions

Ratings

Unit

min typ max

I

IH

1

Port C, D, E, F: Output Nch Tr. off (including off leak

+5.0 µA

current of Nch Tr.), V

IN

= +13.5

High-level input current

I

IH

2

Port A, G: Output Nch Tr. off (including off leak

+5.0 µA

current of Nch Tr.), V

IN

= V

DD

IIH3 OSC1: External clock mode, VIN= V

DD

+1.0 µA

I

IL

1 Port: Output Nch Tr. off, VIN= V

SS

–1.0 µA

Low-level input current I

IL

2 RES: VIN= V

SS

–150 –50 µA

I

IL

3 OSC1: External clock mode, VIN= V

SS

–1.0 µA

V

OL

1 Port: IOL= 10 mA, VDD= 4.0 to 6.0 V 1.5 V

Low-level output current

V

OL

2

Port: I

OL

= 1 mA, IOLof each port; 1 mA or less

0.5 V

V

DD

= 3.0 to 6.0 V
[Schmitt characteristics]
Hysteresis voltage VHIS 0.1 V

DD

V

High-level threshold voltage VtH RES, INT, SCK, SI, OSC1 of Schmitt type

*4

0.4 V

DD

0.8 V

DD

V

Low-level threshold voltage VtL 0.2 V

DD

0.6 V

DD

V

[Current dissipation]
2-pin RC oscillator IDDOP1

V

DD

: Output Nch Tr. off at operating, port = VDD,

4.5 6 mA

Fig. 2, fosc = 900 kHz (typ)

IDDOP2 V

DD

: Fig 3, 4 MHz, 1/3 predivider 4.5 7 mA

Ceramic oscillator

IDDOP3 V

DD

: Fig 3, 4 MHz, 1/4 predivider 4.5 6 mA

IDDOP4 V

DD

: Fig 3, 400 kHz 4.0 4.5 mA

IDDOP5 V

DD

: Fig 3, 800 kHz 4.5 6 mA

V

DD

: 200 kHz to 1444 kHz, 1/1 predivider;

External clock IDDOP6 600 kHz to 4330 kHz, 1/3 predivider; 4.5 7 mA

800 kHz to 4330 kHz, 1/4 predivider

Standby mode IDDst

V

DD

: Output Nch Tr. off, VDD= 6 V 0.05 10 µA

V

DD

: Port = VDD, VDD= 3 V 0.025 5 µA

[Oscillator characteristics]

OSC1, OSC2: Fig 3, fo = 400 kHz 384 400 416 kHz
OSC1, OSC2: Fig 3, fo = 800 kHz 768 800 832 kHz

Ceramic OSC frequency fCFOSC

*5

OSC1, OSC2: Fig 3, fo = 1 MHz 960 1000 1040 kHz
OSC1, OSC2: Fig 3, fo = 4 MHz, 1/3 predivider,

3840 4000 4160 kHz

1/4 predivider
Fig 4, fo = 400 kHz 10 ms

Stabilization tCFS Fig 4, fo = 800 kHz, 1 MHz, 4 MHz, 1/3 predivider,

10 ms

1/4 predivider
OSC1, OSC2: Fig. 2, Cext = 270 pF ± 5%,

666 900 1334 kHz

2-pin RC oscillator

fMOSC

Fig. 2, Rext = 4.7 kΩ ± 1%, V

DD

= 4 to 6 V

frequency

OSC1, OSC2: Fig. 2, Cext = 270 pF ± 5%,

283 400 717 kHz

Fig. 2, Rext = 12 kΩ ± 1%, V

DD

= 3 to 6 V
[Pull-up resistance]
I/O port RES: RU RES: V

IN

= VSS, VDD= 5 V 50 100 250 kΩ
[External reset characteristics]
Reset time tRST See Fig. 5

Pin capacitance C

P

f = 1 MHz. VIN= VSSfor all pins other than those

10 pF

being tested.
[Serial clock]
Input clock cycle time tCKCY1 SCK: Fig. 6 3.0 µs
Output clock cycle time tCKCY2 SCK: Fig. 6

64 × tCYC

*6

µs
Input clock low-level pulse width tCKL1 SCK: Fig. 6 1.0 µs
Output clock low-level pulse width tCKL2 SCK: Fig. 6 32 × tCYC µs
Input clock high-level pulse width tCKH1 SCK: Fig. 6 1.0 µs
Output clock high-level pulse width tCKH2 SCK: Fig. 6 32 × tCYC µs
[Serial input]
Data setup time tICK SI: Specified from the rising edge of SCK. Fig. 6 0.4 µs
Data hold time tCKI 0.4 µs

Electrical Characteristics at Ta = +10 to +40°C, VSS= 0 V, VDD= 3.0 to 6.0 V

Continued on next page.

No. 5221-11/19

LC65E1104

Continued from preceding page.

Parameter Symbol Conditions

Ratings

Unit

min typ max

[Serial output]
Output delay time tCKO

SO: Specified from the falling edge of SCK.

0.6 µs

Nch OD only, external 1kΩ, external 50 pF, Fig. 6
[Pulse output]
Period tPCY 64 ×tCYC µs

High-level pulse width tPH

32 × tCYC

µs

± 10%

Low-level pulse width tPL

32 × tCYC

µs

± 10%
[AD conversion characteristics]
Resolution V

DD

= 4.7 to 5.3 V 8 bits

Absolute accuracy AV+ = V

DD

, AV– = VSS, VDD= 4.7 to 5.3 V ±1 ±2 LSB

AD speed 1/1, at 26 × tCYC, V

DD

= 4.7 to 5.3 V

72 (tCYC 312 (tCYC

Conversion time TCAD

= 2.77 µs) = 12 µs)

µs

AD speed 1/2, at 51 × tCYC, VDD= 4.7 to 5.3 V

141 (tCYC 612 (tCYC

= 2.77 µs) = 12 µs)

Reference input voltage

AV+ AV+: V

DD

= 4.7 to 5.3 V AV– V

DD

V

AV– AV–: V

DD

= 4.7 to 5.3 V V

SS

AV+

Reference input current range IRIF AV+, AV–: AV+ = V

DD

, VDD= 4.7 to 5.3 V, AV– = V

SS

75 150 300 µA

Analog input voltage range VAIN AD0 to AD7: V

DD

= 4.7 to 5.3 V AV– AV+ V

Port pins AD0 to AD7

1

Including output OFF leakage current. VAIN = V

DD

,

Analog port input current IAIN

V

DD

= 4.7 to 5.3 V

µA

Port pins AD0 to AD7
VAIN = V

SS

, VDD= 4.7 to 5.3 V

–1

[Watchdog timer]

Cw WDR: VDD= 3 to 6 V 0.1 ± 5% µF

Guaranteed constant

*7

Rw WDR: VDD= 3 to 6 V 680 ± 1% kΩ

RI WDR: V

DD

= 3 to 6 V 100 ± 1% Ω

Clear time (discharge) tWCT WDR: Fig. 8, V

DD

= 3 to 6 V 100 µs

Clear time (charge) tWCCY WDR: Fig. 8, V

DD

= 3 to 6 V 36 ms

Cw WDR: V

DD

= 4 to 6 V 0.047 ± 5% µF

Guaranteed constant

*7

Rw WDR: VDD= 4 to 6 V 680 ± 1% kΩ

RI WDR: V

DD

= 4 to 6 V 100 ± 1% Ω

Clear time (discharge) tWCT WDR: Fig. 8, V

DD

= 4 to 6 V 40 µs

Clear time (charge) tWCCY WDR: Fig. 8, V

DD

= 4 to 6 V 18 ms

PE0: Fig. 7, tCYC = 4 × system clock period,
Nch OD only, external 1 kΩ, external 50 pF

Note: 1. The LC65E1104 will accept input voltages up to the generated oscillator amplitude if the oscillator circuit in figure 4 with circuit constants in the

guaranteed constants ranges is driven from within the IC.

2. Average over a 100 ms period

3. The operating supply voltage V

DD

must be held until standby mode is enterd after the execution of a HALT instruction. The PA3 pin must be free

from chattering during the HALT instruction cycle.

4. The OSC1 pin input circuit has Schmitt trigger characteristics when the 2-terminal RC oscillator option or the external clock oscillator option is
selected.

5. fCFOSC: oscillator frequency. The center frequency of a ceramic oscillator has a tolerance range of about 1% around the nominal value specified
by the manufacturer of the oscillator element. For details, refer to the specifications of the ceramic resonator.

6. TCYC = 4 × system clock period

7. If the LC65E1104 is used in an environment subject to condensation, leakage between PE1 and adjacent pins and leakage associated with
external RCA circuits require special attention.

Fig. 1 External Clock Input Waveform

Fig. 2 2-pin RC Oscillator Circuit Fig. 3 Ceramic Oscillator

No. 5221-12/19

LC65E1104

Fig. 4 Oscillator Stabilization Period

Table 1 Constants Guaranteed for Ceramic Resonator Oscillator

No. 5221-13/19

LC65E1104

4 MHz (Murata)

C1 33 pF ± 10%

CSA4.00MG C2 33 pF ± 10%
CST4.00MGW (built-in C)

R 0 Ω
4 MHz (Kyocera) C1 33 pF ± 10%
KBR4.0 MSA C2 33 pF ± 10%
KBR4.0MKS (built-in C) R 0 Ω

1 MHz (Murata)

C1 100 pF ± 10%

CSB1000J

C2 100 pF ± 10%

R 2.2 kΩ

1 MHz (Kyocera)

C1 100 pF ± 10%

KBR1000F

C2 100 pF ± 10%

R 0 kΩ

800 kHz (Murata)

C1 100 pF ± 10%

CSB800J

C2 100 pF ± 10%

R 2.2 kΩ

800 kHz (Kyocera)

C1 220 pF ± 10%

KBR800F

C2 220 pF ± 10%

R 0 kΩ

400 kHz (Murata)

C1 220 pF ± 10%

CSB400P

C2 220 pF ± 10%

R 2.2 kΩ

400 kHz (Kyocera)

C1 330 pF ± 10%

KBR400BK

C2 330 pF ± 10%

R 0 kΩ

Fig. 5 Reset Circuit

Note: When the rise time of the power supply is close

to 0, the reset time will be between 10 and 100
ms for a CRES of 0.5 µF. If the rise time of the
power supply is significantly longer, the value
of CRES must be increased so that the reset
time will be 10 ms or longer.

Note: The constants above are preliminarlly. Final ratings will be fixed after evaluation.

Fig. 6 Serial Input /Output Timing

Fig. 7 Pulse Output Timing at Port PE0

Note: 1. tWCCT: The charge time due to the time constant of the external Cw, Rw, and R1 components

2. tWCT: The discharge time due to program operation

Fig. 8 Watchdog Timer Waveform

No. 5221-14/19

LC65E1104

No. 5221-15/19

LC65E1104

For LC651104F, 651102F
Absolute Maximum Ratings at Ta = 25°C, VSS= 0 V

Parameter Symbol Conditions Ratings Unit

Maximum supply voltage V

DD

max V

DD

–0.3 to +7.0 V

Output voltage V

O

OSC2

Allowable up to the

V

generated voltage

Input voltage

V

I

1 OSC1

*1

–0.3 to VDD+ 0.3 V

V

I

2 TEST, RES, AV+, AV– –0.3 to VDD+ 0.3 V

Input/output voltage

V

IO

1 PC0 to PC3, PD0 to PD3, PE0, PE1, PF0 to PF3 –0.3 to +15 V

V

IO

2 PA0 to PA3, PG0 to PG3 –0.3 to VDD+ 0.3 V

Peak output current I

OP

I/O port –2 to +20 mA

I

OA

I/O port: Per pin over a 100 ms period –2 to +20 mA

ΣI

OA

1

PC0 to PC3, PD0 to PD3, PE0, PE1:Total current for

–15 to +100 mA

Average output current PC0 to PC3, PD0 to PD3, and PE0, PE1

*2

ΣIOA2

PF0 to PF3, PG0 to PG3, PA0 to PA3: Total current for

–15 to +100 mA

PF0 to PF3, PG0 to PG3, and PA0, PA3

*2

Allowable power dissipation

Pd max1 Ta = +10 to +40°C (DIC package) 250 mW

Pd max2 Ta = +10 to +40°C (MFC package) 150 mW
Operating temperature Topr +10 to +40 °C
Storage temperature Tstg –55 to +125 °C

Parameter Symbol Conditions

Ratings

Unit

min typ max

Operating supply voltage V

DD

V

DD

4.0 6.0 V

Standby supply voltage VST V

DD

: RAM, register hold

*3

1.8 6.0 V

V

IH

1 Port C, D, E, F: Output Nch Tr. OFF 0.7 V

DD

+13.5 V

V

IH

2 Port A, G: Output Nch Tr. OFF 0.7 V

DD

V

DD

V

High-level input voltage V

IH

3 INT, SCK, SI: Output Nch Tr. OFF 0.8 V

DD

+13.5 V

V

IH

4 RES: VDD= 1.8 to 6.0 V 0.8 V

DD

V

DD

V

V

IH

5 OSC1: External clock mode 0.8 V

DD

V

DD

V

V

IL

1 Port: Output Nch Tr. OFF V

SS

0.3 V

DD

V

V

IL

2 INT, SCK, SI: Output Nch Tr. OFF V

SS

0.25 V

DD

V

Low-level input voltage V

IL

3 OSC1: External clock V

SS

0.25 V

DD

V

V

IL

4 TEST V

SS

0.3 V

DD

V

V

IL

5 RES V

SS

0.25 V

DD

V
Operating frequency (cycle time) fOP (Tcyc) 200 (20) 4330 (0.92) kHz (µs)
[External clock conditions]
Frequency text 200 4330 kHz
Pulse width textH, textL OSC1: Fig. 1 69 ns
Rise/fall time textR, textF OSC1: Fig. 1 50 ns
Oscillation guaranteed constants

Fig. 2 See Table 1

ceramic resonator oscillator

Allowable Operating Conditions at Ta = +10 to +40°C, VSS= 0 V, VDD= 4.0 to 6.0 V

No. 5221-16/19

LC65E1104

Parameter Symbol Conditions

Ratings

Unit

min typ max

I

IH

1

Port C, D, E, F: Output Nch Tr. OFF, (Including the Nch.

+5.0 µA

transistor off state leakage current.), V

IN

= +13.5

High-level input current

I

IH

2

Port A, G: Output Nch Tr. OFF, (Including the Nch.

+5.0 µA

transistor off state leakage current.), V

IN

= V

DD

IIH3 OSC1: External clock mode, VIN= V

DD

+1.0 µA

I

IL

1 Port of OD type: Output Nch Tr. OFF, VIN= V

SS

–1.0 µA

Low-level input current I

IL

2 RES: VIN= V

SS

–150 –50 µA

I

IL

3 OSC1: External clock mode, VIN= V

SS

–1.0 µA

Low-level output voltage

V

OL

1 Port: IOL= 10 mA 1.5 V

V

OL

2 Port: IOL= 1 mA, IOLof each port; 1 mA or less 0.5 V
[Schmitt characteristics]
Hysteresis voltage VHIS 0.1 V

DD

V

High-level threshold voltage VtH RES, INT, SCK, SI, OSC1 of Schmitt type

*4

0.4 V

DD

0.8 V

DD

V

Low-level threshold voltage VtL 0.25 V

DD

0.6 V

DD

V

[Current drain]
Ceramic resonator oscillator IDDOP1 5 8 mA

External clock IDDOP2 5 8 mA

Standby mode IDDst

V

DD

: Output Nch Tr. OFF, VDD= 6 V 0.05 10 µA

V

DD

: Port = VDD, VDD= 3 V 0.025 5 µA
[Oscillator characteristics]
Ceramic resonator oscillator fCFOSC OSC1, OSC2: Fig.2, fo = 4 MHz

*5

3840 4000 4160 kHz
Frequency stabilization time tCFS Fig. 3, fo = 4 MHz 10 ms
[Pull-up resistance]
I/O port RES RU RES: V

IN

= VSS, VDD= 5 V 50 100 250 kΩ
[External reset characteristics]
Reset time tRST See Fig. 4

Pin capacitance C

P

f = 1 MHz. VIN= VSSfor all pins other than those

10 pF

being tested.
[Serial clock]
Input clock cycle time tCKCY1 SCK: Fig. 5 2.0 µs
Output clock cycle time tCKCY2 SCK: Fig. 5

64 × tCYC

*6

µs
Input clock low-level pulse width tCKL1 SCK: Fig. 5 0.6 µs
Output clock low-level pulse width tCKL2 SCK: Fig. 5 32 × tCYC µs
Input clock high-level pulse width tCKH1 SCK: Fig. 5 0.6 µs
Output clock high-level pulse width tCKH2 SCK: Fig. 5 32 × tCYC µs
[Serial input]
Data setup time tICK

SI: Specified from the rising edge of SCK. Fig. 5

0.2 µs
Data hold time tCKI 0.2 µs
[Serial output]

Output delay time tCKO

SO: Specified from the falling edge of SCK. Nch OD

0.4 µs

only, external 1 kΩ, external 50 pF, Fig.5
[Pulse output]
Period tPCY 64 ×tCYC µs

High-level pulse width tPH

32 × tCYC

µs

± 10%

Low-level pulse width tPL

32 × tCYC

µs

± 10%

PE0: Fig. 6, tCYC = 4 × system clock period,
Nch OD only, external 1 kΩ, external 50 pF

V

DD

: Fig. 2, 4 MHz, 200 kHz to 4330 kHz*

Note: * Output Nch Tr. OFF at operating mode,

port = V

DD

Electrical Characteristics at Ta = +10 to +40°C, VSS= 0 V, VDD= 4.0 to 6.0 V

Continued on next page.

No. 5221-17/19

LC65E1104

Continued from preceding page.

Parameter Symbol Conditions

Ratings

Unit

min typ max
[AD conversion characteristics]
Resolution V

DD

= 4.7 to 5.3 V 8 bits

Absolute accuracy AV+ = V

DD

, AV– = VSS, VDD= 4.7 to 5.3 V ±1 ±2 LSB

AD speed 1/1, at 26 × tCYC, V

DD

= 4.7 to 5.3 V

25 (tCYC 312 (tCYC

µs

Conversion time tCAD

= 0.98 µs) = 12 µs)

AD speed 1/2, at 51 × tCYC, V

DD

= 4.7 to 5.3 V

50 (tCYC 612 (tCYC

µs

= 0.98 µs) = 12 µs)

Reference input voltage

AV+ AV+: V

DD

= 4.7 to 5.3 V AV– V

DD

V

AV– AV–: V

DD

= 4.7 to 5.3 V V

SS

AV+

Reference input current range IRIF AV+, AV–: AV+ = V

DD

, VDD= 4.7 to 5.3 V, AV– = V

SS

75 150 300 µA

Analog input voltage range VAIN AD0 to AD7: V

DD

= 4.7 to 5.3 V AV– AV+ V

Port pins AD0 to AD7

1

Including output OFF leakage current. VAIN = V

DD

,

Analog port input current IAIN

V

DD

= 4.7 to 5.3 V

µA

Port pins AD0 to AD7

–1

VAIN = V

SS

, VDD= 4.7 to 5.3 V

[Watchdog timer]

Cw WDR 0.01 ± 5% µF

Guaranteed constants Rw WDR 680 ± 1% kΩ

RI WDR 100 ± 1% Ω
Clear time (discharge) tWCT WDR: Fig. 7 10 µs
Clear time (charge) tWCCY WDR: Fig. 7 42 ms

Note: 1. The LC65E1104 will accept input voltages up to the generated oscillator amplitude if the oscillator circuit in figure 2 with circuit constants in the

guaranteed constants ranges is driven internally.

2. Average over a period of 100 ms.

3. The operating supply voltage V

DD

must be held until standby mode is entered after the execution of a HALT instruction. The PA3 pin must be free

from chattering during the HALT instruction execution cycle.

4. The OSC1 pin input circuit has Schmitt trigger characteristics when the external clock oscillator option is selected.

5. fCFOSC: Oscillator frequency

6. TCYC = 4 × system clock period

7. If the LC65E1104 is used in an environment subject to condensation, leakage between PE1 and adjacent pins and leakage associated with
external RCA circuits require special attention.

Fig. 1 External Clock Input Waveform

Fig. 2 Ceramic Oscillator Circuit Fig. 3 Oscillator Stabilization Period

Fig. 5 Serial Input /Output Timing

Table 1 Constants Guaranteed for Ceramic Resonator Oscillator

No. 5221-18/19

LC65E1104

Note: The constants above are preliminarlly. Final ratings will be fixed after evaluation.

4 MHz (Murata)

C1 33 pF ± 10%

CSA4.00MG C2 33 pF ± 10%
CST4.00MGW (built-in C)

R 0 Ω
4 MHz (Kyocera) C1 33 pF ± 10%
KBR4.0 MSA C2 33 pF ± 10%
KBR4.0MKS (built-in C) R 0 Ω

Fig. 4 Reset Circuit

Note: When the rise time of the power supply is close

to 0, the reset time will be between 10 and 100
ms for a CRES of 0.5 µF. If the rise time of the
power supply is significantly longer, the value
of CRES must be increased so that the reset
time will be 10 ms or longer.

No. 5221-19/19

LC65E1104

Fig. 6 Pulse Output Timing at Port PE0

Note: 1. tWCCY: The charge time due to the time constant of the external Cw, Rw, and R1 components

2. tWCT: The discharge time due to program operation

Fig. 7 Watchdog Timer Waveform

This catalog provides information as of December, 1997. Specifications and information herein are subject to
change without notice.

■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace
equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of
which may directly or indirectly cause injury, death or property loss.

■ Anyone purchasing any products described or contained herein for an above-mentioned use shall:
➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and

distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all
damages, cost and expenses associated with such use:

➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on

SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees
jointly or severally.

■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for
volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied
regarding its use or any infringements of intellectual property rights or other rights of third parties.