Datasheet LC651432N, LC651431N, LC651431F, LC651432F Datasheet (SANYO)

Ordering number : ENN6498

40700RM (OT) No. 6498-1/39

Overview

The LC651431N/F/L and LC651432N/F/L are the small­scale control models in Sanyo’s LC6500 Series of 4-bit
microcontrollers and feature the same basic architecture
and instruction set. These microcontrollers are appropriate
for a wide range of applications, from applications that
require only a limited number of circuits and controls and
were previously implemented in standard logic to larger
application such as audio equipment, including tape decks
and disc players, office equipment, communication
equipment, automotive equipment, and home appliances.
Furthermore, since these products have equivalent basic
functions (although there are differences in some functions
and characteristics) and are pin compatible with the earlier
LC6543N/F/L and LC6546N/F/L products, they can be
used to replace those devices.

Features

• Fabricated in a CMOS process for low power operation
(Standby mode can be controlled by CPU instructions.)

• ROM/RAM
LC651432N/F/L
—ROM: 2 K × 8 bits, RAM: 128 × 4 bits
LC651431N/F/L
—ROM: 1 K × 8 bits, RAM: 64 × 4 bits

• Instruction set: The 80-instruction set common to the
whole LC6500 Series

• Wide operating supply voltage range of 2.2 to 6.0 V
(L versions)

• Instruction cycle time of 0.92 µs (F versions)

• On-chip serial I/O function

• Highly flexible I/O ports
Number of ports
— 7 ports (Up to 25 pins)
All ports
— Can be used for either input or output
— Voltage handling capability (input and output):

15 V maximum (For open-drain specification ports)

— Output current: 20 mA maximum sink current

(Capable of directly driving an LED.)
I/O port options to match application requirements:
— Open-drain output and pull-up resistor specification:

Can be specified for all ports in bit units.
— Output level at reset specification: Either a high or

low level can be specified for ports C and D in 4-bit

units each.

• Interrupts
Timer overflow vector interrupt (can also be tested by
CPU instructions)
INT pin or serial I/O full/empty vector interrupt (can
also be tested by CPU instructions)

• Stack levels: 4 levels (also used by interrupts)

• Timers: 8-bit programmable timer with 4-bit prescaler

• Clock oscillator options to match application
requirements:
Oscillator circuit option:
— Two-pin RC oscillator (N and L versions)

Two-pin ceramic oscillator or single external clock
input pin (N, F, and L versions)

— Divider circuit option: No divider, built-in divide-

by-three circuit, built-in divide-by-four circuit
(N and L versions)

• Continuous square-wave output with a period 64 times
the cycle time.

LC651432N/F/L, 651431N/F/L

SANYO Electric Co.,Ltd. Semiconductor Company

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN

Four-Bit CMOS Microcontrollers for

Small-Scale Control Applications

CMOS IC

Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.

SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.

No. 6498-2/39

LC651432N/F/L, 651431N/F/L

(1.04)

1.78

0.95

0.48

10.16

3.95max

(3.25)

0.51min

3.0

0.25

115

30 16

8.6

27.0

SANYO: DIP30SD

[LC651432N/F/L, 651431N/F/L]

Package Dimensions

unit : mm

3196A-DIP30SD

115

16

7.6

0.65

9.75

0.5

5.6

0.1

1.5max

30

0.22

(0.33)

0.15

(1.3)

SANYO: SSOP30

[LC651432N/F/L, 651431N/F/L]

unit : mm

3191A-SSOP30

0.15

15.2

115

30 16

(0.6)

1.00.4

2.45max

(2.15)

0.1

0.65

7.9

10.5

SANYO: MFP30S

[LC651432N/F/L, 651431N/F/L]

unit : mm

3216B-MFP30S

No. 6498-3/39

LC651432N/F/L, 651431N/F/L

Function Overview

Parameter LC651432N/1431N LC651432F/1431F LC651432L/1431L

ROM

2048 × 8 bits (1432N/F/L)

Memory

1024 × 8 bits (1431N/F/L)

RAM

128 × 4 bits (1432N/F/L)

64 × 4 bits (1431N/F/L)

Instructions

Instruction set 80
Table reference Provided
Interrupts One external, one internal
Timers 8-bit timer with 4-bit prescaler

On-chip functions Stack levels 4

HALT instruction based

Standby function standby function

Provided
Number of ports Up to 25 I/O pins
Serial ports I/O in 4-bit or 8-bit units
I/O voltage 15 V max.

I/O ports Output current 10 mA typ. 20 mA max.

I/O circuit types Open drain (n channel) or built-in pull-up resistor output can be specified in 1-bit units.
Output level at reset High or low can be specified in port units (C and D ports only)
Square-wave output Possible
Minimum cycle time 2.77 µs (V

DD

≥ 3 V) 0.92 µs (VDD≥ 3 V) 3.84 µs (VDD≥ 2.2 V)

Characteristics Supply voltage 3 to 6 V 3 to 6 V 2.2 to 6 V

Supply current 1 mA typ. 1.5 mA typ. 1 mA typ.

RC oscillator (400 or 800 kHz typical)

RC oscillator (400 kHz typical)

Oscillator

Oscillator element Ceramic oscillator (400 kHz, Ceramic oscillator: 4 MHz Ceramic oscillator (400 kHz

800 kHz, 1 MHz, or 4 MHz) or 4 MHz)

Divider circuit option 1/1, 1/3, 1/4 1/1 1/1, 1/3, 1/4

Other features Package

DIP30S-D, MFP30S,

SSOP30

Note: Sanyo will be providing details on oscillator elements and oscillator circuit constants as recommended circuits are developed. Contact your Sanyo

representative for more information.

No. 6498-4/39

LC651432N/F/L, 651431N/F/L

Differences between the LC651432N/LC651431N and the LC6543N/LC6546N

This table lists the points that require care when replacing the LC6543N/LC6546N with the LC651432N/LC651431N in
completes end products.

Parameter LC651432N/1431N LC6543N/46N

Pdmax(1) : DIP 310 mW 250 mW

Allowable power dissipation Pdmax(2) : MFP 220 mW 150 mW

Pdmax(3) : SSOP 160 mW (This package not available.)

I/O voltage (PIO) V

IO

(3) added –0.3 to VDD+ 0.3

–0.3 to +15 V

(When open-drain output is used.)

–0.3 to VDD+ 0.3

(When a pull-up resistor is used.)

VIH(1) to VIH(7)

High-level input voltage V

IH

(n) (Associated with the I/O voltage (PI0) VIH(1) to VIH(6)

changes mentioned above.)

IIH(1) to IIH(3)

High-level input current I

IH

(n) (Associated with the I/O voltage (PI0) IIH(1) to IIH(2)

changes mentioned above.)

f

CFOSC

Oscillator frequency precision: ±2%

[OSC1, OSC2]

Recommended oscillator circuit constants Oscillator frequency precision: ±4%

Oscillator characteristics

(under evaluation)

Ceramic oscillator

800 kHz typical (V

DD

= 3 to 6 V) 850 kHz typical (VDD= 4 to 6 V)

Oscillator frequency

Circuit constant changes: Rext = 6.8 kΩ ±1% Circuit constant changes: Rext = 4.7 kΩ ±1%

2-pin RC oscillator f

MOSC

Sample-to-sample frequency variation: Sample-to-sample frequency variation:

Oscillator frequency [OSC1, OSC2]

595 to 1274 kHz 619 to 1144 kHz

400 kHz typical (VDD= 3 to 6 V) 400 kHz typical (VDD= 3 to 6 V)

Sample-to-sample frequency variation: Sample-to-sample frequency variation:

284 to 790 kHz 305 to 546 kHz

Current drain I

DD

1 mA typ. 2 mA typ.

Serial clock input clock cycle time t

CKCY

(1)[SCK] min. 2.0 µs min 3.0 µs

Package

DIP30S-D, MFP30S,

DIP30S-D, MFP30S

SSOP30 added

Differences between the LC651432F/LC651431F and the LC6543F/LC6546F

This table lists the points that require care when replacing the LC6543F/LC6546F with the LC651432F/LC651431F in
completes end products.

Parameter LC651432F/1431F LC6543F/46F

Pdmax(1) : DIP 310 mW 250 mW

Allowable power dissipation Pdmax(2) : MFP 220 mW 150 mW

Pdmax(3) : SSOP 160 mW (This package not available.)

Operating supply voltage V

DD

3 to 6 V 4.5 to 6 V

I/O voltage (PI0) V

IO

(3) added –0.3 to VDD+ 0.3

–0.3 to +15 V

(When open-drain output is used.)

–0.3 to VDD+ 0.3

(When a pull-up resistor is used.)

VIH(1) to VIH(7)

High-level input voltage V

IH

(n) (Associated with the I/O voltage (PI0) VIH(1) to VIH(6)

changes mentioned above.)

IIH(1) to IIH(3)

High-level input current I

IH

(n) (Associated with the I/O voltage (PI0) IIH(1) to IIH(2)

changes mentioned above.)

IIH(1) to IIH(3)

Low-level input voltage V

IL

(n) Specifications when VDD= 4 to 6 V Specifications when VDD= 4 to 6 V

Specifications added for V

DD

= 3 to 6 V

Oscillator characteristics

f

CFOSC

Ceramic oscillator

[OSC1, OSC2]

Oscillator frequency precision: ±2% Oscillator frequency precision: ±4%

Oscillator frequency

Current drain I

DD

1.5 mA typ. 2.5 mA typ.

Serial clock input clock cycle time t

CKCY

(1)[SCK] min. 2.0 µs min 3.0 µs

Package

DIP30S-D, MFP30S,

DIP30S-D, MFP30S

SSOP30 added

No. 6498-5/39

LC651432N/F/L, 651431N/F/L

Differences between the LC651432L/LC651431L and the LC6543L/LC6546L

This table lists the points that require care when replacing the LC6543L/LC6546L with the LC651432L/LC651431L in
completes end products.

Parameter LC651432L/1431L LC6543L/46L

Pdmax(1) : DIP 310 mW 250 mW

Allowable power dissipation Pdmax(2) : MFP 220 mW 150 mW

Pdmax(3) : SSOP 160 mW (This package not available.)

I/O voltage (PI0) V

IO

(3) added –0.3 to VDD+ 0.3

–0.3 to +15 V

(When open-drain output is used.)

–0.3 to VDD+ 0.3

(When a pull-up resistor is used.)

VIH(1) to VIH(7)

High-level input voltage V

IH

(n) (Associated with the I/O voltage (PI0) VIH(1) to VIH(6)

changes mentioned above.)

IIH(1) to IIH(3)

High-level input current I

IH

(n) (Associated with the I/O voltage (PI0) IIH(1) to IIH(2)

changes mentioned above.)

f

CFOSC

Oscillator frequency precision: ±2%

Oscillator characteristics

[OSC1, OSC2]

Recommended oscillator circuit constants Oscillator frequency precision: ±4%

Ceramic oscillator

(under evaluation)

Oscillator frequency 400 kHz typical (V

DD

= 2.2 to 6 V) 400 kHz typical (VDD= 2.2 to 6 V)

2-pin RC oscillator f

MOSC

Circuit constant changes: Rext = 15 kΩ ±1% Circuit constant changes: Rext = 12 kΩ ±1%

Oscillator frequency [OSC1, OSC2] Sample-to-sample frequency variation: Sample-to-sample frequency variation:

200 to 790 kHz 284 to 546 kHz

Current drain I

DD

1 mA typ. 2 mA typ.

Package

DIP30S-D, MFP30S,

DIP30S-D, MFP30S

SSOP30 added

Caution: Always test the end product thoroughly after changing the microcontroller used.

Pin Assignment

The same pin assignment is used for the DIP, MFP, and SSOP packages.

RES

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

PE2

PE1

PE0

PD3

PD2

PD1

PD0

PC3

PC2

PC1

PC0

VSS

TEST

OSC1

PA1

PE3

VDD

PF0/SI

PF1/SO

PF2/SCK

PF3/INT

PG0

PG1

PG2

PG3

PA0

PA2

PA3

PI0/OSC2

12

1

2

3

4

5

6

7

8

9

10

11

13

14

15

LC651432N/F/L
LC651431N/F/L

Pin Nomenclature

OSC1, OSC2: Connections for capacitor and resistor oscillator components or a ceramic oscillator element.
PG0 to 3: Shared-function I/O port G0 to 3 PI0: Shared-function I/O port IO
RES: Reset TEST:Test
PA0 to 3: Shared-function I/O port A0 to 3 INT: Interrupt request
PC0 to 3: Shared-function I/O port C0 to 3 SI: Serial input
PD0 to 3: Shared-function I/O port D0 to 3 SO: Serial output
PE0 to 3: Shared-function I/O port E0 to 3 SCK: Serial clock input or output pin
PF0 to 3: Shared-function I/O port F0 to 3

Notes: 1. The SI, SO, SCK, and INT pins are shared-function pins also used as PF0 to 3.

2. OSC2 and PIO are a single pin set exclusively to one or the other function as a user option.

Note: * OSC2 and PIO are a single pin set exclusively to one or the other function as a user option.

RAM: Data memory ROM: Program memory
F: Flags PC: Program counter
WR: Working register INT: Interrupt control
AC: Accumulator IR: Instruction register
ALU: Arithmetic and logic unit I.DEC: Instruction decoder
DP: Data pointer CF, CSF: Carry flag, carry save flag
E: E register ZF, ZSF: Zero flag, zero save flag
CTL: Control register EXTF: External interrupt request flag
OSC: Oscillator circuit TMF: Internal interrupt request flag
TM: Timer
STS: Status register

No. 6498-6/39

LC651432N/F/L, 651431N/F/L

LC651432N/F/L, LC651431N/F/L

Port A

Port C

Port D

Port E

Port F

Serial

shift

register

Serial

shift

register

Port G Port I

Serial
mode

register

Serial
mode

register

I/O buffer

RAM

I.DEC

E AC

ALU

CF

EXTF TMF

CSF ZSF

TM

CTL

INT

OSC

System bus

STS

DP

PA0 to 3

PC0 to 3

PD0 to 3

PE0 to 3

PF0 to 3

I/O bus

OSC1
OSC2*

IR

ROM

PC

STACK 1
STACK 2
STACK 3
STACK 4

RES
TEST
V

DD

V

SS

PF1/SO

Shared with port F

4/8 bits

4 bits

Lower digit

Higher

4/8 bits

PF0/SI

PF2/SCK

PF3/INT

FWR

PG0-3 PI0

*

ZF

System Block Diagram

Development Support

The following are available to support the development of LC651431 and LC651432 applications.

• User’s manual
“LC6543/46 User’s Manual” No. E71

• Development tool manual
See the “EVA86000 Development Tool Manual for 4-Bit Microcontrollers.”

• Software manual
“LC65/66 Series Software Manual”

• Development tools
Program development: EVA86000 System
Program evaluation: LC65E43 on-chip EPROM microcontroller

No. 6498-7/39

LC651432N/F/L, 651431N/F/L

Pins Functions

Count Pin I/O Function Options Reset state

Handling when
unused

1V

DD

— Power supply — — —

1V

SS

—

1 OSC1 Input • Connection for the external system clock 1. Single-pin external clock input — —

RC or ceramic oscillator element 2. 2-pin RC oscillator

• When a single pin is used for external clock 3. 2-pin ceramic oscillator
input, the PI0/OSC2 pin is used as the PI0 4. Divider circuit option
I/O port. • No divider

• When a 2-pin RC oscillator or a 2-pin ceramic • Divide-by-three circuit
oscillator is used, the PI0/OSC2 pin is used as • Divide-by-four circuit
the OSC2 oscillator pin.

4 PA0 to PA3 I/O • I/O port A0 to 3 1. Open-drain output • High-level The open-drain

Input in 4-bit units (IP instruction) 2. Built-in pull-up resistor output (with output option
Output in 4-bit units (OP instruction) Options 1 and 2 may be specified the output n- must be
Test in single-bit units (BP and BNP instructions) in bit units. channel selected and
Set/reset in single-bit units (SPB and RPB transistor off) the pin
instructions) connected to

• PA3 (Any one of PA0 to 3 can be selected) is V

SS

.

used for standby mode control.

• Applications must assure that key bounce or
similar noise does not occur on PA3

(or PA0 to 3)

during a HALT instruction execution cycle.

4 PC0 to PC3 I/O • I/O port C0 to 3 1. Open-drain output • High-level The same as

Provides the same functions as PA0 to 3. 2. Built-in pull-up resistor output

that for PC0 to 3

(See note.) 3. High-level output at reset • Low-level

• The output level at reset can be specified to be 4. Low-level output at reset output
either high or low. • Options 1 and 2 may be specified (Specified as a
Note: This port does not have the standby in bit units. user option.)

mode control function. • Options 3 and 4 are specified in

a single 4-bit group

4 PD0 to PD3 I/O • I/O port D0 to 3 The same as those for PC0 to 3. The same as The same as

Provides the same functions as PC0 to 3.

those for PC0 to 3. those for PC0 to 3.

Continued on next page.

No. 6498-8/39

LC651432N/F/L, 651431N/F/L

Continued from preceding page.

Count Pin I/O Function Options Reset state

Handling when
unused

4 PE0 to PE3 I/O • I/O port E0 to 3 1. Open-drain output • High-level The same as

Input in 4-bit units (IP instruction) 2. Built-in pull-up resistor output (with that for
Output in 4-bit units (OP instruction) Options 1 and 2 may be specified the output n- PA0 to 3.
Set/reset in single-bit units (SPB and RPB in bit units. channel
instructions) transistor off)
Test in single-bit units (BP and BNP instructions)

• PE0 also has a continuous pulse (64Tcyc)
output function.

4 PF0/SI I/O • I/O port F0 to 3 The same as those for PE0 to 3. The same as The same as

PF1/SO Functions and options identical to PE0 to 3. that for PE0 to 3. that for

PF2/SCK (See note.) The serial port PA0 to 3.

PF3/INT • PF0 to 3 have shared functions as the serial is disabled and

interface pins and the INT input. INT is the
Either function can be selected under program interrupt source.
control.
SI ... Serial input port
SO ... Serial output port
SCK ... Serial clock input or output
INT ... Interrupt request input
Serial input/output is switched between 4-bit
and 8-bit units under program control.
Note: This port does not have a continuous
pulse output function.

4 PG0 to PG3 I/O • I/O port G0 to 3 The same as those for PE0 to 3. The same as The same as

Functions and options identical to PE0 to 3. those for that for
(See note.) PE0 to 3. PA0 to 3.
Note: This port does not have a continuous
pulse output function.

1 PI0/OSC2 I/O • I/O port IO The same as those for PG0 to 3. The same as The same as

Output Functions and options identical to PG0 to 3. those for that for

• However, consists of a single bit. PG0 to 3. PA0 to 3.

• When a 2-pins oscillator is used, this pin
functions as the OSC2 pin, and the I/O port
function is not available.

1 RES Input • System reset input — — —

• Connect an external capacitor to implement a
power-on reset.

• The reset start operation requires that a low
level be held for at least 4 clock cycles.

1 TEST Input • IC test pin — — This pin must

This pin must be connected to V

SS

during be connected to

normal operation. V

SS

.

No. 6498-9/39

LC651432N/F/L, 651431N/F/L

Oscillator Circuit Options

Option Circuit Conditions and notes

The PI0/OSC2 pin is used as the PI0 pin.External clock

OSC1

The PI0/OSC2 pin is used as the OSC2 pin
and the port function is unavailable.

Two-pin RC oscillator

OSC1

PI0/OSC

Rext

Cext

The PI0/OSC2 pin is used as the OSC2 pin
and the port function is unavailable.

Ceramic oscillator

OSC1

PI0/OSC

R

C1

C2

Ceramic oscillator

element

Divider Circuit Options

Option Circuit Conditions and notes

• Applicable to all three oscillator options.

• The oscillator frequency or the external clock
must not exceed 1444 kHz. (LC651431N and
LC651432N)

• The oscillator frequency or the external clock
must not exceed 4330 kHz. (LC651431F and
LC651432F)

• The oscillator frequency or the external clock
must not exceed 1040 kHz. (LC651431L and
LC651432L)

No divider circuit (1/1)

f

OSC

Oscillator circuit

Timing

generator

• Only applicable to the external clock and the
ceramic oscillator option.

• The oscillator frequency or the external clock
must not exceed 4330 kHz.

Divide-by-three circuit (1/3)

f

OSC

Divide-by-three

circuit

f

OSC

3

Oscillator circuit

Timing

generator

• Only applicable to the external clock and the
ceramic oscillator option.

• The oscillator frequency or the external clock
must not exceed 4330 kHz.

Divide-by-four circuit (1/4)

f

OSC

Divide-by-four

circuit

f

OSC

4

Oscillator circuit

Timing

generator

Caution: The following table summarizes the oscillator and divider option combinations. Use care when selecting these options.

Oscillator Divider Options for the LC651431N/LC651432N, LC651431F/LC651432F, and
LC651431L/LC651432L

No. 6498-10/39

LC651432N/F/L, 651431N/F/L

LC651432N, LC651431N

Oscillator type Frequency Divider option (cycle time) VDDrange Notes

Ceramic oscillator 400 kHz 1/1 (10 µs) 3 to 6 V The divide-by-three and divide-by-four

circuits cannot be used.

800 kHz 1/1 (5 µs) 3 to 6 V

1/3 (15 µs) 3 to 6 V
1/4 (20 µs) 3 to 6 V

1 MHz 1/1 (4 µs) 3 to 6 V

1/3 (12 µs) 3 to 6 V
1/4 (16 µs) 3 to 6 V

4 MHz 1/3 (3 µs) 3 to 6 V The no-divider (1/1) option cannot be used.

1/4 (4 µs) 3 to 6 V

Single-pin external clock input 200 to 1444 kHz 1/1 (20 to 2.77 µs) 3 to 6 V

600 to 4330 kHz 1/3 (20 to 2.77 µs) 3 to 6 V
800 to 4330 kHz 1/4 (20 to 3.70 µs) 3 to 6 V

External clock provided by a As above
2-pin RC oscillator circuit

2-pin RC oscillator Using the no-divider (1/1) option and the 3 to 6 V

recommended circuit constants. If the use of circuit
values other than the recommended values is unavoidable, the
frequencies, divider options, and V

DD

ranges specified for the

single-pin external clock input option must be strictly observed.

External clock used with the The IC cannot be driven by an external clock with this option. If external clock drive is required, select either the external
ceramic oscillator option clock option or the 2-pin RC oscillator option

LC651432F, LC651431F

Oscillator type Frequency Divider option (cycle time) VDDrange Notes
Ceramic oscillator 4 MHz 1/1 (1 µs) 3 to 6 V
Single-pin external clock input 200 to 4330 kHz 1/1 (20 to 0.92 µs) 3 to 6 V
External clock used with the The IC cannot be driven by an external clock with this option. If external clock drive is required, select the external clock

ceramic oscillator circuit option.

LC651432L, LC651431L

Oscillator type Frequency Divider option (cycle time) VDDrange Notes
Ceramic oscillator 400 kHz 1/1 (10 µs) 2.2 to 6 V The divide-by-three and divide-by-four

circuits cannot be used.

4 MHz 1/4 (4 µs) 2.2 to 6 V The no-divider (1/1) and divide-by-three option

cannot be used.

Single-pin external clock input 200 to 1040 kHz 1/1 (20 to 3.84 µs) 2.2 to 6 V

600 to 3120 kHz 1/3 (20 to 3.84 µs) 2.2 to 6 V
800 to 4160 kHz 1/4 (20 to 3.84 µs) 2.2 to 6 V

External clock provided by a As above
2-pin RC oscillator circuit

2-pin RC oscillator Using the no-divider (1/1) option and the 2.2 to 6 V

recommended circuit constants. If the use of circuit
values other than the recommended values is unavoidable, the
frequencies, divider options, and V

DD

ranges specified for the

single-pin external clock input option must be strictly observed.

External clock used with the The IC cannot be driven by an external clock with this option. If external clock drive is required, select either the external
ceramic oscillator option clock option or the 2-pin RC oscillator option

No. 6498-11/39

LC651432N/F/L, 651431N/F/L

Port C and D Output Level at Reset Option

One of the following two options for the output level at reset may be chosen for the I/O ports C and D in 4-bit group
units.

Port Output Circuit Type Option

One of the following two options for the circuit type can be selected for the I/O ports in bit units.

Option Conditions and notes

High-level output at reset Ports C and D in 4-bit units

Low-level output at reset Ports C and D in 4-bit units

Option Circuit Applicable ports

• Not applicable to the PI0/OSC2 pin if either
the 2-pin RC oscillator or the ceramic
oscillator is selected as the oscillator circuit.

Open-drain output

Built-in pull-up resistor
output

Specifications

No. 6498-12/39

LC651432N/F/L, 651431N/F/L

Parameter Symbol Conditions Applicable pins Ratings Unit

Maximum supply voltage V

DD

max V

DD

–0.3 to +7.0 V

Voltages up to the

Output voltage V

O

OSC2 voltage generated V

are allowed.

Input voltage

VI(1) OSC1

*1

–0.3 to VDD+0.3 V

V

I

(2) TEST, RES –0.3 to VDD+0.3 V

V

IO

(1) Ports with open-drain specifications –0.3 to +15 V

I/O voltage

V

IO

(2)

Ports with pull-up resistor

–0.3 to VDD+0.3 V

specifications

V

IO

(3) PI0 –0.3 to VDD+0.3 V

Peak output current I

OP

I/O ports –2 to +20 mA

I

OA

Per single pin, the average over a

I/O ports –2 to +20 mA

100 ms period
The total current for PC0 to 3,

PC0 to 3

mA

Average output current

ΣI

OA

(1)

PD0 to 3, and PE0 to 3

*2

PD0 to 3 –15 to +100
PE0 to 3

The total current for PF0 to 3,

PF0 to 3, PI0

ΣI

OA

(2)

PG0 to 3, PA0 to 3, and PI0

*2

PG0 to 3 –15 to +100 mA
PA0 to 3

Pd max(1) Ta = –40 to +85°C (DIP package) 310 mW

Allowable power dissipation Pd max(2) Ta = –40 to +85°C (MFP package) 220 mW

Pd max(3) Ta = –40 to +85°C (SSOP package) 160 mW
Operating temperature Topr –40 to +85 °C
Storage temperature Tstg –55 to 125 °C

LC651432N, 651431N

Absolute Maximum Ratings at Ta = 25°C, VSS= 0 V

Parameter Symbol Conditions Applicable pins

Ratings

Unit

min typ max

Operating supply voltage V

DD

V

DD

3.0 6.0 V

Standby supply voltage V

ST

RAM and register contents

V

DD

1.8 6.0 V

retained.

*3

VIH(1)

With the n-channel output Ports with open-drain

0.7 V

DD

13.5 V

transistors off specifications (except for I0)

VIH(2)

With the n-channel output Ports with pull-up resistor

0.7 V

DD

V

DD

V

transistors off specifications (except for I0)

VIH(3)

With the n-channel output

Port I0 0.7 V

DD

V

DD

V

transistors off

High-level input voltage

VIH(4)

With the n-channel output The INT, SCK, and SI pins

0.8 V

DD

13.5 V

transistors off with open-drain specifications
With the n-channel output

The INT, SCK, and SI pins

V

IH

(5)

transistors off

with pull-up resistor 0.8 V

DD

V

DD

V

specifications

VIH(6) VDD= 1.8 to 6 V RES 0.8 V

DD

V

DD

V

V

IH

(7) External clock specifications OSC1 0.8 V

DD

V

DD

V

Allowable Operating Ranges at Ta = –40 to +85°C, VSS= 0 V, VDD= 3.0 to 6.0 V (unless otherwise specified)

Continued on next page.

No. 6498-13/39

LC651432N/F/L, 651431N/F/L

Continued from preceding page.

Parameter Symbol Conditions Applicable pins

Ratings

Unit

min typ max

With the n-channel output

V

IL

(1) transistors off Port V

SS

0.3 V

DD

V

V

DD

= 4 to 6 V

With the n-channel output

VIL(2) transistors off Port V

SS

0.25 V

DD

V

3 to 6 V
With the n-channel output

V

IL

(3) transistors off INT, SCK, SI V

SS

0.25 V

DD

V

V

DD

= 4 to 6 V

With the n-channel output

VIL(4) transistors off INT, SCK, SI V

SS

0.2 V

DD

V

Low-level input voltage 3 to 6 V

V

IL

(5)

External clock specifications

OSC1 V

SS

0.25 V

DD

V

V

DD

= 4 to 6 V

V

IL

(6)

External clock specifications

OSC1 V

SS

0.2 V

DD

V

3 to 6 V

V

IL

(7) VDD= 4 to 6 V TEST V

SS

0.3 V

DD

V

V

IL

(8) 3 to 6 V TEST V

SS

0.25 V

DD

V

V

IL

(9) VDD= 4 to 6 V RES V

SS

0.25 V

DD

V

V

IL

(10) 3 to 6 V RES V

SS

0.2 V

DD

V

A clock frequency of up to

Operating frequency

4.33 MHz may be used when
200 1444 kHz

(cycle time)

fop (Tcyc) either the divide-by-three

(20) (2.77) (µs)

circuit or the divide-by-four
circuit is used.

External clock conditions

Frequency text OSC1 200 4330 kHz

Pulse width textH, textL OSC1 69 ns

Rise and fall time textR, textF OSC1 50 ns

Recommended oscillator
circuit constants

Two-pin RC oscillator Cext

See figure 2. OSC1, OSC2

220 ± 5% pF
Rext 12 ±1% kΩ
Cext

See figure 2. OSC1, OSC2

220 ±5% pF

Rext 6.8 ±1% kΩ

Ceramic oscillator

*4

See figure 3.

See table 1.

See figure 1.
The divide-by-three circuit or

the divide-by-four circuit
must be used if the clock
frequency exceeds 1.444
MHz.

No. 6498-14/39

LC651432N/F/L, 651431N/F/L

Parameter Symbol Conditions Applicable pins

Ratings

Unit

min typ max

• With the output n-channel Open-drain specification ports
transistors off (except I0)

I

IH

(1)

(Including the n-channel

5.0 µA

transistor off leakage
current.)

•V

IN

= 13.5 V

High-level input current • With the output n-channel The I0 port with open-drain

transistors off specifications

IIH(2)

(Including the n-channel

1.0 µA

transistor off leakage
current.)

•V

IN

= V

DD

IIH(3)

• External clock mode

OSC1 1.0 µA

•V

IN

= V

DD

• With the output n-channel

I

IL

(1) transistors off Open-drain specification ports –1.0 µA

•V

IN

= V

SS

• With the output n-channel Built-in pull-up resistor

Low-level input current I

IL

(2) transistors off specification ports –1.3 –0.35 mA

•V

IN

= V

SS

IIL(3) VIN= V

SS

RES –45 –10 µA

I

IL

(4)

• External clock mode

OSC1 –1.0 µA

•V

IN

= V

SS

VOH(1)

•I

OH

= –50 µA Built-in pull-up resistor VDD– 1.2 V

High-level output voltage

•V

DD

=4.0 to 6.0 V specification ports

V

OH

(2) • IOH= –10 µA

Built-in pull-up resistor V

DD

– 0.5 V

specification ports

V

OL

(1)

•I

OL

= 10 mA

Ports 1.5 V

•V

DD

= 4.0 to 6.0 V

Low-level output voltage I

OL

= 1 mA, when IOLfor

V

OL

(2) all ports is less than or Ports 0.5 V

equal to 1 mA.

Hysteresis voltage V

HIS

RES, INT, SCK, SI, and

0.1 V

DD

V

High-level threshold voltage

V

tH

OSC1 with Schmitt trigger 0.4 V

DD

0.8 V

DD

V

Low-level threshold voltage

V

tL

specifications

*5

0.2 V

DD

0.6 V

DD

V

Current drain

*6

Two-pin RC oscillator • While operating, with the

output n-channel

I

DDOP

(1) transistors off V

DD

13mA

• Port voltage = V

DD

• Figure 2, fosc = 800 kHz
(typical)

Ceramic oscillator

I

DDOP

(2)

See figure 2.

V

DD

0.8 2.5 mA

fosc = 400 kHz (typical)

I

DDOP

(3)

• Figure 3, 4 MHz, divide-

V

DD

13mA

by-three circuit used.

External clock

I

DDOP

(4)

• Figure 3, 4 MHz, divide-

V

DD

13mA

by-four circuit used.

Standby mode I

DDOP

(5) See figure 3. 400 kHz V

DD

1 2.5 mA

I

DDOP

(6) See figure 3. 800 kHz V

DD

13mA

• 200 to 1444 kHz, no divider

• 600 to 4330 kHz, divide-

I

DDOP

(7) by-three circuit used V

DD

14mA

• 800 to 4330 kHz, divide­by-four circuit used

Output n-channel V

DD

0.05 10 µA

I

DDst

transistors off, VDD= 6 V
Port voltage = V

DD

, V

DD

0.025 5 µA

V

DD

= 3 V

Electrical Characteristics at Ta = –40 to +85°C, VSS= 0 V, VDD= 3.0 to 6.0 V (unless otherwise specified)

Schmitt characteristics

Continued on next page.

No. 6498-15/39

LC651432N/F/L, 651431N/F/L

Continued from preceding page.

Parameter Symbol Conditions Applicable pins

Ratings

Unit

min typ max

Oscillator characteristics

Ceramic oscillator • Figure 3, fo = 400 kHz OSC1, OSC2 392 400 408 kHz
Oscillator frequency • Figure 3, fo = 800 kHz OSC1, OSC2 784 800 816 kHz

f

CFOSC

*7

• Figure 3, fo = 1 MHz OSC1, OSC2 980 1000 1020 kHz

• Figure 3, fo = 4 MHz, OSC1, OSC2 3920 4000 4080 kHz
divide-by-three or divide­by-four circuit used.

Oscillator stabilization time

*8

• Figure 4, fo = 400 kHz 10 ms

• Figure 4, fo = 800 kHz, 10 ms

t

CFS

1 MHz, or 4 MHz, divide­by-three or divide-by-four
circuit used.

Two-pin RC oscillator •

Figure 2, Cext = 220 pF ±5%

OSC1, OSC2 595 800 1274 kHz

Oscillator frequency

f

MOSC

•

Figure 2, Rext = 6.8 kΩ ±1%

•

Figure 2, Cext = 220 pF ±5%

OSC1, OSC2

284 400 790 kHz

•

Figure 2, Rext = 12 kΩ ±1%

• Output n-channel Ports with built-in pull-up

Built-in pull-up resistor I/O ports

RPP transistors off resistor specifications 8 14 30 kΩ

RES • V

IN

= VSS, VDD= 5 V

Ru • V

IN

= VSS, VDD= 5 V RES 200 500 800 kΩ

External reset characteristics

Reset time t

RST

See figure 5.

• f = 1 MHz

Pin capacitance Cp • With all pins except the pin 10 pF

being tested at V

IN

= VSS.

Serial clock

Input clock cycle time t

CKCY

(1) See figure 6. SCK 2.0 µs

Output clock cycle time

t

CKCY

(2) See figure 6. SCK

64 ×

µs

T

CYC

*9

Input clock low-level pulse t

CKL

(1) See figure 6.

SCK 1.0 µs

width
Output clock low-level pulse

t

CKL

(2) See figure 6. SCK

32 ×

µs

width T

CYC

Input clock high-level pulse

t

CKH

(1) See figure 6. SCK 1.0 µs

width
Output clock high-level pulse

t

CKH

(2) See figure 6. SCK

32 ×

µs

width T

CYC

Serial input

Data setup time t

ICK

Stipulated with respect to SI 0.5 µs
the SCK rising edge.

Data hold time t

CKI

See figure 6. SI 0.5 µs

Serial output

Output delay time t

CKO

• Stipulated with respect to
the SCK falling edge.

• With external 1 kΩ
resistors and 50 pF SO 0.5 µs
capacitors on the
n-channel open-drain
outputs only.

• See figure 6.

Continued on next page.

No. 6498-16/39

LC651432N/F/L, 651431N/F/L

Continued from preceding page.

Notes: 1. Voltages up to the generated oscillation amplitude are allowed with internal drive using the oscillator circuit of figure 3 and the recommended circuit

constants.

2. The average over a 100 ms period.

3. Applications must hold the operating supply voltage V

DD

level from the point a HALT instruction is executed until the IC enters the standby state.

Also, switch bounce and similar noise must not appear on PA3 (or PA0 to 3) during the HALT instruction execution cycle.

4. The recommended circuit constants for which stable oscillation has been verified with the manufacturer of the oscillator element using the Sanyo
specified oscillator characteristics evaluation board.

5. The OSC1 pin has Schmitt trigger characteristics when either 2-pin RC oscillator or external clock input is specified as the oscillator option.

6. The result of measurement when the recommended external circuit constants are used with the Sanyo characteristics evaluation board. The current
due to the IC output transistors and pull-up resistor transistors is not included.

7. Indicates the frequency when f

CFOSC

is due to the use of the recommended circuit constants in table 1.

8. Indicates the required time for oscillation to stabilize starting from the point when V

DD

first exceeds the lower limit of the operating supply voltage

range. (See figure 4.)

9. T

CYC

= 4 × <system clock period>

Parameter Symbol Conditions Applicable pins

Ratings

Unit

min typ max

Pulse output

Period t

PCY

PE0 64 × µs

T

CYC

High-level pulse width t

PH

PE0 32 × µs

T

CYC

±10%

Low-level pulse width t

PL

PE0 32 × µs

T

CYC

±10%

• See figure 7

•T

CYC

= 4 × <system clock

period>

• With external 1 kΩ
resistors and external 50
pF capacitors on the n­channel open-drain outputs
only.

Figure 1 External Clock Input Waveform

Figure 2 Two-Pin RC Oscillator Circuit Figure 3 Ceramic Oscillator Circuit

No. 6498-17/39

LC651432N/F/L, 651431N/F/L

OSC1 (OSC2)

External clock

Open

V

DD

0.8 V

DD

0.2 V

DD

V

SS

texttext

text text

text

OSC1 OSC2

OSC1

OSC2

R

C2C1

Ceramic

oscillator

element

Cext

Rext

No. 6498-18/39

LC651432N/F/L, 651431N/F/L

Figure 4 Oscillator Stabilization Time

V

DD

OSC

0 V

Lower limit of the
operating V

DD

range

Stable oscillation

Oscillator

stabilization

time t

CFS

Figure 5 Reset Circuit

Note: When the power supply rise time is effectively zero, the reset

time for a C

RES

of 0.1 µF will be between 10 and 100 ms. If the
power supply rise time is relatively long, increase the value of
C

RES

so that the reset time is over 10 ms.

C

RES

( = 0.1 µF)

RES

Table 1 Ceramic Oscillator Recommended

Circuit Constants

4 MHz (Murata Mfg. Co., Ltd.) C1 33 pF ±10%
CSA4.00MG C2 33 pF ±10%
CST4.00MGW (Built-in capacitor) R 0 Ω
4 MHz (Kyocera Corporation) C1 33 pF ±10%
KBR4.0MSB C2 33 pF ±10%
KBR4.0MKC (Built-in capacitor) R 0 Ω
1 MHz (Murata Mfg. Co., Ltd.) C1 100 pF ±10%
CSB1000J C2 100 pF ±10%

R 2.2 kΩ
800 kHz (Murata Mfg. Co., Ltd.) C1 100 pF ±10%
CSB800J C2 100 pF ±10%

R 2.2 kΩ
400 kHz (Murata Mfg. Co., Ltd.) C1 220 pF ±10%
CSB400P C2 220 pF ±10%

R 2.2 kΩ

No. 6498-19/39

LC651432N/F/L, 651431N/F/L

Figure 6 Serial I/O Timing

0.8 V

DD

0.2 V

DD

V

DD

1 kΩ

50 pF

Load circuit

Input data

SCK

SI

SO

t

CKO

t

ICK

t

CKI

t

CKH

t

CKL

t

CKCY

Output data

Figure 7 Port PE0 Pulse Output Timing

t

PCY

t

PL

t

PH

0.7 V

DD

0.25 V

DD

The load conditions are the
same as those in figure 6.

LC651431N and LC651432N RC Oscillator Characteristics

Figure 8 shows the LC651431N and LC651432N RC oscillator characteristics.
However, the LC651431N and LC651432N have the following RC oscillator frequency sample-to-sample variations.

1) VDD= 3.0 to 6.0 V, Ta = –40 to 85°C
When the external circuit constants are: Cext = 220 pF, and

Rext = 12 kΩ, the frequency range will be:
284 kHz ≤ f

MOSC

≤ 790 kHz

2) VDD= 3.0 to 6.0 V, Ta = –40 to 85°C
When the external circuit constants are: Cext = 220 pF, and

Rext = 6.8 kΩ, the frequency range will be:
595 kHz ≤ f

MOSC

≤ 1274 kHz

Note that only the above circuit constants are guaranteed.

If using other values for these constants is unavoidable, use values in the following ranges.
Cext = 150 to 390 pF
Rext = 3 to 20 kΩ
(See figure 8.)

Notes: 10. The oscillator frequency must be in the range 350 to 750 kHz when VDD= 5.0 V and Ta = 25°C.

11. Applications must assure adequate margins so that oscillator frequency falls in the operating clock frequency range (in the oscillator divider option
table) for the ranges V

DD

= 3.0 to 6.0 V and Ta = –40 to 85°C.

No. 6498-20/39

LC651432N/F/L, 651431N/F/L

Figure 8 RC Oscillator Frequency Data (representative values)

These characteristics curves
are for reference purposes only.
These characteristics are not
guaranteed.

V

DD

= 5 (V)

Ta = 25°C

f MOSC [kHz]

f MOSC–Rext

Rext [kΩ]

1.5

1000

9
8
7
6

5
4

3

2

1000

1105432543

C = 150p

C = 270p

C = 390p

No. 6498-21/39

LC651432N/F/L, 651431N/F/L

Parameter Symbol Conditions Applicable pins Ratings Unit

Maximum supply voltage V

DD

max V

DD

–0.3 to +7.0 V

Voltages up to the

Output voltage V

O

OSC2 voltage generated V

are allowed.

Input voltage

VI(1) OSC1

*1

–0.3 to VDD+0.3 V

V

I

(2) TEST, RES –0.3 to VDD+0.3 V

V

IO

(1) Ports with open-drain specifications –0.3 to +15 V

I/O voltage

V

IO

(2)

Ports with pull-up resistor

–0.3 to VDD+0.3 V

specifications

V

IO

(3) PI0 –0.3 to VDD+0.3 V

Peak output current I

OP

I/O ports –2 to +20 mA

I

OA

Per single pin, the average over a

I/O ports –2 to +20 mA

100 ms period
The total current for PC0 to 3,

PC0 to 3

mA

Average output current

ΣI

OA

(1)

PD0 to 3, and PE0 to 3

*2

PD0 to 3 –15 to +100
PE0 to 3

The total current for PF0 to 3,

PF0 to 3, PI0

ΣI

OA

(2)

PG0 to 3, PA0 to 3, and PI0

*2

PG0 to 3 –15 to +100 mA
PA0 to 3

Pd max(1) Ta = –40 to +85°C (DIP package) 310 mW

Allowable power dissipation Pd max(2) Ta = –40 to +85°C (MFP package) 220 mW

Pd max(3) Ta = –40 to +85°C (SSOP package) 160 mW
Operating temperature Topr –40 to +85 °C
Storage temperature Tstg –55 to 125 °C

LC651432F, 651431F

Absolute Maximum Ratings at Ta = 25°C, VSS= 0 V

Parameter Symbol Conditions Applicable pins

Ratings

Unit

min typ max

Operating supply voltage V

DD

V

DD

3.0 6.0 V

Standby supply voltage V

ST

RAM and register contents

V

DD

1.8 6.0 V

retained.

*3

VIH(1)

With the n-channel output Ports with open-drain

0.7 V

DD

13.5 V

transistors off specifications (except for I0)

VIH(2)

With the n-channel output Ports with pull-up resistor

0.7 V

DD

V

DD

V

transistors off specifications (except for I0)

VIH(3)

With the n-channel output

Port I0 0.7 V

DD

V

DD

V

transistors off

High-level input voltage

VIH(4)

With the n-channel output The INT, SCK, and SI pins

0.8 V

DD

13.5 V

transistors off with open-drain specifications
With the n-channel output

The INT, SCK, and SI pins

V

IH

(5)

transistors off

with pull-up resistor 0.8 V

DD

V

DD

V

specifications

VIH(6) VDD= 1.8 to 6 V RES 0.8 V

DD

V

DD

V

V

IH

(7) External clock specifications OSC1 0.8 V

DD

V

DD

V

Allowable Operating Ranges at Ta = –40 to +85°C, VSS= 0 V, VDD= 3.0 to 6.0 V (unless otherwise specified)

Continued on next page.

No. 6498-22/39

LC651432N/F/L, 651431N/F/L

Continued from preceding page.

Parameter Symbol Conditions Applicable pins

Ratings

Unit

min typ max

With the n-channel output

V

IL

(1) transistors off Port V

SS

0.3 V

DD

V

V

DD

= 4 to 6 V

With the n-channel output

VIL(2) transistors off Port V

SS

0.25 V

DD

V

3 to 6 V
With the n-channel output

V

IL

(3) transistors off INT, SCK, SI V

SS

0.25 V

DD

V

V

DD

= 4 to 6 V

With the n-channel output

VIL(4) transistors off INT, SCK, SI V

SS

0.2 V

DD

V

Low-level input voltage 3 to 6 V

V

IL

(5)

External clock specifications

OSC1 V

SS

0.25 V

DD

V

V

DD

= 4 to 6 V

V

IL

(6)

External clock specifications

OSC1 V

SS

0.2 V

DD

V

3 to 6 V

V

IL

(7) VDD= 4 to 6 V TEST V

SS

0.3 V

DD

V

V

IL

(8) 3 to 6 V TEST V

SS

0.25 V

DD

V

V

IL

(9) VDD= 4 to 6 V RES V

SS

0.25 V

DD

V

V

IL

(10) 3 to 6 V RES V

SS

0.2 V

DD

V

Operating frequency 200 4330 kHz
(cycle time) fop (Tcyc) (20) (0.92) (µs)

External clock conditions

Frequency text OSC1 200 4330 kHz

Pulse width textH, textL See figure 1. OSC1 69 ns

Rise and fall time textR, textF OSC1 50 ns

Recommended oscillator
circuit constants

Ceramic oscillator

*4

See figure 2. See table 1.

No. 6498-23/39

LC651432N/F/L, 651431N/F/L

Parameter Symbol Conditions Applicable pins

Ratings

Unit

min typ max

• With the output n-channel Open-drain specification ports
transistors off (except I0)

I

IH

(1)

(Including the n-channel

5.0 µA

transistor off leakage
current.)

•V

IN

= 13.5 V

High-level input current • With the output n-channel The I0 port with open-drain

transistors off specifications

IIH(2)

(Including the n-channel

1.0 µA

transistor off leakage
current.)

•V

IN

= V

DD

IIH(3)

External clock mode

OSC1 1.0 µA

V

IN

= V

DD

• With the output n-channel

I

IL

(1) transistors off Open-drain specification ports –1.0 µA

•V

IN

= V

SS

• With the output n-channel Built-in pull-up resistor

Low-level input current I

IL

(2) transistors off specification ports –1.3 –0.35 mA

•V

IN

= V

SS

IIL(3) VIN= V

SS

RES –45 –10 µA

I

IL

(4)

External clock mode

OSC1 –1.0 µA

V

IN

= V

SS

VOH(1) • IOH= –50 µA

Built-in pull-up resistor

VDD– 1.2 V

High-level output voltage

specification ports

V

OH

(2) • IOH= –10 µA

Built-in pull-up resistor

VDD– 0.5 V

specification ports

V

OL

(1) • IOL= 10 mA Ports 1.5 V

Low-level output voltage I

OL

= 1 mA, when IOLfor

V

OL

(2) all ports is less than or Ports 0.5 V

equal to 1 mA.

Hysteresis voltage V

HIS

RES, INT, SCK, SI, and

0.1 V

DD

V

High-level threshold voltage

V

tH

OSC1 with Schmitt trigger 0.4 V

DD

0.8 V

DD

V

Low-level threshold voltage

V

tL

specifications

*5

0.2 V

DD

0.6 V

DD

V

Current drain

*6

Ceramic oscillator

I

DDOP

(1)

• Figure 2, 4 MHz*

V

DD

1.5 4 mA

External clock • 200 to 4330 kHz*

*:

Operating, with the output

I

DDOP

(2) n-channel transistors off, V

DD

14mA

port voltage = V

DD

Standby mode With the output n-channel

I

DDst

transistors off, VDD= 6 V V

DD

0.05 10 µA

Port voltage = VDD, VDD= 3 V

V

DD

0.025 5 µA

Electrical Characteristics at Ta = –40 to +85°C, VSS= 0 V, VDD= 3.0 to 6.0 V (unless otherwise specified)

Schmitt characteristics

Continued on next page.

No. 6498-24/39

LC651432N/F/L, 651431N/F/L

Continued from preceding page.

Parameter Symbol Conditions Applicable pins

Ratings

Unit

min typ max

Oscillator characteristics

Ceramic oscillator f

CFOSC

• Figure 2, fo = 4 MHz

*7

OSC1, OSC2 3920 4000 4080 kHz

Oscillator frequency

t

CFS

• Figure 3, fo = 4 MHz 10 ms

Oscillator stabilization time

*8

• Output n-channel Ports with built-in pull-up

Built-in pull-up resistor I/O ports

RPP transistors off resistor specifications 8 14 30 kΩ

RES • V

IN

= VSS, VDD= 5 V

Ru • V

IN

= VSS, VDD= 5 V RES 200 500 800 kΩ

External reset characteristics

Reset time t

RST

See figure 4.

• f = 1 MHz

Pin capacitance Cp • With all pins except the pin 10 pF

being tested at V

IN

= VSS.

Serial clock

Input clock cycle time t

CKCY

(1) See figure 5. SCK 2.0 µs

Output clock cycle time

t

CKCY

(2) See figure 5. SCK

64 ×

µs

T

CYC

*9

Input clock low-level pulse t

CKL

(1) See figure 5.

SCK 1.0 µs

width
Output clock low-level pulse

t

CKL

(2) See figure 5. SCK

32 ×

µs

width T

CYC

Input clock high-level pulse

t

CKH

(1) See figure 5. SCK 1.0 µs

width
Output clock high-level pulse

t

CKH

(2) See figure 5. SCK

32 ×

µs

width T

CYC

Serial input

Data setup time t

ICK

Stipulated with respect to SI 0.5 µs
the SCK rising edge.

Data hold time t

CKI

See figure 5. SI 0.5 µs

Serial output

Output delay time t

CKO

• Stipulated with respect to
the SCK falling edge.

• With external 1 kΩ
resistors and 50 pF SO 0.5 µs
capacitors on the
n-channel open-drain
outputs only.

• See figure 5

Pulse output

Period t

PCY

PE0 64 × µs

T

CYC

High-level pulse width t

PH

PE0 32 × µs

T

CYC

±10%

Low-level pulse width t

PL

PE0 32 × µs

T

CYC

±10%

• See figure 6

•T

CYC

= 4 × <system clock

period>

• With external 1 kΩ
resistors and external
50 pF capacitors on the
n-channel open-drain
outputs only.

Notes: 1. Voltages up to the generated oscillation amplitude are allowed with internal drive using the oscillator circuit of figure 2 and the recommended circuit

constants.

2. The average over a 100 ms period.

3. Applications must hold the operating supply voltage V

DD

level from the point a HALT instruction is executed until the IC enters the standby state.

Also, switch bounce and similar noise must not appear on PA3 (or PA0 to 3) during the HALT instruction execution cycle.

4. The recommended circuit constants for which stable oscillation has been verified with the manufacturer of the oscillator element using the Sanyo
specified oscillator characteristics evaluation board.

5. The OSC1 pin has Schmitt trigger characteristics when external clock is specified as the oscillator option.

6. The result of measurement when the recommended external circuit constants are used with the Sanyo characteristics evaluation board. The current
due to the IC output transistors and pull-up resistor transistors is not included.

7. Indicates the frequency when f

CFOSC

is due to the use of the recommended circuit constants in table 1.

8. Indicates the required time for oscillation to stabilize starting from the point when V

DD

first exceeds the lower limit of the operating supply voltage

range. (See figure 3.)

9. T

CYC

= 4 × <system clock period>

No. 6498-25/39

LC651432N/F/L, 651431N/F/L

Figure 1 External Clock Input Waveform

Figure 2 Ceramic Oscillator Circuit

OSC1 (OSC2)

External clock

Open

V

DD

0.8 V

DD

0.25 V

DD

V

SS

texttext

text text

text

OSC1

OSC2

R

C2C1

Ceramic

oscillator

element

No. 6498-26/39

LC651432N/F/L, 651431N/F/L

Figure 3 Oscillator Stabilization Time

V

DD

OSC

0 V

Lower limit of the
operating V

DD

range

Stable oscillation

Oscillator

stabilization

time t

CFS

Figure 4 Reset Circuit

Sanyo is currently requesting evaluation of oscillator element
products and recommended circuit constants from Kyocera
Corporation for their products, and thus these recommendations are
subject to change. Contact your Sanyo representative before using
these devices.

Note: When the power supply rise time is effectively zero, the reset

time for a C

RES

of 0.1 µF will be between 10 and 100 ms. If the
power supply rise time is relatively long, increase the value of
C

RES

so that the reset time is over 10 ms.

C

RES

( = 0.1 µF)

RES

Table 1 Ceramic Oscillator Recommended

Circuit Constants

4 MHz (Murata Mfg. Co., Ltd.) C1 33 pF ±10%
CSA4.00MG C2 33 pF ±10%
CST4.00MGW (Built-in capacitor) R 0 Ω
4 MHz (Kyocera Corporation) C1 33 pF ±10%
KBR4.0MSB C2 33 pF ±10%
KBR4.0MKC (Built-in capacitor) R 0 Ω

No. 6498-27/39

LC651432N/F/L, 651431N/F/L

Figure 5 Serial I/O Timing

0.8 V

DD

0.25 V

DD

V

DD

1 kΩ

50 pF

Load circuit

Input data

SCK

SI

SO

t

CKO

t

ICK

t

CKI

t

CKH

t

CKL

t

CKCY

Output data

Figure 6 Port PE0 Pulse Output Timing

t

PCY

t

PL

t

PH

0.7 V

DD

0.3 V

DD

The load conditions are the
same as those in figure 5.

No. 6498-28/39

LC651432N/F/L, 651431N/F/L

Parameter Symbol Conditions Applicable pins Ratings Unit

Maximum supply voltage V

DD

max V

DD

–0.3 to +7.0 V

Voltages up to the

Output voltage V

O

OSC2 voltage generated V

are allowed.

Input voltage

VI(1) OSC1

*1

–0.3 to VDD+0.3 V

V

I

(2) TEST, RES –0.3 to VDD+0.3 V

V

IO

(1) Ports with open-drain specifications –0.3 to +15 V

I/O voltage

V

IO

(2)

Ports with pull-up resistor

–0.3 to VDD+0.3 V

specifications

V

IO

(3) PI0 –0.3 to VDD+0.3 V

Peak output current I

OP

I/O ports –2 to +20 mA

I

OA

Per single pin, the average over a

I/O ports –2 to +20 mA

100 ms period
The total current for PC0 to 3,

PC0 to 3

mA

Average output current

ΣI

OA

(1)

PD0 to 3, and PE0 to 3

*2

PD0 to 3 –15 to +100
PE0 to 3

The total current for PF0 to 3,

PF0 to 3, PI0

ΣI

OA

(2)

PG0 to 3, PA0 to 3, and PI0

*2

PG0 to 3 –15 to +100 mA
PA0 to 3

Pd max(1) Ta = –40 to +85°C (DIP package) 310 mW

Allowable power dissipation Pd max(2) Ta = –40 to +85°C (MFP package) 220 mW

Pd max(3) Ta = –40 to +85°C (SSOP package) 160 mW
Operating temperature Topr –40 to +85 °C
Storage temperature Tstg –55 to 125 °C

LC651432L, 651431L

Absolute Maximum Ratings at Ta = 25°C, VSS= 0 V

Parameter Symbol Conditions Applicable pins

Ratings

Unit

min typ max

Operating supply voltage V

DD

V

DD

2.2 6.0 V

Standby supply voltage V

ST

RAM and register contents

V

DD

1.8 6.0 V

retained. *

2

VIH(1)

With the n-channel output Ports with open-drain

0.7 V

DD

13.5 V

transistors off specifications (except for I0)

VIH(2)

With the n-channel output Ports with pull-up resistor

0.7 V

DD

V

DD

V

transistors off specifications (except for I0)

VIH(3)

With the n-channel output

Port I0 0.7 V

DD

V

DD

V

transistors off

High-level input voltage

VIH(4)

With the n-channel output The INT, SCK, and SI pins

0.8 V

DD

13.5 V

transistors off with open-drain specifications
With the n-channel output

The INT, SCK, and SI pins

V

IH

(5)

transistors off

with pull-up resistor 0.8 V

DD

V

DD

V

specifications

VIH(6) VDD= 1.8 to 6 V RES 0.8 V

DD

V

DD

V

V

IH

(7) External clock specifications OSC1 0.8 V

DD

V

DD

V

V

IL

(1)

With the n-channel output

Ports V

SS

0.2 V

DD

V

transistors off

V

IL

(2)

With the n-channel output

INT, SCK, SI V

SS

0.2 V

DD

V

Low-level input voltage

transistors off

V

IL

(3) External clock specifications OSC1 V

SS

0.15 V

DD

V

V

IL

(4) TEST V

SS

0.22 V

DD

V

V

IL

(5) RES V

SS

0.15 V

DD

V

Allowable Operating Ranges at Ta = –40 to +85°C, VSS= 0 V, VDD= 2.2 to 6.0 V (unless otherwise specified)

Continued on next page.

No. 6498-29/39

LC651432N/F/L, 651431N/F/L

Continued from preceding page.

Parameter Symbol Conditions Applicable pins

Ratings

Unit

min typ max

When the built-in divide-by-

Operating frequency

four circuit is selected, the

200 1040 kHz

(cycle time)

fop (Tcyc) clock frequency upper limit

(20) (3.84) (µs)

is 4.16 MHz.

External clock conditions

Frequency text OSC1 200 4160 kHz

Pulse width textH, textL OSC1 120 ns

Rise and fall time textR, textF OSC1 100 ns

Recommended oscillator
circuit constants

Two-pin RC oscillator Cext

See figure 2. OSC1, OSC2

220 ± 5% pF

Rext 12 ±1% kΩ

Ceramic oscillator

*4

See figure 3.

See table 1.

Figure 1. If the clock
frequency exceeds 1.040
MHz, either the divide-by­three or the divide-by-four
divider circuit option must be
selected.

No. 6498-30/39

LC651432N/F/L, 651431N/F/L

Parameter Symbol Conditions Applicable pins

Ratings

Unit

min typ max

• With the output n-channel Open-drain specification ports
transistors off (except I0)

I

IH

(1)

(Including the n-channel

5.0 µA

transistor off leakage
current.)

•V

IN

= 13.5 V

High-level input current • With the output n-channel The I0 port with open-drain

transistors off specifications

IIH(2)

(Including the n-channel

1.0 µA

transistor off leakage
current.)

•V

IN

= V

DD

IIH(3)

External clock mode

OSC1 1.0 µA

V

IN

= V

DD

• With the output n-channel

I

IL

(1) transistors off Open-drain specification ports –1.0 µA

•V

IN

= V

SS

• With the output n-channel Built-in pull-up resistor

Low-level input current I

IL

(2) transistors off specification ports –1.3 –0.35 mA

•V

IN

= V

SS

IIL(3) VIN= V

SS

RES –45 –10 µA

I

IL

(4)

External clock mode

OSC1 –1.0 µA

V

IN

= V

SS

High-level output voltage V

OH

•IOH= –10 µA Built-in pull-up resistor VDD– 0.5 V

V

OL

(1) • IOL= 3 mA Ports 1.5 V

Low-level output voltage

I

OL

= 1 mA, when IOLfor

V

OL

(2) all ports is less than or Ports 0.4 V

equal to 1 mA.

Hysteresis voltage V

HIS

RES, INT, SCK, SI, and

0.1 V

DD

V

High-level threshold voltage

V

tH

OSC1 with Schmitt trigger 0.4 V

DD

0.8 V

DD

V

Low-level threshold voltage

V

tL

specifications

*5

0.2 V

DD

0.6 V

DD

V

Current drain

*6

Two-pin RC oscillator • While operating, with the

output n-channel

I

DDOP

(1) transistors off V

DD

0.8 2.5 mA

• Port voltage = V

DD

• Figure 2, fosc = 400 kHz
(typical)

Ceramic oscillator

I

DDOP

(2)

• Figure 3, 4 MHz, divide-

V

DD

13mA

by-four circuit used.

External clock

I

DDOP

(3)

• Figure 3, 4 MHz, divide-

V

DD

0.3 1 mA

by-four circuit used.
V

DD

= 2.2 V

Standby mode I

DDOP

(4) See figure 3. 400 kHz V

DD

1 2.5 mA

• 200 to 1024 kHz, no divider

• 600 to 3120 kHz, divide-

I

DDOP

(5) by-three circuit used V

DD

1.5 4 mA

• 800 to 4160 kHz, divide­by-four circuit used

Output n-channel V

DD

0.05 10 µA

I

DDst

transistors off, VDD= 6 V
Port voltage = V

DD

, V

DD

0.025 5 µA

V

DD

= 2.2 V

Electrical Characteristics at Ta = –40 to +85°C, VSS= 0 V, VDD= 2.2 to 6.0 V (unless otherwise specified)

Schmitt characteristics

Continued on next page.

No. 6498-31/39

LC651432N/F/L, 651431N/F/L

Continued from preceding page.

Parameter Symbol Conditions Applicable pins

Ratings

Unit

min typ max

Oscillator characteristics

Ceramic oscillator f

CFOSC

*7

• Figure 3, fo = 400 kHz OSC1, OSC2 392 400 408 kHz

Oscillator frequency • Figure 3, fo = 4 MHz, OSC1, OSC2 3920 4000 4080 kHz

divide-by-four circuit
used.

Oscillator stabilization time

*8

• Figure 4, fo = 400 kHz 10 ms

• Figure 4, fo = 800 kHz, 10 ms

t

CFS

1 MHz, or 4 MHz, divide­by-four circuit used.

Two-pin RC oscillator

f

MOSC

•

Figure 2, Cext = 220 pF ±5%

OSC1, OSC2 200 400 790 kHz

Oscillator frequency •

Figure 2, Rext = 12 kΩ ±1%

• Output n-channel Ports with built-in pull-up

Built-in pull-up resistor I/O ports

RPP transistors off resistor specifications 8 14 30 kΩ

RES • V

IN

= VSS, VDD= 5 V

Ru • V

IN

= VSS, VDD= 5 V RES 200 500 800

External reset characteristics

Reset time t

RST

See figure 5.

• f = 1 MHz

Pin capacitance Cp • With all pins except the pin 10 pF

being tested at V

IN

= VSS.

Serial clock

Input clock cycle time t

CKCY

(1) See figure 6. SCK 12.0 µs

Output clock cycle time

t

CKCY

(2) See figure 6. SCK

64 ×

µs

T

CYC

*9

Input clock low-level pulse t

CKL

(1) See figure 6.

SCK 4.0 µs

width
Output clock low-level pulse

t

CKL

(2) See figure 6. SCK

32 ×

µs

width T

CYC

Input clock high-level pulse

t

CKH

(1) See figure 6. SCK 4.0 µs

width
Output clock high-level pulse

t

CKH

(2) See figure 6. SCK

32 ×

µs

width T

CYC

Serial input

Data setup time t

ICK

Stipulated with respect to SI 0.5 µs
the SCK rising edge.

Data hold time t

CKI

See figure 6. SI 0.5 µs

Serial output

Output delay time t

CKO

• Stipulated with respect to
the SCK falling edge.

• With external 1 kΩ
resistors and 50 pF SO 2.0 µs
capacitors on the
n-channel open-drain
outputs only.

• See figure 6

Pulse output

Period t

PCY

PE0 64 × µs

T

CYC

High-level pulse width t

PH

PE0 32 × µs

T

CYC

±10%

Low-level pulse width t

PL

PE0 32 × µs

T

CYC

±10%

• See figure 7

•T

CYC

= 4 × <system clock

period>

• With external 1 kΩ

resistors and external
50 pF capacitors on the
n-channel open-drain
outputs only.

No. 6498-32/39

LC651432N/F/L, 651431N/F/L

Notes: 1. Voltages up to the generated oscillation amplitude are allowed with internal drive using the oscillator circuit of figure 3 and the recommended circuit

constants.

2. The average over a 100 ms period.

3. Applications must hold the operating supply voltage V

DD

level from the point a HALT instruction is executed until the IC enters the standby state.

Also, switch bounce and similar noise must not appear on PA3 (or PA0 to 3) during the HALT instruction execution cycle.

4. The recommended circuit constants for which stable oscillation has been verified with the manufacturer of the oscillator element using the Sanyo
specified oscillator characteristics evaluation board.

5. The OSC1 pin has Schmitt trigger characteristics when either 2-pin RC oscillator or external clock input is specified as the oscillator option.

6. The result of measurement when the recommended external circuit constants are used with the Sanyo characteristics evaluation board. The current
due to the IC output transistors and pull-up resistor transistors is not included.

7. Indicates the frequency when f

CFOSC

is due to the use of the recommended circuit constants in table 1.

8. Indicates the required time for oscillation to stabilize starting from the point when V

DD

first exceeds the lower limit of the operating supply voltage

range. (See figure 4.)

9. T

CYC

= 4 × <system clock period>

No. 6498-33/39

LC651432N/F/L, 651431N/F/L

Figure 1 External Clock Input Waveform

Figure 2 Two-Pin RC Oscillator Circuit Figure 3 Ceramic Oscillator Circuit

OSC1 (OSC2)

External clock

Open

V

DD

0.8 V

DD

0.15 V

DD

V

SS

texttext

text text

text

OSC1

OSC2

OSC1 OSC2

R

C2C1

Ceramic

oscillator

element

Cext

Rext

No. 6498-34/39

LC651432N/F/L, 651431N/F/L

Figure 4 Oscillator Stabilization Time

V

DD

OSC

0 V

Lower limit of the
operating V

DD

range

Stable oscillation

Oscillator

stabilization

time t

CFS

Figure 5 Reset Circuit

Note: When the power supply rise time is effectively zero, the reset

time for a C

RES

of 0.1 µF will be between 10 and 100 ms. If the
power supply rise time is relatively long, increase the value of
C

RES

so that the reset time is over 10 ms.

C

RES

( = 0.1 µF)

RES

Table 1 Ceramic Oscillator Recommended

Circuit Constants

4 MHz (Murata Mfg. Co., Ltd.) C1 33 pF ±10%
CSA4.00MGU C2 33 pF ±10%
CST4.00MGWU (Built-in capacitor) R 0 Ω
400 kHz (Murata Mfg. Co., Ltd.) C1 330 pF ±10%
CSB400P C2 330 pF ±10%

R 3.3 kΩ

No. 6498-35/39

LC651432N/F/L, 651431N/F/L

Figure 6 Serial I/O Timing

0.8 V

DD

0.2 V

DD

V

DD

1 kΩ

50 pF

Load circuit

Input data

SCK

SI

SO

t

CKO

t

ICK

t

CKI

t

CKH

t

CKL

t

CKCY

Output data

Figure 7 Port PE0 Pulse Output Timing

t

PCY

t

PL

t

PH

0.7 V

DD

0.25 V

DD

The load conditions are the
same as those in figure 6.

No. 6498-36/39

LC651432N/F/L, 651431N/F/L

LC651431L and LC651432L RC Oscillator Characteristics

Figure 8 shows the LC651431L and LC651432L RC oscillator characteristics.
However, the LC651431L and LC651432L have the following RC oscillator frequency sample-to-sample variations.

VDD= 2.2 to 6.0 V, Ta = –40 to 85°C
When the external circuit constants are: Cext = 220 pF, and

Rext = 12 kΩ, the frequency range will be:
200 kHz ≤ f

MOSC

≤ 790 kHz

Note that only the above circuit constants are guaranteed.

If using other values for these constants is unavoidable, use values in the following ranges.
Cext = 150 to 390 pF
Rext = 3 to 20 kΩ
(See figure 8.)

Notes: 10. The oscillator frequency must be in the range 350 to 500 kHz when VDD= 5.0 V and Ta = 25°C.

11. Applications must assure adequate margins so that oscillator frequency falls in the operating clock frequency range (in the oscillator divider option
table) for the ranges V

DD

= 2.2 to 6.0 V and Ta = –40 to 85°C.

Figure 8 RC Oscillator Frequency Data (representative values)

These characteristics curves
are for reference purposes only.
These characteristics are not
guaranteed.

V

DD

= 5 (V)

Ta = 25°C

f MOSC [kHz]

f MOSC–Rext

Rext [kΩ]

1.5

1000

9
8
7
6

5
4

3

2

1000

1105432543

C = 150p

C = 270p

C = 390p

Notes on PCB Construction

This section presents notes on noise as seen from the microcontroller itself and methods for reducing such noise when
designing the printed circuit board for a mass-produced product using these microcontrollers. The design techniques
presented here can be effective for preventing or avoiding problems (such as microcontroller malfunction and program
runaway) due to noise.

1. VDDand VSS: Power supply pins
Insert capacitors that meet the following conditions between the VDDand VSSpins.

• For each of the capacitors C1 and C2, make the wiring lengths from the IC as close to equal as possible (L1 = L1’

and L2 = L2’), and keep these lines as short as possible as well.

• Insert the capacitors C1, a large capacitor, and C2, a small capacitor, in parallel.

• The VDDand VSSlines in the printed circuit board pattern should be wider than any other lines.

2. OSC1 and OSC2: Clock input and output pins
When the ceramic oscillator option is selected (figure 2-1)

• Keep the length (L

OSC

) of the connection lines between the
clock I/O pins (input: OSC1, output: OSC2) and the
external components as short as possible.

• Keep the length (L

VSS

+ L1 (L2)) from the VSSside of the
capacitor connected to the oscillator element to the VSSpin
as short as possible.

• VSSline for the oscillator circuit and other VSSlines
should branch from a point nearest to the VSSpin.

• There are cases where the values of the oscillator circuit
components (the capacitors C1 and C2, the limit resistor
Rd, and other components) must be modified from the
values recommended in this document to adjust the
oscillator frequency. Consult with the oscillator element
manufacturer when determining the component values.

When the 2-pin RC oscillator option is selected (figure 2-2)

• Keep the length (L

OSC

) of the connection lines between the
clock I/O pins (input: OSC1, output: OSC2) and the
external components (the capacitor Cext and the resistor
Rext) as short as possible.

• Keep the length (L

VSS

+ Lc) from the VSSside of the
capacitor connected to the oscillator element to the VSSpin
as short as possible.

• VSSline for the oscillator circuit and other VSSlines should branch from a point nearest to the VSSpin.

No. 6498-37/39

LC651432N/F/L, 651431N/F/L

Figure 2-1 Oscillator Circuit Example 1

(ceramic oscillator)

V

SS

V

DD

L1

L2

C2C1

+

L1’

L2’

L

VSS

V

SS

OSC2

OSC1

C1

C2

Rd

L1

L2

L

OSC

Figure 2-2 Oscillator Circuit Example 2

(2-pin RC oscillator)

V

SS

OSC1
OSC2

L

VSS

Lc

L

OSC

Rext

Cext

When the external oscillator option is selected (figure 2-3)

• Keep the length (L

OSC

) of the line between the external
oscillator and the IC clock input pin (OSC1) as short as
possible.

• Also keep the length (L

OSC

) of the lines between the
external oscillator and the VDDand VSSused as short as
possible.

Other common points:

• Keep signals that change rapidly and large-amplitude signals
connected to medium-voltage handling ports as far away from
the oscillator circuit as possible and do not allow such lines to
cross lines related to clock signals.

3. RES: Reset pin

• Keep the line from the external reset circuit to the RES pin as short as possible.

• Keep the length (L1, L2) of the lines from the capacitor (Cres) inserted between RES and VSSas short as possible.

4. TEST: Test pin

• Keep the line that connects the TEST pin to VSSas short as possible.

• Take the line that connects the TEST pin to VSSfrom a location as close to the VSSpin as possible.

No. 6498-38/39

LC651432N/F/L, 651431N/F/L

Figure 2-3 Oscillator Circuit
Example 3 (external oscillator)

Figure 3 RES Pin Wiring

L

OS

External
oscillator

V

SS

V

DD

OSC1
PI0

V

SS

L2

Cres

L1

Lres

RES

External

circuit

Figure 4 TEST Pin Wiring

V

SS

TEST

L

PS No. 6498-39/39

LC651432N/F/L, 651431N/F/L

This catalog provides information as of April, 2000. Specifications and information herein are subject to
change without notice.

Specifications of any and all SANYO products described or contained herein stipulate the performance,
characteristics, and functions of the described products in the independent state, and are not guarantees
of the performance, characteristics, and functions of the described products as mounted in the customer’s
products or equipment. To verify symptoms and states that cannot be evaluated in an independent device,
the customer should always evaluate and test devices mounted in the customer’s products or equipment.

SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all
semiconductor products fail with some probability. It is possible that these probabilistic failures could
give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire,
or that could cause damage to other property. When designing equipment, adopt safety measures so
that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective
circuits and error prevention circuits for safe design, redundant design, and structural design.

In the event that any or all SANYO products (including technical data, services) described or contained
herein are controlled under any of applicable local export control laws and regulations, such products must
not be exported without obtaining the export license from the authorities concerned in accordance with the
above law.

No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system,
or otherwise, without the prior written permission of SANYO Electric Co., Ltd.

Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification”
for the SANYO product that you intend to use.

Information (including circuit diagrams and circuit parameters) herein is for example only; it is not
guaranteed for volume production. SANYO believes information herein is accurate and reliable, but
no guarantees are made or implied regarding its use or any infringements of intellectual property rights
or other rights of third parties.

5. I/O pins
All of the pins on these microcontrollers are shared-function I/O pins.

• When used as input pins, insert limiting resistors and keep the connection lines as short as possible.
Supplement: This can be effective in preventing or avoiding microcontroller problems (such as malfunctions and

program runaway), not only in printed circuit board design, but in selecting the microcontroller option
types discussed below and when considering application program specifications.

• If signals are input when the microcontroller power supply is unstable, select the medium-voltage (n-channel open

drain) output as the output circuit type for that pin, and also insert a limiting resistor as close to the pin as possible.

• Always adopt key bounce elimination techniques when inputting external signals to any microcontroller pin.

• Periodically refresh the pin output data with an output instruction (OP or SPB).

• When reading data input to a shared-function (bidirectional) I/O pin, set the value of the output data for that pin to 1

on every read operation with an output instruction (OP or SPB).

6. Unused pins

• Refer to the pin functions table in the user’s manual for the product itself or in the relevant Sanyo Semiconductor

Development Report.

The information presented in this document consists of examples, and its use is not guaranteed in mass-produced end
products. In actual product design (including the selection of circuit component values), we strongly recommend
using the materials presented here as a reference and performing thorough evaluation and testing.