Page 1
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
Overview
The LC5822, LC5823, and LC5824 are CMOS
microcontrollers that feature the low-voltage operation
required for battery-power applications and that provide
4 KB, 6 KB, or 8 KB of ROM, 1 kilobit of RAM, and an
LCD driver.
These microcontrollers support an instruction set based on
that of the earlier LC5800, LC5812, and LC5814 for
excellent efficiency in software development.
Applications
• LCD display in multi-function watches, timers, and
other products
• Control and LCD display in timers
• Control and LCD display in miniature test equipment,
health maintenance equipment, and other products
• These microcontrollers are optimal for products that
include an LCD display, especially battery powered
products.
Wide Allowable Operating Ranges
Note*: When the backup flag is set, the BAK pin is connected to VDD.
Features
• These microcontrollers are high-end versions of the
LC5800 and provide the following features.
Low Current Drain * In halt mode (typical)
• Ceramic oscillator 400 kHz (3.0 V) 200 µA
• Crystal oscillator 32 kHz (1.5 V, Ag specifications)
3.0 µA (LCD biases other than 1/3) 4.5 µA (LCD drive:
1/3 bias)
• Crystal oscillator 32 kHz (3.0 V, Li specifications)
2.0 µA (LCD biases other than 1/3) 6.0 µA (LCD drive:
1/3 bias)
Timer and Counter Functions
• One 8-bit programmable timer (May be used as an event
counter)
• One 8-bit programmable reload timer
• Time base timer (for clocks)
• Watchdog timer
• 8-bit serial I/O (3-pin synchronous system)
Standby Functions
• Clock standby function (halt mode)
Only the oscillator circuits, the divider circuit, and the
LCD driver operate. All other internal operations are
stopped. This provides a power-saving function in which
current drain is minimized, and allows a clock function
to be implemented easily with low power dissipation.
Furthermore, low-speed and high-speed modes can be
implemented by setting the operating modes of the two
oscillator circuits.
• Full standby function (hold mode)
• Halt mode can be cleared by any of two external and
two internal interrupts.
CMOS IC
82198RM (OT) No. 5944-1/24
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
4-Bit Single-Chip Microcontrollers Featuring 4 KB to 8 KB of ROM, 1 Kbit of RAM,
and an LCD Driver for Medium Speed Small-Scale Control Applications
LC5824, LC5823, LC5822
Ordering number : EN5944
Power Cycle Supply
options times voltage Notes
supply range
EXT-V 10 µs V
DD
= 2.3 to 3.6 V
When an 800-kHz ceramic
oscillator is used
EXT-V 20 µs V
DD
= 2.3 to 3.6 V
When an 400-kHz ceramic
oscillator is used
EXT-V 61 µs V
DD
= 2.3 to 3.6 V
When an 65-kHz crystal oscillator
is used
EXT-V 122 µs V
DD
= 2.0 to 3.6 V
When an 32-kHz crystal oscillator
is used
Li 122 µs V
DD
= 2.6 to 3.6 V*
When an 32-kHz crystal oscillator
is used
Ag 122 µs V
DD
= 1.3 to 1.65 V
When an 32-kHz crystal oscillator
is used
Page 2
Improved I/O Functions
• External interrupt pins
• Input pins that can clear halt mode:
10 pins (maximum)
• Input ports with input resistors that can be controlled
from software: 8 pins (maximum)
• Pins with a function that prevents the input port floating
state: 8 pins (maximum)
• LCD drive pins: 4 pins (common), 42 pins (segment outputs)
• General-purpose I/O ports:
16 pins (when all 4 P port pins are used)
• General-purpose inputs: 8 pins
• General-purpose outputs (1):1 pin (the ALM pin)
• General-purpose outputs (2):
42 pins (when all 42 of the
LCD segment outputs are
switched over to function as
general-purpose outputs)
• 8-bit serial output port: 1 set (3 pins: output, input,
and clock)
Functional Overview
• Program ROM: 4096 × 16 bits LC5824
3072 × 16 bits LC5823
2048 × 16 bits LC5822
• Internal RAM: 256 × 4 bits
• All instructions execute in a single cycle.
• Extensive set of interrupt functions for clearing halt and
hold mode
— 8 halt mode clearing functions
— 5 hold mode clearing functions
— 6 interrupt functions
— Subroutines can be nested up to 8 levels (Special-
purpose registers that are shared with the interrupt
function are built in.)
• Powerful hardware to increase system processing capacity
— Segment port related hardware
Built-in segment PLA circuit
Built-in segment decoder
Support for six different LCD drive specifications
Outputs can be switched to CMOS levels
— Built-in 8-bit synchronous serial I/O circuit
— 8-bit read/write timer (plus a separate 8-bit
prescaler; can be used as and event counter)
— 8-bit reload timer (plus built-in 8-bit prescaler)
— Built-in 8-bit prescaler (for use with timer 1, timer 2,
and the serial counter)
— All of RAM can be used a working area (RAM bank
system)
— Dedicated data pointer register for RAM access
— 15-stage divider circuit for clocks (also used as the
LCD voltage alternation frequency generator)
— 8-bit table reference function (reads 8-bit ROM data)
— Chattering prevention circuit (on two ports)
— Alarm signal generation circuit
• LCD panel drive output pins with high flexibility
(42 pins)
— The LCD output pins can be switched to function as
general-purpose outputs.
CMOS/p-channel/n-channel type combinations: Up
to 42 pins
— An alternation frequency appropriate for the LCD
panel used can be selected.
• An oscillator appropriate for your system’s specifications
can be selected.
— A 32- or 65-kHz crystal oscillator can be selected
(Used when a clock function is required or for low
current drain operation.)
— A ceramic oscillator with a frequency from 400 kHz
to 2 MHz can be selected (when high-speed
operation is required.)
Available delivery formats: QIP-80 and chip
Package Dimensions
unit: mm
3174-QFP80E
No. 5944-2/24
LC5824, LC5823, LC5822
Drive system Number of driven segments
Required number of common pins
bias · duty 168 segments 4 pins
bias · duty 126 segments 3 pins
bias · duty 168 segments 4 pins
bias · duty 126 segments 3 pins
bias · duty 84 segments 2 pins
Static drive 42 segments 1 pin
[LC5824, 5823, 5822]
SANYO: QIP80E
Page 3
Pin Assignment
No. 5944-3/24
LC5824, LC5823, LC5822
Top view
Page 4
No. 5944-4/24
LC5824, LC5823, LC5822
Pad Arrangement
Chip size: 4.92 mm × 5.15 mm
Pad size: 120 µm × 120 µm
Chip thickness 480 µm (chip specifications)
Pad Coordinates
PAD No. Pin
Coordinates
X
µmY µm
60 Seg 22 –2030 –2178
61 Seg 23 –1850 –2178
62 Seg 24 –1670 –2178
63 Seg 25 –1490 –2178
64 Seg 26 –1310 –2178
65 Seg 27 –1130 –2178
66 Seg 28 –950 –2178
67 Seg 29 –770 –2178
68 Seg 30 –590 –2178
69 Seg 31 –410 –2178
70 Seg 32 –230 –2178
71 Seg 33 –50 –2178
72 Seg 34 122 –2178
73 Seg 35 302 –2178
74 Seg 36 482 –2178
75 Seg 37 662 –2178
76 Seg 38 842 –2178
77 Seg 39 1022 –2178
78 Seg 40 1202 –2178
79 Seg 41 1382 –2178
80 Seg 42 1562 –2178
81 XC 1774 –2178
82 XTOUT 1954 –2178
83 XTIN 2134 –2178
1 V
DD
2257 –1959
2 V
SS
2257 –1779
3 CFIN/P1 2257 –1599
4 CFOUT/P2 2257 –1402
PAD No. Pin
Coordinates
X
µmY µm
5 VDD3 2257 –1212
6 V
DD
2/BAK 2257 –1032
7 V
DD
1 2257 –852
8 ALM 2257 –601
9 SO1 2257 –419
10 SO2 I/O port 2257 –236
11 SO3 I/O port 2257 56
12 SO4 I/O port 2257 132
13 M1 2257 364
14 M2 I/O port 2257 544
15 M3 I/O port 2257 724
16 M4 I/O port 2257 904
17 RES I/O port 2257 1636
18 Test 2330 1998
19 Test 2330 2178
20 TST 2150 2178
21 CUP1 1970 2178
22 CUP2 1790 2178
23 Seg 1 1606 2178
24 Seg 2 1426 2178
25 Seg 3 1246 2178
26 Seg 4 1066 2178
27 Seg 5 886 2178
28 Seg 6 706 2178
29 Seg 7 526 2178
30 Seg 8 346 2178
31 Seg 9 166 2178
32 Seg 10 –14 2178
PAD No. Pin
Coordinates
X
µmY µm
33 Seg 11 –194 2178
34 Seg 12 –374 2178
35 Seg 13 –546 2178
36 Seg 14 –726 2178
37 Seg 15 –906 2178
38 Seg 16 –1086 2178
39 Seg 17 –1266 2178
40 Seg 18 –1446 2178
41 Seg 19 –1626 2178
42 Seg 20 –1806 2178
43 Seg 21 –1986 2178
44 COM1 –2270 1871
45 COM2 –2270 1628
46 S1 –2270 1367
47 S2 Input port –2270 1140
48 S3 Input port –2270 960
49 S4 Input port –2270 734
50 K1 –2270 328
51 K2 Input port –2270 88
52 K3 Input port –2270 –140
53 K4 Input port –2270 –380
54 A1 –2270 –593
55 A2 I/O ports –2270 –773
56 A3 I/O ports –2270 –953
57 A4 I/O ports –2270 –1133
58 COM3/P3 –2270 –1602
59 COM4/P4 –2270 –1846
Note: • The pin numbers are the QIP-80E mass-production package pin numbers.
• The test pin (TST) must be connected to V
SS
.
• Pads number 42 and 43 in the chip version must be left open.
• Do not use solder dip techniques to mount the QIP-80E package version.
• In the chip version, the substrate must be either connected to V
SS
or left open.
Page 5
System Block Diagram
No. 5944-5/24
LC5824, LC5823, LC5822
RAM: Data memory
ROM: Program memory
DP: Data pointer register
BNK: Bank register
APG: RAM page flag
AC: Accumulator
ALU: Arithmetic and logic unit
B: B register
OPG: ROM page flag
PC: Program counter
IR: Instruction register
STS1: Status register 1
STS2: Status register 2
STS3: Status register 3
STS4: Status register 4
PLA: Programmed logic array used for segment data and strobe functions
WAIT.C:Wait time counter
Address
Buffer
Accumulator
(AC) (4 bits)
Data I/O - D bus
Timer 1
Timer 2
Carrier control circuit
Interrupt control
Watchdog timer
LCD driver
Reset
circuit
Chronograph
circuit
Chronograph
control circuit
Switch-
ing
circuit
System clock
generator
Voltage step-
Serial I/O
B register
(4 bits)
OPG
(2 bits)
Program
counter
(13 bits)
Clock timer
(15 bits)
Alarm tone
generator
Segment decoder
strobe decoder
Table
reference
Crystal
oscillator
circuit
(32 kHz/65 kHz)
CF/RC oscillator
circuit
(400 kHz to
4 MHz)
Page 6
No. 5944-6/24
LC5824, LC5823, LC5822
Pin Functions
Pin No. Pin I/O Function Options Status at reset
24
25
V
DD
V
SS
—
—
30
29
28
V
DD
1
V
DD
2/BAK
V
DD
3
—
—
—
LCD drive power supply
Power supply
Pin
• Ag specifications
• Li specifications
• EXT-V specifications
42
43
CUP1
CUP2
——Connections of the LCD power supply step-up (step-down)
capacitors
26
27
CFIN
CFOUT
Input
Output
System clock oscillator connections
• Ceramic element connections (CF specifications)
• RC component connections (RC specifications)
*: This oscillator circuit is stopped when a STOP or SLOW
instruction is executed.
• CF specifications
• RC specifications
• Unused
23
22
XTIN
XTOUT
Input
Output
Used for reference counting (clock specifications, LCD
alternation frequency) and as the system clock.
• 32-kHz crystal oscillator
• 65-kHz crystal oscillator
*: This oscillator circuit is stopped when a STOP instruction is
executed.
• 32-kHz specifications
• 65-kHz specifications
• 38-kHz specifications
• Unused
— XC —
Used for the phase compensation capacitor connected between
this pin and XTOUT and XTIN. This pin is only used in the chip
product.
67
68
69
70
S1
S2
S3
S4
Input
Input-only port
• Input pins used to acquire input data to RAM
• 1.95-ms and 7.8-ms chattering exclusion circuits included.
• Pull-down resistors are built in.
Note: the 1.95 ms and 7.8 ms values are for a ø0 of
32.768 kHz.
• Presence or absence of
low-level hold
transistors
• Pull-down resistors
enabled
Note: After a reset is
cleared, these pins go to
the floating state.
71
72
73
74
K1
K2
K3
K4
Input
Input-only port
• Input pins used to acquire input data to RAM
• 1.95-ms and 7.8-ms chattering exclusion circuits included.
• Pull-down resistors are built in.
Note: the 1.95 ms and 7.8 ms values are for a ø0 of
32.768 kHz.
• Presence or absence of
low-level hold
transistors
• Pull-down resistors
enabled
Note: After a reset is
cleared, these pins go to
the floating state.
36
37
38
39
M1
M2
M3
M4
I/O
I/O port
• Input pins used to acquire input data to RAM.
• Output pins used to output RAM data.
• M4 is also used as the TM1 external clock input in TM1 mode 3.
• M3 is also used for HEF8 halt mode clear control.
*: The minimum period for clock signal inputs is twice the cycle
time
• Pull-down resistors are built in.
• Presence or absence of
low-level hold
transistors
• Output type: CMOS or
p-channel
• Pull-down resistors
enabled
Note: After a reset is
cleared, these pins go to
the floating state.
• Input mode
• The output latch data is
set to 1.
26
27
79
80
P1
P2
P3
P4
I/O
I/O port
• Input pins used to acquire input data to RAM.
• Output pins used to output RAM data.
• Pull-down resistors are built in.
The same as those for
M1 to M4. However, only
for valid ports.
The same as those for
M1 to M4. However, only
for valid ports.
76
77
78
79
A1
A2
A3
A4
I/O
I/O port
• Input pins used to acquire input data to RAM.
• Output pins used to output RAM data.
• Pull-down resistors are built in.
• A1 is also used as the external interrupt request control input
signal (INT).
The same as those for
M1 to M4.
The same as those for
M1 to M4.
Continued on next page.
Power supply
specifications
Page 7
No. 5944-7/24
LC5824, LC5823, LC5822
Continued from preceding page.
Pin No. Pin I/O Function Options Status at reset
32
33
34
35
SO1
SO2
SO3
SO4
I/O
I/O port
• Input pins used to acquire input data to RAM.
• Output pins used to output RAM data.
• Pull-down resistors are built in.
SO1 to SO3 are also used as the serial interface pins.
• The serial interface function can be selected under program
control.
• Pin functions:
SO1: Serial input
SO2: Serial output
SO3: Serial clock
The serial clock can be taken from either internal or external
sources, and can be set up to detect either rising or falling
edges under program control.
Identical to M1 throughM4Identical to M1 through
M4
31 ALM Output
Output-only pin
• A signal modulated by ø0, ø3, or ø4 can be output under
program control.
Low-level output
40 RES Input
IC internal reset input
• The program counter is set to point to location 00H.
• The reset input level can be set to be either high or low.
• Either a pull-up or a pull-down resistor is built in.
Note: Applications must apply the reset signal level for at least
500 µs to effect a reset.
• Selection of a pull-up or
pull-down resistor
• Selection of active-low
or active-high reset
logic
44
64
1
21
Seg 22
Seg 21
Seg 22
Seg 42
Output
LCD panel drive outputs/general-purpose outputs
• LCD panel drive
(1) Static
(2) 1/2 bias 1/2 duty
(3) 1/2 bias 1/3 duty
(4) 1/2 bias 1/4 duty
(5) 1/3 bias 1/3 duty
(6) 1/3 bias 1/4 duty
One of items (1) through (5) is selected as a mask option.
• General-purpose output ports
(1) CMOS output
(2) p-channel open-drain output
(3) n-channel open-drain output
One of items (1) through (3) is selected as a mask option.
• The adoption of the segment PLA in these microcontrollers
means that there is no need for programs to control the
LCD/general-purpose output states of these pins.
• Output latch control is supported in the oscillator stopped
standby states and during a reset.
• Any combination of LCD and general-purpose output functions
may be used.
• Switching between LCD
drive output and
general-purpose output
• Switching between the
LCD drive type options
—Static
—1/2 bias 1/2 duty
—1/2 bias 1/3 duty
—1/2 bias 1/4 duty
—1/3 bias 1/3 duty
—1/3 bias 1/4 duty
• General-purpose output
type switching
—CMOS
—p-channel open-drain
—n-channel open-drain
• Standby mode output
latch control
• When used for LCD
drive:
—All lit
—All off
*Determined by the
master options
• When used as generalpurpose outputs:
—High level
—Low level
*Determined by the
master options
Note: When a
combination of LCD drive
and general-purpose
outputs is selected, these
pins will be either:
All lit/high-level output, or
All off/low-level output.
• During the reset period,
the LCD drive functions
as static drive.
65
66
79
80
COM1
COM2
COM3
COM4
Output
Common drive outputs for the LCD panel
The table below lists which pins are used in each of the drive
types.
However, note that the listed alternation frequencies are the
typical specifications when ø0 is 32.768 kHz.
41 TST Input
Test input
• In the QIP-80 version, this pin must be connected to V
SS
.
• In the chip version, this pin must be left open or connected to
V
SS
.
—
—
TEST
TEST
—
—
Test pins.
(These are not used in the device user interface.)
Note: Note that the “
✕” symbol indicates that the corresponding
common pin cannot be used in that drive type.
*In products with the CF
specifications, the
alternation frequency
signal stops briefly.
Static 1/2 duty 1/3 duty 1/4/duty
COM1
●● ●● ●● ●●
COM2 ✕ ●● ●● ●●
COM3 ✕ ✕ ●● ●●
COM4 ✕ ✕ ✕ ●●
Alternation
32 Hz 32 Hz 42.7 Hz 64 Hz
frequency
Page 8
No. 5944-8/24
LC5824, LC5823, LC5822
Sample Application Circuit
LCD : 1/2 bias — 1/4 duty
Page 9
No. 5944-9/24
LC5824, LC5823, LC5822
Oscillator Circuit Options
Option Circuit type Notes
• The cycle time is 4 times the f1 period.
• The divider circuit outputs (ø1 through ø15)
are used as the clock time base, the LCD
drive waveform generation clock, and for
S/K port chattering prevention.
• OSC1 is stopped by the execution of a
SLOW instruction.
RC & Xtal
• The cycle time is 4 times n times the f1
period. (n:1)
• The divider circuit outputs (ø1 through ø15)
are used as the clock time base, the LCD
drive waveform generation clock, and for
S/K port chattering prevention.
• OSC1 is stopped by the execution of a
SLOW instruction.
CF & Xtal
• 400 kHz (CF)
• 4 MHz (CF)
• The cycle time is 4 times the f1 period.
• The divider circuit outputs (ø1 through ø15)
are used as the clock time base, the LCD
drive waveform generation clock, and for
S/K port chattering prevention.
RC
Timing
generator
Divider
Timing
generator
Divider
Timing
generator
Divider
Continued on next page.
Page 10
No. 5944-10/24
LC5824, LC5823, LC5822
Option Circuit type Notes
• The cycle time is 4 times n times the f1
period. (n:1)
• The divider circuit outputs (ø1 through ø15)
are used as the clock time base, the LCD
drive frequency generation clock, and for
S/K port chattering prevention.
CF
• 400 kHz
• 4 MHz
• The cycle time is 4 times the f2 period.
• The divider circuit outputs (ø1 through ø15)
are used as the clock time base, the LCD
drive waveform generation clock, and for
S/K port chattering prevention.
Note that the CFIN and CFOUT pins are
switched over to function as the P1 and P2
pins.
Xtal
• 32 kHz
• 55 kHz
Continued from preceding page.
Timing
generator
Divider
Timing
generator
Divider
Page 11
No. 5944-11/24
LC5824, LC5823, LC5822
Crystal Oscillator Circuit Options
Option Circuit type Notes
The resistor RD is built into the IC when this
circuit is used at 32 kHz.
Used at 32 kHz
• The cycle time is 4 times n times the f1
period. (n:2)
• The divider circuit outputs (ø1 through ø15)
are used as the clock time base, the LCD
drive frequency generation clock, and for
S/K port chattering prevention.
• OSC1 is stopped by the execution of a
SLOW instruction.
Used at 38 kHz
Used at 65 kHz
Input Port Options
Option Circuit type Notes
When use of the hold transistor is selected, it
is used to minimize the current drain that
flows in the pull-down resistor when a pushbutton switch is used with S1 or a slide switch
is used with S2.
• When the input open specifications are
selected, before reading the input, the pulldown transistor is turned on. Then the input
state is read and the pull-down transistor is
turned off. If the input was in the floating
state, the low level hold transistor operates
to hold the level.
If use of the hold transistor is not selected:
• The circuit is used with the pull-down
transistor turned on.
• Select unused if the external control signal
line connected to this input will never be in
the floating state.
Low level hold
transistor
selection
RES Pin
Option Circuit type Notes
Internal resistor and polarity selections
• Reset on low, pull-up resistor included
• Reset on high, pull-down resistor included
• Reset on low, no resistors connected
• Reset on high, no resistors connected
Pull-up resistor,
pull-down
resistor,
resistors left
open, and level
selections
Bus
SF2/RF2, D2 to D7
Output mode
Pull-down resistor
Pull-down resistor
Pull-up resistor
Low level
hold transistor
Page 12
Mask Option List
Voltage specifications
• Ag specifications
• Li specifications
• EXT-V specifications
LCD driver
• Static
• 1/2 bias — 1/2 duty
• 1/2 bias — 1/3 duty
• 1/2 bias — 1/4 duty
• 1/3 bias — 1/3 duty
• 1/3 bias — 1/4 duty
• Unused
Segment port states during a reset
LCD driver pins
• All lit
• All off
CMOS p/n-channel pins
• High level
• Low level
Oscillator specifications
• CF only (ceramic oscillator element)
• RC only (using a resistor and a capacitor)
• Crystal only
• CF + crystal
• RC + crystal
CF
• 400 kHz
• 800 kHz
• 1 MHz
• 2 MHz
• 4 MHz
RC
• 400 kHz
• 800 kHz
• 1 MHz
Crystal
• 32 kHz
• 65 kHz
• 38 kHz
LCD alternation frequency
• SLOW
• TYP
• FAST
External reset circuit
• RES pin
• RES pin + S1 to S4 pressed at the same time
Internal reset circuit (power on reset)
• Selected
• Disabled
RES pin
• Reset on low, pull-up resistor included
• Reset on high, pull-down resistor included
• Reset on low, no resistors connected
• Reset on high, no resistors connected
Alarm output initial level
• Low level
• High level
Chronometer and strobe selection
• 00H
• 10H
• 00H & 10H
• Unused
Port S low level hold transistors
• Low level hold transistors present
• Low level hold transistors disabled
Port K low level hold transistors
• Low level hold transistors present
• Low level hold transistors disabled
Port M low level hold transistors
• Low level hold transistors present
• Low level hold transistors disabled
Port P low level hold transistors
• Low level hold transistors present
• Low level hold transistors disabled
Port SO low level hold transistors
• Low level hold transistors present
• Low level hold transistors disabled
Port A low level hold transistors
• Low level hold transistors present
• Low level hold transistors disabled
M1 to M4 outputs
• CMOS
• p-channel
• n-channel
P1 to P4 outputs
• CMOS
• p-channel
• n-channel
A1 to A4 outputs
• CMOS
• p-channel
• n-channel
No. 5944-12/24
LC5824, LC5823, LC5822
Page 13
These electrical characteristics are provisional and the values are subject to change.
Ag Specifications
No. 5944-13/24
LC5824, LC5823, LC5822
Parameter Symbol Conditions and applicable pins
Ratings
Unit
min typ max
V
DD
–0.3 +4.0 V
V
DD
1 –0.3 +4.0 V
Maximum supply voltage V
DD
2 –0.3 +5.5 V
V
DD
3 For 1/3-bias LCD drive techniques –0.3 +4.0 V
V
DD
3 For LCD drive techniques other than 1/3 bias –0.3 +4.0 V
S1 to S4, K1 to K4, M1 to M4, A1 to A4, SO1 to SO4,
Maximum input voltage V
IN
1
RES,TST
–0.3 VDD+ 0.3 V
M1 to M4, A1 to A4, SO1 to SO4, ALM, CUP2
V
OUT
1
(With M1 to M4, A1 to A4, and SO1 to SO4 in input mode)
–0.3 +0.3 V
Maximum output voltage
V
OUT
2 SEGOUT, COM1 to COM4, CUP1 –0.3 VDD3 + 0.3 V
Operating temperature Topg –20 +65 °C
Storage temperature Tstg –30 +125 °C
Absolute Maximum Ratings at Ta = 25°C ±2°C, VSS= 0 V
Parameter Symbol Conditions and applicable pins
Ratings
Unit
min typ max
V
DD
VBAK = VDD1 1.3 1.65 V
V
DD
1
Supply voltage V
DD
2 2.4 3.3 V
V
DD
3 For 1/3-bias LCD drive techniques 3.7 4.95 V
V
DD
3 For LCD drive techniques other than 1/3 bias 2.4 3.3
S1 to S4, K1 to K4, M1 to M4, A1 to A4, SO1 to SO4,
High-level input voltage V
IH
(With M1 to M4, A1 to A4, and SO1 to SO4 in input mode) VDD– 0.2 V
DD
V
RES
S1 to S4, K1 to K4, M1 to M4, A1 to A4, SO1 to SO4,
Low-level input voltage V
IL
(With M1 to M4, A1 to A4, and SO1 to SO4 in input mode) 0 0.2 V
RES
Operating frequency fopg Ta = –20 to +65°C 32 33 kHz
Allowable Operating Ranges at Ta = 25°C ±2°C, VSS= 0 V
Parameter Symbol Conditions and applicable pins
Ratings
Unit
min typ max
R
IN
1A
V
DD
= 1.5 V, Low level hold transistor
50 500 kΩ
V
IN
= 0.35 VDD*1 Figure 1
R
IN
1B
V
DD
= 1.5 V, Programmable pull-down resistor
50 1000 kΩ
V
IN
= 0.7 VDD*1 Figure 1
Input resistance R
IN
2A
V
DD
= 1.5 V, Low level hold transistor
50 500 kΩ
V
IN
= 0.35 VDD, Input mode *2, Figure 1
R
IN
2B
V
DD
= 1.5 V, Programmable pull-down resistor
50 1000 kΩ
V
IN
= 0.7 VDD, Input mode *2, Figure 1
R
IN
3
V
DD
= 1.5 V, The RES pin pull-up/pull-down resistor
10 300 kΩ
V
IN
= 0.7 VDD/0.3 V
DD
High-level output voltage VOH1 VDD= 1.3 V, IOH= –250 µA, ALM
VDD– 0.65
V
Low-level output voltage V
OL
1 VDD= 1.3 V, IOL= 250 µA, ALM 0.65 V
V
DD
= 1.5 V, M1 to 4, A1 to 4, SO1 to 4
High-level output voltage V
OH
2 IOH= –20 µA,
VDD– 0.2
V
(With M1 to M4, A1 to A4, and SO1 to SO4 in output mode)
VDD= 1.5 V, M1 to 4, A1 to 4, SO1 to 4
Low-level output voltage V
OL
2 IOL= 20 µA, 0.2 V
(With M1 to M4, A1 to A4, and SO1 to SO4 in output mode)
Electrical Characteristics at Ta = 25°C ±2°C, VSS= 0 V, VDD= VDD1
Continued on next page.
Page 14
No. 5944-14/24
LC5824, LC5823, LC5822
Continued from preceding page.
Parameter Symbol Conditions and applicable pins
Ratings
Unit
min typ max
Segment driver output impedance
[When Set Up as CMOS Output Ports]
High-level output voltage V
OH
3 VDD= 1.5 V, IOH= –3 µA, Segment 1 to 42 VDD– 1.0 V
Low-level output voltage V
OL
3 VDD= 1.5 V, IOL= 3 µA, Segment 1 to 42 1.0 V
[When Set Up as P-Channel Open-Drain Output Ports]
High-level output voltage V
OH
3 VDD= 1.5 V, IOH= –3 µA, Segment 1 to 42 0.3 1.0 V
Output off leakage current I
OFFVDD
= 1.5 V, VOL= VSS, Segment 1 to 42 1.0 µA
[Static Drive]
High-level output voltage V
OH
3 VDD= 1.5 V, IOH= –0.4 µA, SEGOUT VDD2 – 0.2 V
Low-level output voltage V
OL
3 VDD= 1.5 V, IOL= 0.4 µA, SEGOUT 0.2 V
High-level output voltage V
OH
4 VDD= 1.5 V, IOH= –4 µA, COM1 VDD2 – 0.2 V
Low-level output voltage V
OL
4 VDD= 1.5 V, IOL= 4 µA, COM1 0.2 V
[Duplex Drive (1/2 bias - 1/2 duty)]
High-level output voltage V
OH
3 VDD= 1.5 V, IOH= –0.4 µA, SEGOUT VDD2 – 0.2 V
Low-level output voltage V
OL
3 VDD= 1.5 V, IOL= 0.4 µA, SEGOUT 0.2 V
High-level output voltage V
OH
4 VDD= 1.5 V, IOH= –4 µA, COM1 to COM2 VDD2 – 0.2 V
Middle-level output voltage V
OMVDD
= 1.5 V, IOH= –4 µA, IOL= 4 µA, COM1 to COM2 VDD1 – 0.2 VDD1 + 0.2 V
Low-level output voltage V
OL
4 VDD= 1.5 V, IOL= 4 µA, COM1 to COM2 0.2 V
[1/2 Bias - 1/3 Duty and 1/2 Bias - 1/4 Duty Drive]
High-level output voltage V
OH
3 VDD= 1.5 V, IOH= –0.4 µA, SEGOUT VDD2 – 0.2 V
Low-level output voltage V
OL
3 VDD= 1.5 V, IOL= 0.4 µA, SEGOUT 0.2 V
High-level output voltage
V
OH
4 VDD= 1.5 V, IOH= –4 µA, COM1 to COM3 (1/3 duty)
V
DD
2 – 0.2 V
COM1 to COM4 (1/4 duty)
Middle-level output voltage V
OM
VDD= 1.5 V, IOH= –4 µA, IOL= 4 µA,
V
DD
1 – 0.2 VDD1 + 0.2 V
COM1 to COM3 (1/3 duty), COM1 to COM4 (1/4 duty)
Low-level output voltage VOL4
V
DD
= 1.5 V, IOL= 4 µA, COM1 to 2
0.2 V
COM1 to COM3 (1/3 duty), COM1 to COM4 (1/4 duty)
[1/3 Bias - 1/3 Duty and 1/3 Bias - 1/4 Duty Drive]
High-level output voltage V
OH
3 VDD= 1.5 V, IOH= –0.4 µA, SEGOUT VDD3 – 0.2 V
M1-level output voltage V
OM
1–3 VDD= 1.5 V, IOH= –0.4 µA, IOL= 0.4 µA, SEGOUT VDD2 – 0.2 VDD2 + 0.2 V
M2-level output voltage V
OM
2–3 VDD= 1.5 V, IOH= –0.4 µA, IOL= 0.4 µA, SEGOUT VDD1 – 0.2 VDD1 + 0.2 V
Low-level output voltage V
OL
3 VDD= 1.5 V, IOL= 0.4 µA, SEGOUT 0.2 V
High-level output voltage V
OH
4
V
DD
= 1.5 V, IOH= –4 µA, COM1 to COM3 (1/3 duty)
V
DD
3 – 0.2 V
COM1 to COM4 (1/4 duty)
M1-level output voltage VOM1–4
V
DD
= 1.5 V, IOH= –4 µA, IOL= 4 µA,
V
DD
2 – 0.2 VDD2 + 0.2 V
COM1 to COM3 (1/3 duty), COM1 to COM4 (1/4 duty)
M2-level output voltage VOM2–4
V
DD
= 1.5 V, IOH= –4 µA, IOL= 4 µA,
V
DD
1 – 0.2 VDD1 + 0.2 V
COM1 to COM3 (1/3 duty), COM1 to COM4 (1/4 duty)
Low-level output voltage VOL4
V
DD
= 1.5 V, IOL= 4 µA, COM1 to COM3 (1/3 duty),
0.2 V
COM1 to COM4 (1/4 duty)
Continued on next page.
Page 15
No. 5944-15/24
LC5824, LC5823, LC5822
Continued from preceding page.
Parameter Symbol Conditions and applicable pins
Ratings
Unit
min typ max
[Output Voltage]
LCD drive method: 1/3 bias
(doubler) V
DD
2
V
DD
= 1.35 V, fopg = 32.768 kHz, C1 to C3 = 0.1 µF
2.5 V
Figure 2
(tripler) V
DD
3
V
DD
= 1.35 V, fopg = 32.768 kHz, C1 to C3 = 0.1 µF
3.75 V
Figure 2
LCD drive method: 1/2 bias
(doubler) V
DD
2
V
DD
= 1.35 V, fopg = 32.768 kHz, C1 to C2 = 0.1 µF
2.5 V
Figure 3
[Current Drain (with the backup flag cleared)]
LCD drive method: 1/3 bias | I
DD
|
V
DD
= 1.5 V, In halt mode, C1 to C3 = 0.1 µF, CI = 25 kΩ,
3.5 µA
Figure 2, Co = Cg = 20 pF, 32.768 kHz Xtal
LCD drive methods other than
| I
DD
|
V
DD
= 1.5 V, In halt mode, C1 = C2 = 0.1 µF, CI = 25 kΩ,
2.0 µA
1/3 bias Figure 3, Co = Cg = 20 pF, 32.768 kHz Xtal
Oscillator start voltage | Vstt |
Co = Cg = 20 pF, CI = 25 kΩ, Figure 3,
1.35 V
32.768 kHz Xtal
Oscillator hold voltage | V
HOLD
|
V
BAK
= VDD1, CI = 25 kΩ, Figures 2 and 3
1.3 1.65 V
Co = Cg = 20 pF, 32.768 kHz Xtal
Oscillator start time Tstt
VDD= 1.35 V, CI = 25 kΩ, Figure 4,
10 sec
Co = Cg = 20 pF, 32.768 kHz Xtal
Oscillator correction capacitance
10P XC 8 10 12 pF
20P XTOUT 16 20 24 pF
Page 16
No. 5944-16/24
LC5824, LC5823, LC5822
Li Specifications
Absolute Maximum Ratings at Ta = 25°C ±2°C, VSS= 0 V
Parameter Symbol Conditions and applicable pins
Ratings
Unit
min typ max
V
DD
–0.3 +4.0 V
V
DD
1 V
BAK
= VDD1 or VDD2 –0.3 +4.0 V
Maximum supply voltage V
DD
2 –0.3 +4.0 V
V
DD
3 (LCD drive method: 1/3 bias) –0.3 +5.5 V
V
DD
3 (LCD drive methods other than 1/3 bias) –0.3 +4.0 V
Maximum input voltage
S1 to S4, K1 to K4, M1 to M4, A1 to A4, SO1 to SO4,
V
IN
1 (With M1 to M4, A1 to A4, and SO1 to SO4 in input mode) –0.3 VDD+ 0.3 V
RES, TST
Maximum output voltage
V
OUT
1
M1 to M4, A1 to A4, SO1 to SO4,
(LCD drive method: 1/3 b
ias)
(With M1 to M4, A1 to A4, and SO1 to SO4 in output mode)
–0.3 VDD+ 0.3 V
ALM, CUP2
V
OUT
2 SEGOUT, COM1 to COM4, CUP1 –0.3 VDD3 + 0.3 V
(LCD drive methods other than M1 to M4, A1 to A4, SO1 to SO4,
1/3 bias) V
OUT
2
(With M1 to M4, A1 to A4, and SO1 to SO4 in output mode)
–0.3 VDD+ 0.3 V
ALM, SEGOUT, COM1 to COM4, CUP1, CUP2
Operating temperature Topg –20 +65 °C
Storage temperature Tstg –30 +125 °C
Parameter Symbol Conditions and applicable pins
Ratings
Unit
min typ max
V
DDVBAK
= VDD/2
2.0 3.6 V
V
DD
2 (With the backup flag cleared)
Supply voltage V
DDVBAK
= V
DD
1.3 3.6 V
V
DD
2 (With the backup flag uncleared)
V
DD
3 (LCD drive method: 1/3-bias) 3.9 5.0 V
V
DD
3 (LCD drive methods other than 1/3 bias)
VDD3 = VDD2
V
S1 to S4, K1 to K4, M1 to M4, A1 to A4, SO1 to SO4,
High-level input voltage V
IH
(With M1 to M4, A1 to A4, and SO1 to SO4 in input mode) VDD– 0.4 V
DD
V
RES
S1 to S4, K1 to K4, M1 to M4, A1 to A4, SO1 to SO4,
Low-level input voltage V
IL
(With M1 to M4, A1 to A4, and SO1 to SO4 in input mode) 0 0.4 V
RES
Operating frequency fopg Ta = –20 to +65°C 32 33 kHz
Allowable Operating Ranges at Ta = 25°C ±2°C, VSS= 0 V
Parameter Symbol Conditions and applicable pins
Ratings
Unit
min typ max
R
IN
1A
V
DD
= 3.0 V, VIN= 0.35 V
DD
50 500 kΩ
Low level hold transistor *1, Figure 5
RIN1B
V
DD
= 3.0 V, VIN= 0.7V
DD
50 1000 kΩ
Programmable pull-down resistor *1, Figure 5
Input resistance RIN2A
V
DD
= 3.0 V, input mode, Low level hold transistor *1, 50 500 kΩ
V
IN
= 0.35 VDD, Figure 5
R
IN
2B
V
DD
= 3.0 V, Programmable pull-down resistor, *2, 50 1000 kΩ
V
IN
= 0.7 VDD, input mode, Figure 5
R
IN
3
V
DD
= 3.0 V, RES pin pull-up/pull-down resistor
10 300 kΩ
V
IN
= 0.7 VDD/0.3 V
DD
Electrical Characteristics at Ta = 25°C ±2°C, VSS= 0 V, VDD= VDD2
Page 17
No. 5944-17/24
LC5824, LC5823, LC5822
Parameter Symbol Conditions and applicable pins
Ratings
Unit
min typ max
High-level output voltage V
OH
1 VDD= 2.5 V, IOH= –250 µA, ALM VDD– 0.65 V
Low-level output voltage V
OL
1 VDD= 2.5 V, IOL= 250 µA, ALM 0.65 V
High-level output voltage V
OH
2
V
DD
= 3.0 V, IOH= –40 µA, M1 to M4, A1 to A4, SO1 to SO4,
V
DD
– 0.4 V
(With M1 to M4, A1 to A4, and SO1 to SO4 in output mode)
Low-level output voltage VOL2
V
DD
= 3.0 V, IOL= 40 µA, M1 to M4, A1 to A4, SO1 to SO4,
0.4 V
(With M1 to M4, A1 to A4, and SO1 to SO4 in output mode)
Segment driver output impedance
[When Set Up as CMOS Output Ports]
High-level output voltage V
OH
3 VDD= 3.0 V, IOH= –5 µA, Segment 1 to 42 VDD– 1 V
Low-level output voltage V
OL
3 VDD= 3.0 V, IOL= 5 µA, Segment 1 to 42 1 V
[When Set Up as P-Channel Open-Drain Output Ports]
High-level output voltage V
OH
3 VDD= 2.5 V, IOH= –10 µA, Segment 1 to 42 0.3 1 V
Output off leakage current I
OFFVDD
= 3.0 V, VOL= V
SS
1 µA
[Static Drive]
High-level output voltage V
OH
3 VDD= 3.0 V, IOH= –0.4 µA, SEGOUT VDD– 0.2 V
Low-level output voltage V
OL
3 VDD= 3.0 V, IOL= 0.4 µA, SEGOUT 0.2 V
High-level output voltage V
OH
4 VDD= 3.0 V, IOH= –4 µA, COM1 VDD– 0.2 V
Low-level output voltage V
OL
4 VDD= 3.0 V, IOL= 4 µA, COM1 0.2 V
[Duplex Drive (1/2 bias - 1/2 duty)]
High-level output voltage V
OH
3 VDD= 3.0 V, IOH= –0.4 µA, SEGOUT VDD– 0.2 V
Low-level output voltage V
OL
3 VDD= 3.0 V, IOL= 0.4 µA, SEGOUT 0.2 V
High-level output voltage V
OH
4 VDD= 3.0 V, IOH= –4 µA, COM1 to COM2 VDD– 0.2 V
Middle-level output voltage V
OMVDD
= 3.0 V, IOH= –4 µA, IOL= 4 µA, COM1 to COM2 VDD1 – 0.2 VDD1 + 0.2 V
Low-level output voltage V
OL
4 VDD= 3.0 V, IOL= 4 µA, COM1 to COM2 0.2 V
[1/2 Bias - 1/3 Duty and 1/2 Bias - 1/4 Duty Drive]
High-level output voltage V
OH
3 VDD= 3.0 V, IOH= –0.4 µA, SEGOUT VDD– 0.2 V
Low-level output voltage V
OL
3 VDD= 3.0 V, IOL= 0.4 µA, SEGOUT 0.2 V
High-level output voltage V
OH
4
V
DD
= 3.0 V, IOH= –4 µA, COM1 to COM3 (1/3 duty)
V
DD
– 0.2 V
COM1 to COM4 (1/4 duty)
V
DD
= 3.0 V, IOH= –4 µA, IOL= 4 µA,
Middle-level output voltage V
OM
COM1 to COM3 (1/3 duty) VDD1 – 0.2 VDD1 + 0.2 V
COM1 to COM4 (1/4 duty)
Low-level output voltage V
OL
4
V
DD
= 3.0 V, IOL= 4 µA, COM1 to COM3 (1/3 duty)
0.2 V
COM1 to COM4 (1/4 duty)
Electrical Characteristics at Ta = 25°C ±2°C, VSS= 0 V, VDD= VDD2
Continued on next page.
Page 18
No. 5944-18/24
LC5824, LC5823, LC5822
Continued from preceding page.
Parameter Symbol Conditions and applicable pins
Ratings
Unit
min typ max
[1/3 Bias - 1/3 Duty and 1/3 Bias - 1/4 Duty Drive]
High-level output voltage V
OH
3 VDD= 3.0 V, IOH= –0.4 µA, SEGOUT VDD3 – 0.2 V
M1-level output voltage V
OM
1–3 VDD= 3.0 V, IOH= –0.4 µA, IOL= 0.4 µA, SEGOUT VDD2 – 0.2 VDD2 + 0.2 V
M2-level output voltage V
OM
2–3 VDD= 3.0 V, IOH= –0.4 µA, IOL= 0.4 µA, SEGOUT VDD1 – 0.2 VDD1 + 0.2 V
Low-level output voltage V
OL
3 VDD= 3.0 V, IOL= 0.4 µA, SEGOUT 0.2 V
V
DD
= 3.0 V, IOH= –4 µA,
High-level output voltage V
OH
4 COM1 to COM3 (in 1/3 duty mode) VDD3 – 0.2 V
COM1 to COM4 (in 1/4 duty mode)
VDD= 3.0 V, IOH= –4 µA, IOL= 4 µA,
M1-level output voltage V
OH
1–4 COM1 to COM3 (in 1/3 duty mode) VDD2 – 0.2 VDD2 + 0.2 V
COM1 to COM4 (in 1/4 duty mode)
V
DD
= 3.0 V, IOH= –4 µA, IOL= 4 µA,
M2-level output voltage V
OM
2–4 COM1 to COM3 (in 1/3 duty mode) VDD1 – 0.2 VDD1 + 0.2 V
COM1 to COM4 (in 1/4 duty mode)
VDD= 3.0 V, IOL= 4 µA,
Low-level output voltage V
OL
4 COM1 to COM3 (in 1/3 duty mode) 0.2 V
COM1 to COM4 (in 1/4 duty mode)
[Output Voltage]
LCD drive method: 1/3 bias
(halver) V
DD
1
V
DD
= 3.0 V, fopg = 32.768 kHz,
1.35 V
C1 to C4 = 0.1 µF, Figure 6
(tripler) V
DD
3
V
DD
= 3.0 V, fopg = 32.768 kHz,
4.1 V
C1 to C4 = 0.1 µF, Figure 6
LCD drive method: 1/2 bias
(halver) V
DD
1
V
DD
= 3.0 V, fopg = 32.768 kHz,
1.35 V
C1 = C2 = 0.1 µF, Figure 7
[Current Drain (With the backup flag cleared)]
V
DD
= 3.0 V, Halt mode
LCD drive method: 1/3 bias | I
DD
| C1 to C4 = 0.1 µF, C1 = 25 kΩ, Figure 6 2.0 µA
Co = Cg = 20 pF, 32.768 kHz Xtal
LCD drive methods other than
V
DD
= 3.0 V, Halt mode
1/3 bias
| I
DD
| C1 = C2 = 0.1 µF, CI = 25 kΩ, Figure 7 1.0 µA
Co = Cg = 20 pF, 32.768 kHz Xtal
Oscillator start capacitor | Vstt |
V
DD
1 = VDD, CI = 25 kΩ, Figure 4
1.35 V
Co = Cg = 20 pF, 32.768 kHz Xtal
Oscillator hold voltage
V
HOLD
V
BAK
= VDD1 = VDD/2, CI = 25 kΩ, Figures 6 and 7
2.6 V
(with the backup flag cleared) Co = Cg = 20 pF, 32.768 kHz Xtal
Oscillator start time Tstt
VDD1 = VDD= 1.35 V, CI = 25 kΩ, Figure 4
10 sec
Co = Cg = 20 pF, 32.768 kHz Xtal
Oscillator correction capacitance
10P XC 8 10 12 pF
20P XTOUT 16 20 24 pF
Page 19
No. 5944-19/24
LC5824, LC5823, LC5822
EXT-V Specifications
Absolute Maximum Ratings at Ta = 25°C ±2°C, VSS= 0 V
Parameter Symbol Conditions and applicable pins
Ratings
Unit
min typ max
V
DD
–0.3 +4.0 V
V
DD
1 –0.3 +4.0 V
Maximum supply voltage V
DD
2 –0.3 +4.0 V
V
DD
3 (LCD drive method: 1/3 bias) –0.3 +5.5 V
V
DD
3 (LCD drive methods other than 1/3 bias) –0.3 +4.0 V
Maximum input voltage
S1 to S4, K1 to K4, M1 to M4, A1 to A4, SO1 to SO4,
V
IN
2 (With M1 to M4, A1 to A4, and SO1 to SO4 in input mode) –0.3 VDD+ 0.3 V
RES, TST
Maximum output voltage
M1 to M4, A1 to A4, SO1 to SO4,
(LCD drive method: 1/3 bias)
V
OUT
2
(With M1 to M4, A1 to A4, and SO1 to SO4 in output mode)
–0.3 VDD+ 0.3 V
ALM, CUP2
V
OUT
3 SEGOUT, COM1 to COM4, CUP1 –0.3 VDD3 + 0.3 V
(LCD drive methods other than
M1 to M4, A1 to A4, SO1 to SO4,
1/3 bias)
V
OUT
2
(With M1 to M4, A1 to A4, and SO1 to SO4 in output mode)
–0.3 VDD+ 0.3 V
ALM, SEGOUT, COM1 to COM4, CUP1
Operating temperature Topg –20 +65 °C
Storage temperature Tstg –30 +125 °C
Parameter Symbol Conditions and applicable pins
Ratings
Unit
min typ max
V
DD
1 1.3 3.6 V
V
DD
2.0 3.6 V
Supply voltage V
DD
2
V
DD
3 (LCD drive method: 1/3-bias) 3.9 5.0 V
V
DD
3 (LCD drive methods other than 1/3 bias)
VDD3 = VDD2
V
S1 to S4, K1 to K4, M1 to M4, A1 to A4, SO1 to SO4,
High-level input voltage V
IH
(With M1 to M4, A1 to A4, and SO1 to SO4 in input mode) VDD– 0.4 V
DD
V
RES
S1 to S4, K1 to K4, M1 to M4, A1 to A4, SO1 to SO4,
Low-level input voltage V
IL
(With M1 to M4, A1 to A4, and SO1 to SO4 in input mode) 0 0.4 V
RES
Operating frequency fopg Ta = –20 + 65°C 32 33 kHz
Allowable Operating Ranges at Ta = 25°C ±2°C, VSS= 0 V
Parameter Symbol Conditions and applicable pins
Ratings
Unit
min typ max
R
IN
1A
V
DD
= 3.0 V, VIN= 0.35 VDD, Low level hold transistor *1,
50 500 kΩ
Figure 5
R
IN
1B
V
DD
= 3.0 V, VIN= 0.7 VDD, Programmable pull-down
50 1000 kΩ
resistor *1, Figure 5
Input resistance
R
IN
2A
V
DD
= 3.0 V, VIN= 0.35 VDD, Input mode, Low level hold
50 500 kΩ
transistor *1, Figure 5
R
IN
2B
V
DD
= 3.0 V, VIN= 0.7 VDD, input mode,
50 1000 kΩ
Programmable pull-down resistor *2, Figure 5
R
IN
3
V
DD
= 3.0 V, VIN= 0.7 VDD/0.3 V
DD
10 300 kΩ
RES pin pull-up/pull-down resistor
Electrical Characteristics at Ta = 25°C ±2°C, VSS= 0 V, VDD= VDD2
Continued on next page.
Page 20
No. 5944-20/24
LC5824, LC5823, LC5822
Continued from preceding page.
Parameter Symbol Conditions and applicable pins
Ratings
Unit
min typ max
High-level output voltage V
OH
1 VDD= 2.5 V, IOH= –250 µA, ALM VDD– 0.65 V
Low-level output voltage V
OL
1 VDD= 2.5 V, IOL= 250 µA, ALM 0.65 V
High-level output voltage V
OH
2
V
DD
= 3.0 V, IOH= –40 µA, M1 to M4, A1 to A4, SO1 to SO4
V
DD
– 0.4 V
(With M1 to M4, A1 to A4, and SO1 to SO4 in output mode)
Low-level output voltage
V
OL
2
V
DD
= 3.0 V, IOL= 40 µA, M1 to M4, A1 to A4, SO1 to SO4
0.4 V
(With M1 to M4, A1 to A4, and SO1 to SO4 in output mode)
Segment driver output impedance
[When Set Up as CMOS Output Ports]
High-level output voltage V
OH
3 VDD= 2.4 V, IOH= –10 µA, Segment 1 to 42 VDD– 1 V
Low-level output voltage V
OL
3 VDD= 2.4 V, IOL= 40 µA 1 V
High-level output voltage V
OH
4 VDD= 2.4 V, IOH= –5 µA, Segment 1 to 42 VDD– 1 V
Low-level output voltage V
OL
4 VDD= 2.4 V, IOL= 20 µA 1 V
[When Set Up as P-Channel Open-Drain Output Ports]
High-level output voltage V
OH
3 VDD= 2.4 V, IOH= –10 µA, Segment 1 to 42 VDD– 0.2 0.3 1 V
Output off leakage current I
OFFVDD
= 2.6 V, VOL= V
SS
1 µA
[Static Drive]
High-level output voltage V
OH
5 VDD= 3.0 V, IOH= –0.4 µA, SEGOUT VDD– 0.2 V
Low-level output voltage V
OL
5 VDD= 3.0 V, IOL= 0.4 µA, SEGOUT 0.2 V
High-level output voltage V
OH
6 VDD= 3.0 V, IOH= –4 µA, COM1 VDD– 0.2 V
Low-level output voltage V
OL
6 VDD= 3.0 V, IOL= 4 µA, COM1 0.2 V
[Duplex Drive (1/2 bias - 1/2 duty)]
High-level output voltage V
OH
5 VDD= 3.0 V, IOH= –0.4 µA, SEGOUT VDD2 – 0.2 V
Low-level output voltage V
OL
5 VDD= 3.0 V, IOL= 0.4 µA, SEGOUT 0.2 V
High-level output voltage V
OH
6 VDD= 3.0 V, IOH= –4 µA, COM1 to COM2 VDD1 – 0.2 V
Middle-level output voltage V
OMVDD
= 3.0 V IOH= –4 µA, IOL= 4 µA, COM1 to COM2 VDD1 + 0.2 V
Low-level output voltage V
OL
6 VDD= 3.0 V, IOL= 4 µA, COM1 to COM2 0.2 V
[1/2 Bias - 1/3 Duty and 1/2 Bias - 1/4 Duty Drive]
High-level output voltage V
OH
5 VDD= 3.0 V, IOH= –0.4 µA, SEGOUT VDD– 0.2 V
Low-level output voltage V
OL
5 VDD= 3.0 V, IOL= 0.4 µA, SEGOUT 0.2 V
V
DD
= 3.0 V, IOH= –4 µA,
High-level output voltage V
OH
6 COM1 to COM3 (1/3 duty) VDD2 – 0.2 V
COM1 to COM4 (1/4 duty)
V
DD
= 3.0 V IOH= –4 µA, IOL= 4 µA,
Middle-level output voltage V
OM
COM1 to COM3 (1/3 duty) VDD1 – 0.2 VDD1 + 0.2 V
COM1 to COM4 (1/4 duty)
VDD= 3.0 V, IOL= 4 µA,
Low-level output voltage V
OL
6 COM1 to COM3 (1/3 duty) 0.2 V
COM1 to COM4 (1/4 duty)
Continued on next page.
Page 21
No. 5944-21/24
LC5824, LC5823, LC5822
Continued from preceding page.
Parameter Symbol Conditions and applicable pins
Ratings
Unit
min typ max
[1/3 Bias - 1/3 Duty and 1/3 Bias - 1/4 Duty Drive]
High-level output voltage V
OH
5 VDD= 3.0 V, IOH= –0.4 µA, SEGOUT VDD3 + 0.2 V
Middle-level output voltage
V
OM
1–5 VDD= 3.0 V, IOH= –0.4 µA, IOL= 0.4 µA, SEGOUT VDD2 – 0.2 VDD2 + 0.2 V
V
OM
2–5 VDD= 3.0 V, IOH= –0.4 µA, IOL= 0.4 µA, SEGOUT VDD1 – 0.2 VDD1 + 0.2 V
Low-level output voltage V
OL
5 VDD= 3.0 V, IOL= 0.4 µA, SEGOUT 0.2 V
V
DD
= 3.0 V, IOH= –0.4 µA,
High-level output voltage V
OH
6 COM1 to COM3 (in 1/3 duty mode) VDD3 + 0.2 V
COM1 to COM4 (in 1/4 duty mode)
VDD= 3.0 V, IOH= –0.4 µA, IOL= 0.4 µA,
V
OM
1–6 COM1 to COM3 (in 1/3 duty mode) VDD2 – 0.2 VDD2 + 0.2 V
COM1 to COM4 (in 1/4 duty mode)
Middle-level output voltage
V
DD
= 3.0 V, IOH= –0.4 µA, IOL= 0.4 µA,
V
OM
2–6 COM1 to COM3 (in 1/3 duty mode) VDD1 – 0.2 VDD1 + 0.2 V
COM1 to COM4 (in 1/4 duty mode)
Low-level output voltage VOL6 VDD= 3.0 V, IOL= 0.4 µA 0.2 V
[Output Voltage]
LCD drive method: 1/3 bias
(halver) V
DD
1
V
DD
= 3.0 V, fopg = 32.768 kHz,
1.35 V
C1 to C4 = 0.1 µF, Figure 6
(tripler) V
DD
3
V
DD
= 3.0 V, fopg = 32.768 kHz,
4.1 V
C1 to C4 = 0.1 µF, Figure 6
LCD drive method: 1/2 bias
(halver) V
DD
1 VDD= 3.0 V, fopg 32.768 kHz, C1 = C2 = 0.1 µF, Figure 7 1.35 V
[Current Drain (With the backup flag cleared)]
LCD drive method: 1/3 bias | I
DD
|
V
DD
= 3.0 V, Halt mode, C1 to C4 = 0.1 µF, CI = 25 kΩ
5.0 µA
Co = Cg = 20 pF, 32.768 kHz Xtal, Figure 6
LCD drive methods other than
| I
DD
|
V
DD
= 3.0 V, Halt mode, C1 to C2 = 0.1 µF, CI = 25 kΩ,
5.0 µA
1/3 bias Figure 7, Co = Cg = 20 pF, 32.768 kHz, Xtal
Oscillator start voltage Vstt
V
DD
= VDD2, CI = 25 kΩ, Figure 4, 2.2 V
Co = Cg = 20 pF, 32.768 kHz Xtal
Oscillator hold voltage
V
HOLD
VDD= VDD2, CI = 25 kΩ, , Figures 5, 6, 7, and 8, 2.0 V
(with the backup flag cleared) Co = Cg = 20 pF, 32.768 kHz Xtal
Oscillator start time Tstt
V
DD
= VDD2 = 2.2 V, CI = 25 kΩ, Figure 4
10 sec
Co = Cg = 20 pF, 32.768 kHz Xtal
Oscillator correction capacitance
10P XC 8 10 12 pF
20P XTOUT 16 20 24 pF
Note : 1. S1 to 4, K1 to 4
2. M1 to 4, A1 to 4, SO1 to 4
Page 22
Figure 1 S1 to S4, K1 to K4, M1 to M4, A1 to A4, and SO1 to SO4
Can be applied by
application software
No. 5944-22/24
LC5824, LC5823, LC5822
Figure 2 Output Voltage, Current Drain, and Oscillator Hold Voltage Test Circuit
Figure 3 Output Voltage, Current Drain, and Oscillator Hold Voltage Test Circuit
Page 23
No. 5944-23/24
LC5824, LC5823, LC5822
Figure 4 Oscillator Start Voltage, Oscillator Start Time, and Frequency Stability Test Circuit
Figure 5 S1 to S4, K1 to K4, M1 to M4, A1 to A4, and SO1 to SO4
Can be applied by
application software
Figure 6 Output Voltage, Current Drain, and Oscillator Hold Voltage Test Circuit
Page 24
This catalog provides information as of August, 1998. Specifications and information herein are subject to
change without notice.
Specifications of any and all SANYO products described or contained herein stipulate the performance,
characteristics, and functions of the described products in the independent state, and are not guarantees
of the performance, characteristics, and functions of the described products as mounted in the customer’s
products or equipment. To verify symptoms and states that cannot be evaluated in an independent device,
the customer should always evaluate and test devices mounted in the customer’s products or equipment.
SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all
semiconductor products fail with some probability. It is possible that these probabilistic failures could
give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire,
or that could cause damage to other property. When designing equipment, adopt safety measures so
that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective
circuits and error prevention circuits for safe design, redundant design, and structural design.
In the event that any and all SANYO products described or contained herein fall under strategic
products (including services) controlled under the Foreign Exchange and Foreign Trade Control Law of
Japan, such products must not be exported without obtaining export license from the Ministry of
International Trade and Industry in accordance with the above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system,
or otherwise, without the prior written permission of SANYO Electric Co., Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification”
for the SANYO product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not
guaranteed for volume production. SANYO believes information herein is accurate and reliable, but
no guarantees are made or implied regarding its use or any infringements of intellectual property rights
or other rights of third parties.
PS No. 5944-24/24
LC5824, LC5823, LC5822
Figure 7 Output Voltage, Current Drain, and Oscillator Hold Voltage Test Circuit
Figure 8 Output Voltage, Current Drain, and Oscillator Hold Voltage Test Circuit
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