Datasheet LB11824M Datasheet (SANYO)

Page 1

Ordering number : ENN7107

80102RM (OT) No. 7107-1/17

Overview

The LB11824M is a direct PWM drive predriver IC for use with three-phase power brushless motors. The LB11824M can implement a motor drive circuit with the desired output capacity (voltage and current) by using appropriate external transistors. This device is optimal for motor drive in larger home appliances such as air conditioners and on-demand hot water heaters.

Functions and Features

• Three-phase bipolar drive

• Direct PWM drive

• Built-in forward/reverse switching circuit

• Full complement of built-in protection circuits, including current limiter, undervoltage protection circuit, motor lockup protection circuit, and thermal protection circuit.

• Can be controlled by either a command voltage or the duty of an input PWM signal.

• Provides three types of Hall-effect element signal pulse outputs.

Package Dimensions

unit: mm

3073C-MFP30SD

30 16

1.0

15.2

0.4

0.65

10.5

7.9

0.25

(0.6)

2.45max

0.1

(2.25)

SANYO: MFP30SD

[LB11824M]

LB11824M

SANYO Electric Co.,Ltd. Semiconductor Company

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN

Direct PWM Drive Brushless Motor Predriver for On-Demand Water Heater

and Air Conditioner Motors

Monolithic Digital IC

Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft’s control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications.

SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein.

Parameter Symbol Conditions Ratings Unit

Supply voltage 1 V

1 max VCC1 pin 14.5 V

Supply voltage 2 V

2 max VCC2 pin 14.5 V

Supply voltage 3 V

3 max VCC3 pin 20 V

Output current I

max Pins UL, VL, WL, UH, VH, WH 40 mA RF pin applied voltage VRF max 4V LVS pin applied voltage VLVS max 20 V TOC pin applied voltage VTOC max V

VCTL pin applied voltage VCTL max 14.5 V

Specifications

Absolute Maximum Ratings at Ta = 25°C

Continued on next page.

Page 2

No. 7107-2/17

LB11824M

Continued from preceding page.

Parameter Symbol Conditions Ratings Unit Allowable power dissipation Pd max Independent IC 0.9 W Operating temperature Topr –20 to +100 °C Storage temperature Tstg –55 to +150 °C

Parameter Symbol Conditions

Ratings

Unit

min typ max

Supply current 1 I

1-1 15 20 mA

Supply current 2 I

1-2 Stop mode 2.5 4 mA Output block Output voltage 1-1 V

OUT

1-1 Low level IO= 400 µA 0.1 0.3 V

Output voltage 1-2 V

OUT

1-2 Low level IO= 10 mA 0.8 1.1 V

Output voltage 2 V

OUT

2 High level IO= –20 mA

VCC1 – 1.1 VCC1 – 0.9

Temperature coefficient 1-1 ∆V

OUT

1-1 Design target value*, Low level IO= 400 µA 0.2 mV/°C

Temperature coefficient 1-2 ∆V

OUT

1-2 Design target value*, Low level IO= 10 mA –1.5 mV/°C

Temperature coefficient 2 ∆V

OUT

2 Design target value*, High level IO= –20 mA 1.5 mV/°C 12 V Regulator-voltage output (12REG pin) Output voltage V12REG V

3 = 15 V, IO= –30 mA 11.7 12.1 12.6 V

Voltage regulation

∆12VREG1

VCC3 = 13.5 to 19 V, IO= –30 mA 150 300 mV

Load regulation

∆12VREG2

IO= –5 to –45 mA, VCC3 = 15 V 100 200 mV

Temperature coefficient

∆12VREG3

Design target value* 2 mV/°C 5 V Regulator-voltage output (VREG pin) Output voltage VREG 4.7 5.0 5.3 V Voltage regulation ∆VREG1 V

1 = 8 to 13.5 V 40 100 mV Load regulation ∆VREG2 IO = –5 to –20 mA 5 30 mV Temperature coefficient ∆VREG3 Design target value* 0 mV/°C

Electrical Characteristics at Ta = 25°C, VCC1 = 12 V, VCC2 = VREG

Parameter Symbol Conditions Ratings Unit

Supply voltage range 1-1 V

1-1 VCC1 pin 8 to 13.5 V

Supply voltage range 1-2 V

1-2 VCC1 pin, with VCC1-VREG short-circuited 4.5 to 5.5 V

Supply voltage range 2 V

2 VCC2 pin 4.5 to VCC1 V

Supply voltage range 3 V

3 VCC3 pin 13.5 to 19 V

Output curent I

Pins UL, VL, WL, UH, VH, WH 30 mA 12V constant-voltage output current I12REG –50 mA 5V constant-voltage output current IREG –20 mA HP pin applied voltage VHP 0 to 13.5 V HP pin output current IHP 0 to 10 mA

Allowable Operating Range at Ta = 25°C

Continued on next page.

Note*: These items are design target values and are not tested.

Page 3

No. 7107-3/17

LB11824M

Parameter Symbol Conditions

Ratings

Unit

min typ max Hall Amplifier Block Input bias current IHB (HA) –2 –0.5 µA Common-mode input voltage range 1 VICM1 Hall device used 0.5

VCC1 – 2.0

Common-mode input voltage range 2 VICM2 For input one-side bias (Hall IC application) 0 V

1 V Hall input sensitivity 50 mVp-p Hysteresis width ∆V

(HA) 20 30 50 mV

Input voltage L

→ H VSLH (HA) 5 15 25 mV Input voltage H → L VSHL (HA) –25 –15 –5 mV VCTL pin Input voltage 1 VCTL1 Output duty 0% 1.05 1.4 1.75 V Input voltage 2 VCTL2 Output duty 100% 3.0 3.5 4.1 V Input bias current 1 IB1 (CTL) VCTL = 0 V –80 –60 µA Input bias current 2 IB2 (CTL) VCTL = 5 V 60 80 µA PWM oscillator (PWM pin) Output H level voltage

VOH(PWM)

2.75 3.0 3.25 V

Output L level voltage

VOL(PWM)

1.0 1.2 1.3 V External C charge current ICHG VPWM = 2.1 V –60 –45 –30 µA Oscillator frequency f (PWM) C = 1000pF 17.6 22 26.8 kHz Amplitude V (PWM) 1.6 1.8 2.1 Vp-p TOC pin Input voltage 1 VTOC1 Output duty 0% 2.72 3.0 3.30 V Input voltage 2 VTOC2 Output duty 100% 0.99 1.2 1.34 V Input voltage 1L VTOC1L Design target value*, 0% with V

2 = 4.7 V 2.72 2.80 2.90 V

Input voltage 2L VTOC2L Design target value*, 100% with V

2 = 4.7 V 0.99 1.08 1.17 V

Input voltage 1H VTOC1H Design target value*, 0% with V

2 = 5.3 V 3.08 3.20 3.30 V

Input voltage 2H VTOC2H Design target value*, 100% with V

2 = 5.3 V 1.11 1.22 1.34 V HP pin Output saturation voltage VHPL I

= 7 mA 0.15 0.5 V

Output leakage current IHP leak V

= 13.5 V 10 µA CSD oscillator (CSD pin) Output H level voltage V

(CSD) 3.2 3.6 4.0 V

Output L level voltage V

(CSD) 0.9 1.1 1.3 V External C charge current ICHG1 –14 –10 –6 µA External C discharge current ICHG2 7 11 15 µA Oscillator frequency f (CSD) C = 0.01 µF 200 Hz Amplitude V (CSD) 2.2 2.5 2.75 Vp-p Current limiter circuit (RF pin) Limiter voltage VRF 0.45 0.5 0.55 V

Continued from preceding page.

Continued on next page.

Note*: These items are design target values and are not tested.

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No. 7107-4/17

LB11824M

Parameter Symbol Conditions

Ratings

Unit

min typ max Low-voltage protection circuit (LVS pin) Operating voltage VSDL 3.6 3.8 4.0 V Release voltage VSDH 4.1 4.3 4.5 V Hysteresis width ∆VSD 0.35 0.5 0.65 V Thermal shutdown operation (Overheat protection circuit) Thermal shutdown operating temperature TSD Design target value* (junction temperature) 125 145 165 °C Hysteresis width ∆TSD Design target value* (junction temperature) 20 25 30 °C PWMIN pin Input frequency f (PI) 50 kHz H level input voltage V

(PI) 2.0 VREG V

L level input voltage V

(PI) 0 1.0 V

Input open voltage VIO (PI)

VREG – 0.5

VREG V Hysteresis width VIS (PI) 0.2 0.3 0.4 V H level input current I

(PI) VPWMIN = VREG –10 0 10 µA

L level input current I

(PI) VPWMIN = 0 V –130 –96 µA S/S pin H level input voltage V

(SS) 2.0 VREG V L level input voltage V

(SS) 0 1.0 V Input open voltage VIO (SS)

VREG – 0.5

VREG V

Hysteresis width V

(SS) 0.2 0.3 0.4 V H level input current I

(SS) VS/S = VREG –10 0 10 µA

L level input current I

(SS) VS/S = 0 V –130 –96 µA F/R pin H level input voltage V

(FR) 2.0 VREG V

L level input voltage V

(FR) 0 1.0 V

Input open voltage VIO (FR)

VREG – 0.5

VREG V Hysteresis width VIS (FR) 0.2 0.3 0.4 V H level input current I

(FR) VF/R = VREG –10 0 10 µA

L level input current I

(FR) VF/R = 0 V –130 –96 µA N1 pin H level input voltage V

(N1) 2.0 VREG V

L level input voltage V

(N1) 0 1.0 V

Input open voltage V

(N1)

VREG – 0.5

VREG V

Hysteresis width V

(N1) 0.2 0.3 0.4 V

H level input current I

(N1) VN1 = VREG –10 0 10 µA

L level input current I

(N1) VN1 = 0 V –130 –96 µA N2 pin H level input voltage V

(N2) 2.0 VREG V

L level input voltage V

(N2) 0 1.0 V

Input open voltage V

(N2)

VREG – 0.5

VREG V

H level input current I

(N2) VN2 = VREG –10 0 10 µA

L level input current I

(N2) VN2 = 0 V –130 –96 µA

Continued from preceding page.

Note*: These items are design target values and are not tested.

Page 5

No. 7107-5/17

LB11824M

1.0

0.4

0.8

0.6

0.2

120100806040200–20

Pd max - Ta

0.36W

Ambient temperature, Ta - °C

Power dissipation, Pd max - W

0.9W Independent IC

Three-Phase logic Truth Table (IN = [H] indicates a condition in which IN+ > IN–.)

When S/S and PWMIN pins are not used, set the input to the L level voltage. For HP output, pulsed output of Hall input IN1 (1-Hall output), 1/2 division output of 1 Hall, or synthetic output of three phases of Hall input (three-Hall synthetic output) may be selected.

F/R = L F/R = H Output

IN1 IN2 IN3 IN1 IN2 IN3 PWM — 1 H L H L H L VH UL 2 H L L L H H WH UL 3 H H L L L H WH VL 4 L H L H L H UH VL 5 L H H H L L UH WL 6 L L H H H L VH WL

S/S pin

Input condition Condition

H or open Stop

L Start

PWMIN pin

Input condition Condition

H or open Output OFF

L Output ON

N1,N2 pin

Input condition

HP output

Pin N1 Pin N2

L L 1/2 division L H or open

1 Hall

H or open L H or open H or open Synthesis of three Halls

Page 6

No. 7107-6/17

LB11824M

Pin Assignment

GND N2 HP F/R PWMIN

LB11824M

S/S

RF WH WL VH UH

CSD VCTL PWM

UL V

1 IN1+ IN1–VL

987654321 10 11 12 13 14 15

27 2628 24 2325 2129 2230

19 1820 1617

IN2+ IN2– IN3+ IN3– VREG

TOC 12REG V

3 LVS VCC2

Pin Description

Pin No. Symbol Pin Description Equivalent circuit

Output current detection Connect a resistor(Rf) between this pin and ground. Set with the maximum output current IOUT = 0.5/Rf.

1 RF

VREG

5kΩ

Output pin (external TR drive output) Duty control made on UH, VH, and WH sides.

2 4 6 3 5 7

VCC1

2 4 6 3 5 7

Power supply (output and Hall input blocks). Normally used with the 12 V power supply. Connect to VCC2 and VREG for application with the 5 V single power supply. Connect a capacitor between this pin and GND for stabilization.

Hall amplifier input. IN+ > IN– is the input high state, and the reverse is the input low state. Connect a capacitor between the IN+ and IN– inputs if there

is noise in the Hall sensor signals.

9 10 11 12 13 14

IN1+ IN1– IN2+ IN2– IN3+ IN3–

VCC1

10 12 14

9 11 13

300Ω

Continued on next page.

Page 7

No. 7107-7/17

LB11824M

Pin No. Symbol Pin Description Equivalent circuit

Regulated-voltage output pin (5V output) Connect a capacitor (about 0.1µF) between this pin and

ground for stabilization.

15 VREG

Power pin (PWM oscillation, PWM comparator, VCTL amp). Normally connect to VREG.

VCC1

43kΩ

18kΩ

Voltage detection pin for low-voltage protection. To detect the supply voltage of 5 V or more, connect the zenor diode in series to set the detection voltage.

17 LVS

Power pin (VCC3) for use during application with the supply voltage of 12 V or more.

12 V is generated at the 12 REG pin. To use the 12REG pin, connect this pin to V

1. When not used, keep both

3 and 12 REG open or connect them to GND.

1819V

12REG

VCC2

20kΩ

PWM waveform comparator pin. Normally used in the open condition. By inputting the voltage directly into this pin, the output duty can be controlled without using the VCTL amp.

20 TOC

Continued on next page.

Continued from preceding page.

VCC1

Page 8

No. 7107-8/17

LB11824M

Continued from preceding page.

Pin No. Symbol Pin Description Equivalent circuit

Pin to set the PWM oscillation frequency. Connect a capacitor between this pin and GND.

21 PWM

VCC2

2kΩ

200Ω

Control voltage input pin. For control with this pin, set the PWMIN pin to the L level.

22 VCTL

VCC2

40kΩ

34kΩ

2.26V

Pin to set the operation time of motor lock protection circuit and to set the initial reset pulse.

Connect a capacitor between this pin and GND. When the protection circuit is not to be used, connect a capacitor and resistor (150kW, 4700pF) in parallel between this pin and GND.

23 CSD

VREG

300Ω

Start/stop control pin. Start with L and stop with H or in the open condition

24 S/S

VREG

50kΩ

3.5kΩ 24

PWM pulse input pin. Output drive with L and output OFF with H or in the open condition. For control with this pin, apply the voltage of VCTL2 voltage or more to the VCTL pin.

PWM

VREG

50kΩ

3.5kΩ 25

Continued on next page.

Page 9

No. 7107-9/17

LB11824M

Continued from preceding page.

Pin No. Symbol Pin Description Equivalent circuit

Forward/reverse input pin26 F/R

VREG

50kΩ

3.5kΩ 26

Hall signal output signal27 HP

VREG

Pin to select Hall signal output (HP output)28 N1

VREG

50kΩ

3.5kΩ 28

Pin to select Hall signal output (HP output)29 N2

VREG

50kΩ

3.5kΩ 29

GND pin30 GND

Page 10

Hall-Effect Sensor Input/Output Timing Chart

No. 7107-10/17

LB11824M

F/R = L

F/R = H

IN1

IN2

IN3

IN1

IN2

IN3

PWM output

Page 11

Sample Application Circuit

(1) Bipolar transistor drive (upper side PWM) using a 5 V power supply

No. 7107-11/17

LB11824M

HALL LOGIC

HALL

HYS

AMP

PWM

OSC

F/R

S/S

LOGIC

COMP

TSD

LVSD

CURR

PWM

VCC1

F/R

PRI

DRIVER

GND

12VREG

VCTL

VCC2

VCC1

12VREG

VREG

CSD

PWMIN

VREF

VCC3

VREG

PWM

S/S

LVS

TOC

VREG

–

IN3–IN2–IN1– IN2+IN1+ IN3+

LIM

Page 12

(2) MOS transistor drive (lower side PWM) using a 12 V power supply

No. 7107-12/17

LB11824M

HALL LOGIC

HALL HYS

AMP

PWM

OSC

F/R

S/S

LOGIC

COMP

TSD

LVSD

CURR

PWM

VCC1

F/R

PRI

DRIVER

GND

12VREG

VCTL

VREG

VCC2

VCC1

12VREG

VREG

CSD

PWMIN

Pulse input

VREF

VCC3

VREG

PWM

S/S

LVS

TOC

VREG

–

IN3–IN2–IN1– IN2+IN1+ IN3+

LOGIC

LIM

12V

Page 13

No. 7107-13/17

LB11824M

(3) NMOS transistor plus pnp transistor drive (lower side PWM) using a 15 V power supply

HALL LOGIC

HALL HYS

AMP

PWM

OSC

F/R

S/S

LOGIC

COMP

TSD

LVSD

CURR

PWM

VCC1

F/R

PRI

DRIVER

GND

12VREG

VCTL

VCC2

VCC1

12VREG

VREG

CSD

PWMIN

VREF

VCC3

VREG

PWM

S/S

LVS

TOC

VREG

–

IN3–IN2–IN1– IN2+IN1+ IN3+

LOGIC

LIM

15V

Page 14

LB11824M Function Description

1. Output drive circuit This IC employs a direct PWM drive method to minimize the power loss at output. The output TR is normally saturated in the ON condition, adjusting the motor drive power by changing the output on-duty. Output PWM switching is made on UH, VH, and WH output sides. Since UL - WL and UH- WH outputs are of the same output form, either lower PWM or upper PWM can be selected by changing the external output Tr connection method. Selection of diode to be connected to the non-PWM side output requires attention because there is a problem of reverse recovery time. (Unless a diode with the short reverse recovery time is selected, the through current flows in an instant when the PWM side Tr is turned ON.) UL - WL and UH - WH outputs enter the high impedance condition at a time of stop or when the supply voltage is extremely low (below the allowable operation voltage). Accordingly, an appropriate measure (pull-down resistor, etc.) is necessary in the external circuit to prevent an incorrect action due to the leak current.

2. Current limiting circuit The current limiting circuit performs limiting with the current determined from I = VRF/Rf (VRF= 0.5Vtyp, Rf: current detector resistance) (that is, this circuit limits the peak current). Limiting operation includes decrease in the output on-duty to suppress the current. The current limiting circuit incorporates a filter circuit to prevent an incorrect action of current limiting operation due to detection of the reverse recovery current of output diode during PWM operation. This internal filter circuit will be enough to prevent trouble for normal application. In case of an incorrect action (diode reverse recovery current flowing for 1µs or more), add an external filter circuit (R, C low pass filter, etc.).

3. Power save circuit This IC enters the power save condition to decrease the current dissipation in the stop mode. In this condition, the bias current of most of circuits is cut off. Even in the power save condition, the 5 V regulator output (VREG) is given. If the bias current of Hall device is to be cut, 5V and Hall device may be connected via PNP Tr as a means to meet such needs.

4. Compatibility with various power supplies To operate this IC with external 5V power supply (4.5 - 5.5 V), short-circuit VCC1 and V

REG

pin for connection to power supply. To operate this IC with external 12 V power supply (8 - 13.5 V), connect power supply to VCC1 (5V is generated at the VREG pin to function as a power supply to the control circuit). To operate this IC with external 15 V power supply (13.5 - 19 V), connect power supply to VCC3 and short-circuit 12REG and VCC1 pins (12 V is generated at the 12REG pin to function as a power supply to VCC1). Connect the VCC2 pin basically to the V

REG

pin. In an application in which the motor rotation speed is to be determined by the external fixed voltage (resistor division, etc.), set VCC2 to 12 V (by connecting to VCC1) to suppress variation of the output duty. (Variation of IC is difficult to affect adversely because of increase in the PWM oscillation amplitude and in the comparator dynamic range.)

5. PWM frequency PWM frequency is determined from the capacity C (F) of capacitor connected to the PWM pin.

fPWM .=.1/(45000 × C) Connection of a 1000 pF capacitor causes oscillation of about 22 kHz. Excessively low PWM frequency causes causes a switching sound from the motor while excessively high PWM frequency causes increase in the power loss at the output. About 15 - 50 kHz is recommended. Capacitor GND should be arranged near the IC GND pin as much as possible to protect from the effect of output noise.

No. 7107-14/17

LB11824M

Current detection resistance

To pin RF

To pin VREG

To pin S/S

Hall device

Page 15

6. Drive method The output duty can be controlled according to any of following methods.

• Control with the V

CTL

pin voltage For the control voltage, refer to the electric characteristics. For control with the VCTL pin, set the PWMIN pin voltage to the L level.

• Control with the voltage applied to the TOC pin The TOC pin voltage and PWM oscillation waveform are compared to determine the output duty. The output duty becomes 0 % when the TOC pin voltage exceeds VOH(PWM) (3.0 Vtyp) and 100% when it becomes lower than the VOL(PWM) (1.2 Vtyp). For control with the TOC pin, set the PWMIN pin voltage to the L level. For control with the input level other than the internal CTL amp control input level, external connection of amp allows setting to the arbitrary input level (with the external amp output connected to the TOC pin). For control from the TOC pin, fix the V

CTL

pin voltage.

For an application in which the regulated voltage is applied to the TOC pin through resistor division, etc., it is necessary to take into account the effect of resistor (about 20 kΩ) incorporated between the TOC pin and CTL amp output. (Variation about ±20%, temperature characteristics about +0.3%/°C). If the noise is included in the voltage to be applied to the TOC pin, chattering may occur in the output. In this case, stabilization with a capacitor is necessary.

• Pulse control with the PWMIN pin The output can be controlled on the basis of duty obtained by entering the pulse in the PWMIN pin. The output can be turned ON when the L-level input voltage is applied to the PWM pin and OFF when the H-level input voltage is applied. With the PWMIN pin open, the output becomes the H level and is turned OFF. If input with reversed logic is necessary, addition of external Tr (NPN) may be enough. For control with the PWMIN pin, set the V

CTL

pin voltage that is more than

the V

CTL

2 voltage (output duty set to 100%) or connect the TOC pin to

GND.

7. Hall input signal The Hall input requires the signal input with an amplitude exceeding the hysteresis width (50 mV max). Considering the effect of noise and phase displacement, the input with the amplitude of 120 mV or more is recommended. When the noise causes disturbance in the output waveform (at a time of phase change) or HP output (Hall signal threephase synthesis output), insert a capacitor to the input to prevent such trouble. The Hall input is used as a signal to determine the input to the restriction protection circuit and the protection circuit during reverse. Though noise is ignored to a certain degree, due attention must be paid when using these protection circuits. When all three phases of Hall input signal are entered, the output is turned OFF entirely (all of UL, VL, WL, UH, VH, and WH OFF). To enter the Hall IC output, fix one side of input (+ or –) to the voltage within the common-mode input range for Hall device. This will allow input from 0 to VCC1 for another single-side input.

8. Circuit for low-voltage protection This circuit detects the voltage applied to the LVS pin. When this voltage drops below the operation voltage (see the electric characteristics), the one-side output (UH, VH, and WH) is turned OFF. To prevent repetition of output ON/OFF near the protection activation voltage, the hysteresis is provided. Accordingly, the output is not recovered unless the voltage rises by about 0.5 V above the activation voltage. The protection activation voltage is for the 5V system detection level. The detection level can be raised by connecting the zenor diode in series to the LVS pin and by shifting the detection level. The LVS pin inrush current at a time of detection is about 65µA. To stabilize rise of the zenor diode voltage, increase the diode current by inserting the resistor between the LVS pin and GND. When the protection circuit is not used, apply a voltage on a level where the protection is not activated, instead of setting the LVS pin open (output OFF with the pin open).

No. 7107-15/17

LB11824M

Pin PWMIN

Pulse input

To detection power supply

To pin LVS

Page 16

9. Motor lock protection circuit A motor lock protection circuit is incorporated for protection of IC and motor when the motor is locked. When the Hall input signal is not changed for a certain period with the motor driving, the one-side output (UH, VH, WH) is turned OFF. The time is set by means of a capacity of a capacitor connected to the CSD pin.

Set time (s) .=. 154 × C (µF) Addition of a 0.01 µF capacitor causes a protection time of about 1.54 seconds. (Drive is turned OFF when one cycle of Hall input signal is longer than this time period.) The time to be set must have a sufficient allowance so that the protection is not activated at a normal motor startup. Select the capacitor of 4700 pF or more. The protection circuit is not activated when braking. To cancel the restriction protection condition, one of following steps must be taken:

• Stop mode (10 µs or more)

• Maintaining the output duty 0% condition through input of VCTL or PWMIN for more than the period of tCSD × 2.

(tCSD (s) .=. 0.5 × C (µF). When the 0.01 µF capacitor is added, maintaining for about 10 ms or more is necessary.)

• Re-application of power supply The CSD pin acts also as an initial reset pulse generation pin and causes reset of the logic circuit when connected with GND. Accordingly, the motor drive condition can not be obtained. When this pin is not to be used, a resistor of about 150 kΩ and a capacitor of about 4700 pF must be connected to GND in parallel. When the restriction protection circuit is not used, following functions are also invalid:

• Protection circuit for the reverse mode

• Overheat protection circuit

10. Overheat protection circuit One-side output (UH, VH,WH) is turned OFF when the junction temperature (Tj) exceeds a specified temperature (TSD). Since the minimum variation of TSD is 125°C, thermal design must be made so that Tj = 125°C is not exceeded except in the case of abnormality. Accordingly, Pdmax when Tj (max) = 125°C is 0.72 W (Ta=25°C) When the motor lock protection is not to be used by inserting in parallel the resistor of about 150kΩ and capacitor of about 4700pF between the CSD pin and GND, this overheat protection circuit does not function. In this case, Tj (max) = 150°C, so that Pdmax = 0.9W (Ta = 25°C)

11. Forward/reverse rotation To select forward or reverse in the rotation condition, a measure is taken to prevent flow of the through current (through current due to the output Tr OFF delay time at selection) at the output. Selection during rotation causes the current exceeding the current limit value to flow through the output Tr because of the motor coil resistance and motor reverse electromotive voltage condition. It is therefore necessary to select the external output Tr that is not damaged by this current or to select forward/reverse only when the motor rotation speed has decreased to a certain level.

12. Power supply stabilization This IC is of a switching drive type and the power line tends to be affected. It is therefore necessary to connect a capacitor of sufficient capacity for stabilization between the VCC1 pin and GND. To insert a diode in the power line to prevent breakdown through reverse connection of power supply, the power line becomes more readily affected. It is necessary to select a larger capacity. To turn ON/OFF the power supply with a switch, etc., large distance between the switch and capacitor causes substantial deviation of the supply voltage due to the line inductance and inrush current into the capacitor. In certain cases, the withstand voltage may be exceeded. In this case, do not use a ceramic capacitor whose series impedance is low. Instead, use an electrolytic capacitor to suppress the inrush current and to prevent voltage rise.

13. VREG stabilization To stabilize the V

REG

voltage that is the power supply for the control circuit, connect a 0.1µF or more capacitor

between V

REG

and GND. The capacitor GND must be wired near the GND pin of IC as much as possible.

No. 7107-16/17

LB11824M

Page 17

PS No. 7107-17/17

LB11824M

This catalog provides information as of August, 2002. Specifications and information herein are subject to change without notice.

Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer’s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer’s products or equipment.

SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design.

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Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification” for the SANYO product that you intend to use.

Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.