Datasheet L9954LXP Datasheet (ST)

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Page 1

L9954LXP

Door actuator driver

Features

■ Three half bridges for 0.75 A loads

■ Two configurable high-side driver for up to 1.5A

load (R (R

■ One high-side driver for 6 A load

■ Programmable soft start function to drive loads

with higher inrush currents (i.e. current > 6 A, current > 1.5 A)

■ Very low current consumption in standby mode

■ All outputs short circuit protected

■ Current monitor output for high-side OUT1,

OUT4, OUT5 and OUT6

■ All outputs over temperature protected

■ Open-load diagnostic for all outputs

■ Overload diagnostic for all outputs

■ PWM control of all outputs

■ Charge pump output for reverse polarity

protection

=1600mΩ)

DSon

=500mΩ) or 0.35 A load

DSon

=1800mΩ)

=100mΩ)

DSon

< 6 µA typ; Tj ≤ 85 °C)

PowerSSO-36

Applications

■ Door actuator driver with bridges for mirror axis

control and high-side driver for mirror defroster and two 10 W light bulbs and/or LEDs.

Description

The L9954LXP is a microcontroller driven multifunctional door actuator driver for automotive applications. Up to two DC motors and three grounded resistive loads can be driven with three half bridges and three high-side drivers. The integrated standard Serial Peripheral Interface (SPI) controls all operation modes (forward, reverse, brake and high impedance). All diagnostic information is available via SPI.

Table 1. Device summary

Package

PowerSSO-36 L9954LXP L9954LXPTR

May 2010 Doc ID 16186 Rev 2 1/35

Order codes

Tube Tape and reel

www.st.com

Page 2

Contents L9954LXP

Contents

1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.2 ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.5 SPI - electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.1 Dual power supply: VS and VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.2 Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.3 Inductive loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.4 Diagnostic functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.5 Overvoltage and under voltage detection . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.6 Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.7 Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . 21

3.8 Open-load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.9 Overload detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.10 Current monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.11 PWM inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.12 Cross-current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.13 Programmable soft start function to drive loads with higher inrush current

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4 Functional description of the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.1 Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.2 Chip Select Not (CSN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.3 Serial Data In (DI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.4 Serial Data Out (DO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.5 Serial Clock (CLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.6 Input Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2/35 Doc ID 16186 Rev 2

Page 3

L9954LXP Contents

4.7 Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.8 SPI - input data and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5 Packages thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6.1 ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6.2 PowerSSO-36 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6.3 PowerSSO-36 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Doc ID 16186 Rev 2 3/35

Page 4

List of tables L9954LXP

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 4. ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 5. Operating junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 6. Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 7. Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 8. Overvoltage and under voltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 9. Current monitor output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 10. Charge pump output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 11. OUT1 - OUT6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 12. Delay time from standby to active mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 13. Inputs: CSN, CLK, PWM1/2 and DI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 14. DI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 15. DO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 16. DO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 17. CSN timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 18. SPI - input data and status registers 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 19. SPI - input data and status registers 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 20. PowerSSO-36 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 21. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4/35 Doc ID 16186 Rev 2

Page 5

L9954LXP List of figures

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2. Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 3. SPI - transfer timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 4. SPI - input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 5. SPI - DO valid data delay time and valid time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 6. SPI - DO enable and disable time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 7. SPI - driver turn-on / off timing, minimum CSN HI time . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 8. SPI - timing of status bit 0 (fault condition) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 9. Programmable soft start function for inductive loads and incandescent bulbs . . . . . . . . . . 23

Figure 10. Packages thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 11. PowerSSO-36 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 12. PowerSSO-36 Figure 13. PowerSSO-36

tube shipment (no suffix). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Doc ID 16186 Rev 2 5/35

Page 6

Block diagram and pin description L9954LXP

1 Block diagram and pin description

Figure 1. Block diagram

BAT

Reverse Polarity

Protection

100k

100µF

* Note: Value of capacitor has to be choosen carefully to li mit the VS voltage below absolute

maximum ratings in case of an unexpected freewheeling condition ( e.g. TSD, POR)

10k

VCC

Charge

Pump

VCC

DO CLK CSN

PWM1

SPI

Interface

Driver Interface & Diagnostic

µC

PWM2 / CM

** Note: Resistors between µC and L9954LXP are recommended to lim it currents for negative voltage transients at VBAT (e.g. ISO type 1 pulse)

MUX

GND

Figure 2. Configuration diagram (top view)

GND

OUT6

OUT1

OUT2

OUT3

CM / PWM2

CSN

Vcc

CLK

NC NC

GND

13 14

16 17

PowerSSO-36

OUT1

OUT2

OUT3

Mirror Common

Mirror Vertical

Mirror Horizontal

Lock / Folder

OUT4

Programmable

OUT5

OUT6

Bulb (10W) or

LED Mode

Defroster

GND 36

OUT6

NC 34

OUT5

OUT4

PWM1

GND

6/35 Doc ID 16186 Rev 2

Page 7

L9954LXP Block diagram and pin description

Table 2. Pin definitions and functions

Pin Symbol Function

Ground:

1, 18, 19, 36 GND

2, 35 OUT6

3 4 5

6, 7, 14, 25,

28, 32

OUT1 OUT2

OUT3

8DI

9 CM/PWM2

10 CSN

11 DO

reference potential. Important: for the capability of driving the full current at the outputs all

pins of GND must be externally connected.

High-side driver output 6 The output is built by a high-side switch and is intended for resistive

loads, hence the internal reverse diode from GND to the output is missing. For ESD reason a diode to GND is present but the energy which can be dissipated is limited. The high-side driver is a power DMOS transistor with an internal parasitic reverse diode from the output to V

(bulk-drain-diode). The output is over-current and open-

load protected. Important: for the capability of driving the full current at the outputs both pins of OUT6 must be externally connected.

Half-bridge output 1,2,3 The output is built by a high-side and a low-side switch, which are

internally connected. The output stage of both switches is a power DMOS transistor. Each driver has an internal parasitic reverse diode (bulk-drain-diode: high-side driver from output to V

, switchs driver

from GND to output). This output is over-current and open-load protected.

Power supply voltage (external reverse protection required) For this input a ceramic capacitor as close as possible to GND is

recommended.

Important: for the capability of driving the full current at the outputs all pins of V

must be externally connected.

Serial data input The input requires CMOS logic levels and receives serial data from the

microcontroller. The data is an 24bit control word and the least significant bit (LSB, bit 0) is transferred first.

Current monitor output/PWM2 input Depending on the selected multiplexer bits of input data register this

output sources an image of the instant current through the corresponding high-side driver with a ratio of 1/10.000. This pin is bidirectional. The microcontroller can overdrive the current monitor signal to provide a second PWM input for the output OUT5.

Chip select not input This input is low active and requires CMOS logic levels. The serial data

transfer between L9954LXP and micro controller is enabled by pulling the input CSN to low-level.

Serial data output The diagnosis data is available via the SPI and this 3-state output. The

output remains in 3-state, if the chip is not selected by the input CSN (CSN = high)

Doc ID 16186 Rev 2 7/35

Page 8

Block diagram and pin description L9954LXP

Table 2. Pin definitions and functions (continued)

Pin Symbol Function

Logic supply voltage

12 V

13 CLK

26 CP

27 PWM1

31 33

15, 16, 17, 20, 21, 22, 23, 24,

29, 30, 34

OUT4,

OUT5

NC Not connected pins.

For this input a ceramic capacitor as close as possible to GND is recommended.

Serial clock input This input controls the internal shift register of the SPI and requires

CMOS logic levels.

Charge pump output This output is provided to drive the gate of an external n-channel power

MOS used for reverse polarity protection.

PWM1 input This input signal can be used to control the drivers OUT1-OUT4 and

OUT6 by an external PWM signal.

High-side driver output 4 and 5 Each output is built by a high-side switch and is intended for resistive

loads, hence the internal reverse diode from GND to the output is missing. For ESD reason a diode to GND is present but the energy which can be dissipated is limited. Each high-side driver is a power DMOS transistor with an internal parasitic reverse diode from each output to V

(bulk-drain-diode). Each output is over-current and open-

load protected.

8/35 Doc ID 16186 Rev 2

Page 9

L9954LXP Electrical specifications

2 Electrical specifications

2.1 Absolute maximum ratings

Stressing the device above the rating listed in the “Absolute maximum ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality document

Table 3. Absolute maximum ratings

Symbol Parameter Value Unit

, V

DO, VCLK

CSN, Vpwm1

OUT1,2,3,4,5

OUT6

2.2 ESD protection

Table 4. ESD protection

All pins ± 2

Output pins: OUT1 - OUT6 ± 8

1. HBM according to MIL 883C, Method 3015.7 or EIA/JESD22-A114-A.

2. HBM with all unzapped pins grounded.

DC supply voltage -0.3 to 28 V

Single pulse t

< 400 ms 40 V

max

Stabilized supply voltage, logic supply -0.3 to 5.5 V

Digital input / output voltage -0.3 to V

+ 0.3 V

Current monitor output -0.3 to VCC + 0.3 V

Charge pump output -25 to VS + 11 V

Output current ±5 A

Output current ±10 A

Parameter Value Unit

(1)

(2)

2.3 Thermal data

Table 5. Operating junction temperature

Symbol Parameter Value Unit

Operating junction temperature -40 to 150 °C

Doc ID 16186 Rev 2 9/35

Page 10

Electrical specifications L9954LXP

Table 6. Temperature warning and thermal shutdown

Symbol Parameter Min. Typ. Max. Unit

jTW On

jSD On

jSD Off

jSD HYS

Temperature warning threshold junction temperature

Thermal shutdown threshold junction temperature

Thermal shutdown hysteresis 5 °K

2.4 Electrical characteristics

Values specified in this section are for VS = 8 to 16 V, VCC = 4.5 to 5.3 V, Tj = - 40 to 150 °C, unless otherwise specified. The voltages are referred to GND and currents are assumed positive, when the current flows into the pin.

Table 7. Su p ply

Symbol Parameter Test condition Min. Typ. Max. Unit

Operating supply voltage

range

VS DC supply current

quiescent supply current

VCC DC supply current

quiescent supply

current

increasing

decreasing

VS = 16 V, VCC = 5.3 V active mode OUT1 - OUT6 floating

= 16 V, VCC = 0 V

standby mode OUT1 - OUT6 floating

= -40 °C, 25 °C

test

= 85 °C

test

= 16 V, VCC = 5.3 V

CSN = V

= 16 V, VCC = 5.3 V

CSN = V

(1)

active mode

CC ,

standby mode

OUT1 - OUT6 floating

130 150 °C

150 °C

170 °C

728V

720mA

412µA

625µA

13mA

25 50 µA

= 16 V, VCC = 5.3 V

IS + I

1. Guaranteed by design.

Sum quiescent supply

current

CSN = V standby mode OUT1 - OUT6 floating T

= 130 °C

test

10/35 Doc ID 16186 Rev 2

50 200 µA

Page 11

L9954LXP Electrical specifications

Table 8. Overvoltage and under voltage detection

Symbol Parameter Test condition Min. Typ. Max. Unit

SUV OnVS

SUV OffVS

SUV hystVS

SOV OffVS

SOV OnVS

SOV hystVS

POR Off

POR On

POR hyst

Table 9. Current monitor output

UV-threshold voltage VS increasing 5.7 7.2 V

UV-threshold voltage VS decreasing 5.5 6.9 V

UV-hysteresis V

SUV On

- V

SUV Off

0.5 V

OV-threshold voltage VS increasing 18 24.5 V

OV-threshold voltage VS decreasing 17.5 23.5 V

OV-hysteresis V

SOV Off

- V

SOV On

Power-on reset threshold VCC increasing 4.4 V

Power-on reset threshold VCC decreasing 3.1 V

Power-on reset hysteresis V

POR Off

- V

POR On

0.3 V

Symbol Parameter Test condition Min. Typ. Max. Unit

CM,r

Functional voltage range VCC = 5 V 0 4 V

Current monitor output ratio: I

CM/IOUT6

Current monitor output ratio: ICM/I

OUT1

Current monitor output ratio: I

CM/IOUT4,5

low R

DSon

mode

Current monitor output ratio: I

CM/IOUT4,5

high R

DSon

mode

0V ≤ V

=5V

≤ 4V,

----------------

10000

------------ -

3800

----------------

10200

------------ -

2400

Doc ID 16186 Rev 2 11/35

Page 12

Electrical specifications L9954LXP

Table 9. Current monitor output (continued)

Symbol Parameter Test condition Min. Typ. Max. Unit

Current monitor accuracy Acc I

CM/IOUT 8

Current monitor accuracy Acc I

CM/IOUT 1

CM acc

Current monitor accuracy Acc I

CM/IOUT 4,5

high R

DSon

mode

Current monitor accuracy Acc ICM/I low R

Table 10. Charge pump output

DSon

OUT 4,5

mode

0 V ≤ V V

Out,min 8

Out max 8

0 V ≤ V V

Out,min 1

Out max 1

0 V ≤ V V

Out,min 4,5

Out max 4,5

0 V ≤ V V

Out,min 4,5

Out max 4,5

= 5 V,

= 5V,

= 5 V,

≤ 3.8 V,

= 0.5 A,

= 5.9 A

≤ 3.8 V,

= 60mA,

= 0.6A

≤ 3.8 V,

= 30 mA,

= 300 mA

≤ 3.8 V,

= 150 mA,

= 1 A

4% +

1%FS

8% +

2%FS

Symbol Parameter Test condition Min. Typ. Max. Unit

VS = 8 V, I

Charge pump output

voltage

Charge pump output

current

= 10 V, I

≥ 12 V, ICP = -100 µA VS+10 VS+13 V

= VS+10V,

VS= 13.5 V

= -60 µA VS+6 VS+13 V

= -80 µA VS+8 VS+13 V

95 150 300 µA

Table 11. OUT1 - OUT6

Symbol Parameter Test condition Min. Typ. Max. Unit

= 13.5 V, Tj = 25 °C,

DSon OUT1,

DSon OUT2

DSon OUT3

On resistance to supply or GND

OUT1,2,3

= ± 0.4 A

= 13.5 V, Tj = 125 °C,

= ± 0.4 A

VS = 13.5 V, Tj = 25 °C,

= -0.8 A

OUT4,5

= 13.5 V, Tj = 125 °C,

= -0.8 A

OUT4,5

= 25 °C, I

= 125 °C, I

DSon OUT4,

DSon OUT5

On resistance to supply in low R

DSon

mode

On resistance in high

mode

DSon

V I

12/35 Doc ID 16186 Rev 2

1600 2200 mΩ

2500 3400 mΩ

500 700 mΩ

700 950 mΩ

= - 0.2 A 2000 2700 mΩ

OUT4,5

= - 0.2 A 3200 4300 mΩ

OUT4,5

Page 13

L9954LXP Electrical specifications

Table 11. OUT1 - OUT6 (continued)

Symbol Parameter Test condition Min. Typ. Max. Unit

= 13.5 V, Tj = 25 °C,

DSon OUT6

OUT1

OUT2

OUT3

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

d On H

On resistance to supply

Output current limitation to GND

Output current limitation to supply

Output current limitation to GND in low R

DSon

mode

Output current limitation to GND in high R

DSon

mode

Output current limitation to GND

Output delay time, highside driver on

= −3 A

OUT6

= 13.5 V, Tj = 125 °C,

= −3 A

OUT6

Source, V

Sink, V

Source, V

= 13.5 V, R

= 13.5 V -1.25 -0.75 A

= 13.5 V 0.75 1.25 A

= 13.5 V

= 13.5 V -10.5 -6 A

(1)

load

corresponding low-side driver is not active

-0.65 -0.35 A

100 150 mΩ

150 200 mΩ

-3.0 -1.5 A

10 40 80 µs

d Off H

d On L

d Off L

d HL

d LH

QLH

QLL

OLD123

Output delay time, highside driver off

Output delay time, lowside driver on

Output delay time, lowside driver off

Cross current protection time, source to sink

Cross current protection time, sink to source

Switched-off output current high-side drivers of OUT1-6

Switched-off output current low-side drivers of OUT1-3

Open-load detection current of OUT1, OUT2 and OUT3

= 13.5 V, R

corresponding high-side

load

(2)

15 150 300 µs

15 30 70 µs

driver is not active

= 13.5 V, R

CC ONLS_OFFHS

CC ONHS_OFFLS

= 0 V, standby mode -3 0 -3 µA

OUT1-6

OUT1-2-3-6

= 0 V, active

mode

= 0 V, active mode -10 -8 0 µA

OUT4-5

= VS, standby mode 0 80 120 µA

OUT1-3

= VS, active mode -40 -15 0 µA

OUT1-3

load

- td

(2)

Off H

OFF L

20 150 300 µs

(2)

200 400 µs

-40 -15 0 µA

Source and sink 10 20 30 mA

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Page 14

Electrical specifications L9954LXP

Table 11. OUT1 - OUT6 (continued)

Symbol Parameter Test condition Min. Typ. Max. Unit

Open-load detection

OLD45

current of OUT4 and OUT5

Open-load detection current of OUT4 and OUT5 in high R

DSon

mode

Source

15 40 60 mA

51015mA

OLD6

Open-load detection current of OUT6

Minimum duration of

d OL

open-load condition to set the status bit

Minimum duration of over-

ISC

current condition to switch off the driver

Recovery frequency for

rec0

OC recovery duty cycle bit=0

Recovery frequency for

rec1

OC recovery duty cycle bit=1

/dt

OUT123

OUT45

OUT6

1. OUT1,2,3 32OHM OUT4,5 16OHM OUT4,5 high RDSon mode 63OHM OUT6 4OHM

2. t

CC ON

Slew rate of OUT OUT

/dt

is the switch On delay time t

Slew rate of OUT

Source 30 150 300 mA

and

123

VS = 13.5 V, R

if complement in half bridge has to switch off.

d ON

load

(2)

500 3000 µs

10 100 µs

1 4 kHz

2 6 kHz

0.1 0.4 0.9 V/µs

0.08 0.2 0.4 V/µs

2.5 SPI - electrical characteristics

Values specified in this section are VS = 8 to 16 V, VCC = 4.5 to 5.3 V, Tj = - 40 to 150 °C, unless otherwise specified. The voltages are referred to GND and currents are assumed positive, when the current flows into the pin.

Table 12. Delay time from standby to active mode

Symbol Parameter Test condition Min. Typ. Max. Unit

Switching from standby to active mode.

set

14/35 Doc ID 16186 Rev 2

Delay time

Time until output drivers are enabled after CSN going to high.

160 300 µs

Page 15

L9954LXP Electrical specifications

Table 13. Inputs: CSN, CLK, PWM1/2 and DI

Symbol Parameter Test condition Min. Typ. Max. Unit

inHyst

CSN in

CLK in

DI in

PWM1 in

1. Value of input capacity is not measured in production test. Parameter guaranteed by design.

Table 14. DI timing

Input low-level VCC = 5 V 1.5 2.0 V

inL

Input high-level VCC = 5 V 3.0 3.5 V

inH

Input hysteresis VCC = 5 V 0.5 V

Pull up current at input CSN V

Pull down current at input CLK V

= 3.5 V, VCC = 5 V -40 -20 -5 µA

CSN

= 1.5 V 10 25 50 µA

CLK

Pull down current at input DI VDI = 1.5 V 10 25 50 µA

Pull down current at input PWM1

Input capacitance at input

(1)

CSN, CLK, DI and PWM1/2

(1)

= 1.5 V 10 25 50 µA

PWM

0 V < V

< 5.3 V 10 15 pF

Symbol Parameter Test condition Min. Typ. Max. Unit

CLK

CLKH

CLKL

set CSN

Clock period VCC = 5 V 1000 - ns

Clock high time VCC = 5 V 400 - ns

Clock low time VCC = 5 V 400 - ns

CSN setup time, CSN low before rising edge of CLK

= 5 V 400 - ns

set CLK

set DI

hold DI

1. DI timing parameters tested in production by a passed / failed test: Tj = -40 °C / +25 °C: SPI communication @ 2 MHz. Tj = +125 °C SPI communication @ 1.25 MHz.

Table 15 . DO

CLK setup time, CLK high before rising edge of CSN

DI setup time VCC = 5 V 200 - ns

DI hold time VCC = 5 V 200 - ns

Rise time of input signal DI, CLK,

r in

CSN

Fall time of input signal DI, CLK,

f in

CSN

= 5 V 400 - ns

= 5 V - 100 ns

Symbol Parameter Test condition Min. Typ. Max. Unit

DOL

DOH

Output low-level VCC = 5 V, ID = -2 mA 0.2 0.4 V

Output high-level VCC = 5 V, ID = 2 mA VCC-0.4 VCC-0.2 V

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Page 16

Electrical specifications L9954LXP

Table 15. DO (continued)

Symbol Parameter Test condition Min. Typ. Max. Unit

= VCC,

DOLK

1. Value of input capacity is not measured in production test. Parameter guaranteed by design.

Table 16. DO timing

3-state leakage current

3-state input

(1)

capacitance

Symbol Parameter Test condition Min. Typ. Max. Unit

CSN

0V < V

= VCC,

CSN

0V < V

< V

< 5.3 V

-10 10 µA

10 15 pF

r DO

f DO

en DO tri L

dis DO L tri

DO rise time CL = 100 pF, I

DO fall time CL = 100 pF, I

DO enable time from 3-state to low-level

DO disable time from low-level to 3-state

DO enable time

en DO tri H

from 3-state to highlevel

DO disable time

dis DO H tri

from high-level to 3state

d DO

Table 17. CSN timing

DO delay time

CL = 100 pF, I pull up load to V

=100 pF, I

pull down load to GND

= 100 pF, I

down load to GND

< 0.3 VCC, V

= 100pF

= -1 mA - 80 140 ns

load

= 1 mA - 50 100 ns

load

= 1 mA

load

= 4 mA

load

= -1 mA

load

= -4 mA pull

load

> 0.7 VCC,

- 100 250 ns

- 380 450 ns

- 100 250 ns

- 380 450 ns

- 50 250 ns

Symbol Parameter Test condition Min. Typ. Max. Unit

CSN_HI,stb

CSN_HI,min

CSN HI time, switching from standby mode

CSN HI time, active mode

Transfer of SPI command to Input Register

Transfer of SPI command to input register

20 - - µs

4--µs

16/35 Doc ID 16186 Rev 2

Page 17

L9954LXP Electrical specifications

Figure 3. SPI - transfer timing diagram

CSN high to low: DO enabled

CSN

time

0 1

time

CLK

Input

Input Data

Data

123456 70

DI: data will be accepted on the rising edge of CLK signal

123 45670

DO: data will change on the falling edge of CLK signal

123 45670

fault bit

transfered to output power switches

CSN low to high: actual data is

old data new data

232221201918

Figure 4. SPI - input timing

CSN

set C SN

CLK

set DI

Valid

CLKH

hold DI

CLKL

Va lid

se t CLK

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

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Page 18

Electrical specifications L9954LXP

Figure 5. SPI - DO valid data delay time and valid time

CLK

r DO

(low to high)

d DO

(high to low)

Figure 6. SPI - DO enable and disable time

f in r in

CSN

r i n

0.8 VCC

0.5 VCC

0.2 VCC

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

0.8 VCC 50%

0.2 VCC

pull-up load to VCC

C = 100 pF

t t

en DO tri L

pull-down load to GND

C = 100 pF

t t

18/35 Doc ID 16186 Rev 2

50%

dis DO L tri

50%

Page 19

L9954LXP Electrical specifications

OFF

ON stateOFF

stat

rom shif

Figure 7. SPI - driver turn-on / off timing, minimum CSN HI time

CSN

ut curren

out

output voltage

of a driv

of a driver

output curren

output voltage

of a driv

of a driver

OFF state

CSN low to high: data is

dON

ansf e

ed to output powerswitches

CSN_HI,min

ON sta

tregister

80%

50%

20%

80%

50%

20%

80%

50%

20%

Figure 8. SPI - timing of status bit 0 (fault condition)

CSN high to low and CLK stays low: status information of data bit 0 (fault condition) is transfered to DO

CSN

CLK

DI: data is not accepted

DO: status information of data bit 0 (fault condition) will stay as long as CSN is low

time

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Page 20

Application information L9954LXP

3 Application information

3.1 Dual power supply: VS and V

The power supply voltage VS supplies the half bridges and the high-side drivers. An internal charge-pump is used to drive the high-side switches. The logic supply voltage V (stabilized 5 V) is used for the logic part and the SPI of the device.

Due to the independent logic supply voltage the control and status information not are lost, if there are temporary spikes or glitches on the power supply voltage. In case of power-on (V

increases from under voltage to V

internally generated power-on-reset (POR). If the voltage V minimum threshold (V and the status registers are cleared.

POR ON

= 3.4 V), the outputs are switched to 3-state (high impedance)

POR Off

3.2 Standby mode

The standby mode of the L9954LXP is activated by clearing the bit 23 of the input data register 0. All latched data is cleared and the inputs and outputs are switched to high impedance. In the standby mode the current at V CSN = high (DO in 3-state). By switching the V be achieved. If bit 23 is set, the device is switched to active mode.

3.3 Inductive loads

Each half bridge is built by an internally connected high-side and a low-side power DMOS transistor. Due to the built-in reverse diodes of the output transistors, inductive loads can be driven at the outputs OUT1 to OUT3 without external free-wheeling diodes. The high-side drivers OUT4 to OUT6 are intended to drive resistive loads. Hence only a limited energy (E<1mJ) can be dissipated by the internal ESD-diodes in freewheeling condition. For inductive loads (L>100μH) an external free-wheeling diode connected to GND and the corresponding output is needed.

= 4.2 V) the circuit is initialized by an

decreases under the

(VCC) is less than 6 µA (50µA) for

voltage a very low quiescent current can

3.4 Diagnostic functions

All diagnostic functions (over/open-load, power supply over-/under voltage, temperature warning and thermal shutdown) are internally filtered and the condition has to be valid for at least 32 µs (open-load: 1ms, respectively) before the corresponding status bit in the status registers is set. The filters are used to improve the noise immunity of the device. Open-load and temperature warning function are intended for information purpose and not changes the state of the output drivers. On contrary, the overload condition disables the corresponding driver (over-current) and overtemperature switchs off all drivers (thermal shutdown). Without setting the over-current recovery bits in the input data register, the microcontroller has to clear the over-current status bits to reactivate the corresponding drivers.

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L9954LXP Application information

3.5 Overvoltage and under voltage detection

If the power supply voltage VS rises above the overvoltage threshold V the outputs OUT1 to OUT6 are switched to high impedance state to protect the load. When the voltage V output stages are switched to the high impedance to avoid the operation of the power devices without sufficient gate driving voltage (increased power dissipation). If the supply voltage V return to the programmed state after at least 32 µs.

If the under voltage/overvoltage recovery disable bit is set, the automatic turn-on of the drivers is deactivated. The microcontroller needs to clear the status bits to reactivate the drivers. It is strongly recommended to set bit 20 to avoid a possible high current oscillation in case of a shorted output to GND and low battery voltage.

drops below the under voltage threshold V

recovers (register 0: bit 20=0) to normal operating voltage the outputs stages

(UV-switch-off voltage), the

SUV Off

3.6 Charge pump

The charge pump runs under all conditions in normal mode. In standby the charge pump is out of action.

3.7 Temperature warning and thermal shutdown

If junction temperature rises above T µs and is detectable via the SPI. If junction temperature increases above the second threshold T stages are switched off to protect the device after at least 32 µs. Temperature warning flag and thermal shutdown bit are latched and must be cleared by the microcontroller. The related bit is only cleared if the temperature decreases below the trigger temperature. If the thermal shutdown bit has been cleared the output stages are reactivated.

, the thermal shutdown bit is set and power DMOS transistors of all output

j SD

a temperature warning flag is set after at least 32

j TW

(typical 21 V),

SOV Off

3.8 Open-load detection

The open-load detection monitors the load current in each activated output stage. If the load current is below the open-load detection threshold for at least 1 ms (t open-load bit is set in the status register. Due to mechanical/electrical inertia of typical loads a short activation of the outputs (e.g. 3 ms) can be used to test the open-load status without changing the mechanical/electrical state of the loads.

3.9 Overload detection

In case of an over-current condition a flag is set in the status register in the same way as open-load detection. If the over-current signal is valid for at least t current flag is set and the corresponding driver is switched off to reduce the power dissipation and to protect the integrated circuit. If the over-current recovery bit of the output is zero the microcontroller has to clear the status bits to reactivate the corresponding driver.

) the corresponding

dOL

= 32 µs, the over-

ISC

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Page 22

Application information L9954LXP

3.10 Current monitor

The current monitor output sources a current image at the current monitor output which has a fixed ratio (1/10000) of the instantaneous current of the selected high-side driver. Signal at output CM is blanked after switching on of driver until correct settlement of circuitry (at least for 32 µs).

The bits 18 and 19 of the input data register 0 control which of the outputs OUT1, OUT4, OUT5 and OUT6 is multiplexed to the current monitor output. The current monitor output allows a more precise analysis of the actual state of the load rather than the detection of an open- or overload condition. For example this can be used to detect the motor state (starting, free-running, stalled). Moreover, it is possible to regulate the power of the defroster more precise by measuring the load current. The current monitor output is bidirectional (c.f. PWM inputs).

3.11 PWM inputs

Each driver has a corresponding PWM enable bit which can be programmed by the SPI interface. If the PWM enable bit in Input data register 1 is set, the output is controlled by the logically AND-combination of the PWM signal and the output control bit in input data register 0. The outputs OUT1-OUT4 and OUT6 are controlled by the PWM1 input and the output OUT5 is controlled by the bidirectional input CM/PMW2. For example, the two PWM inputs can be used to dim two lamps independently by external PWM signals.

3.12 Cross-current protection

The three half-bridges of the device are cross-current protected by an internal delay time. If one driver (LS or HS) is turned-off the activation of the other driver of the same half bridge is automatically delayed by the cross-current protection time. After the cross-current protection time is expired the slew-rate limited switch-off phase of the driver is changed to a fast turn-off phase and the opposite driver is turned-on with slew-rate limitation. Due to this behavior it is always guaranteed that the previously activated driver is totally turned-off before the opposite driver starts to conduct.

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L9954LXP Application information

3.13 Programmable soft start function to drive loads with higher inrush current

Loads with start-up currents higher than the overcurrent limits (e.g. inrush current of lamps, start current of motors and cold resistance of heaters) can be driven by using the programmable soft start function (i.e. overcurrent recovery mode). Each driver has a corresponding over-current recovery bit. If this bit is set, the device switchs automatically on the outputs again after a programmable recovery time. The duty cycle in over-current condition can be programmed by the SPI interface to be about 15 %...25 %. The PWM modulated current provides sufficient average current to power up the load (e.g. heat up the bulb) until the load reaches operating condition. The PWM frequency settles at 1.5 kHz or 3 kHz. The device itself cannot distinguish between a real overload and a non linear load like a light bulb. A real overload condition can only be qualified by time. As an example the microcontroller can switch on light bulbs by setting the over-current recovery bit for the first 50ms. After clearing the recovery bit the output is automatically disabled if the overload condition still exits.

Figure 9. Programmable soft start function for inductive loads and incandescent bulbs

Load Current

Overcurrent detection

Unlimited Inrush Current

Limited Inrush Current in overcurrent recovery mode with inductive load

Load Current

Overcurrent detection

Unlimited Inrush Current

Limited Inrush Current in overcurrent recovery mode with incandescent bulb

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Page 24

Functional description of the SPI L9954LXP

4 Functional description of the SPI

4.1 Serial Peripheral Interface (SPI)

This device uses a standard SPI to communicate with a microcontroller. The SPI can be driven by a microcontroller with its SPI peripheral running in following mode: CPOL = 0 and CPHA = 0.

For this mode, input data is sampled by the low to high transition of the clock CLK, and output data is changed from the high to low transition of CLK.

This device is not limited to microcontroller with a build-in SPI. Only three CMOS compatible output pins and one input pin are needed to communicate with the device. A fault condition can be detected by setting CSN to low. If CSN = 0, the DO pin reflects the status bit 0 (fault condition) of the device which is a logical-or of all bits in the status registers 0 and 1. The microcontroller can poll the status of the device without the need of a full SPI communication cycle.

Note: In contrast to the SPI standard the least significant bit (LSB) is transferred first

(see Figure 3).

4.2 Chip Select Not (CSN)

The input pin is used to select the serial interface of this device. When CSN is high, the output pin (DO) is in high impedance state. A low signal activates the output driver and a serial communication can be started. The state when CSN is going low until the rising edge of CSN is called a communication frame.

4.3 Serial Data In (DI)

The input pin is used to transfer data serial into the device. The data applied to the DI is sampled at the rising edge of the CLK signal and shifted into an internal 24 bit shift register. At the rising edge of the CSN signal the contents of the shift register is transferred to data input register. The writing to the selected data input register is only enabled if exactly 24 bits are transmitted within one communication frame (i.e. CSN low). If more or less clock pulses are counted within one frame the complete frame is ignored. This safety function is implemented to avoid an activation of the output stages by a wrong communication frame.

Note: Due to this safety functionality a daisy chaining of SPI is not possible. Instead, a parallel

operation of the SPI bus by controlling the CSN signal of the connected ICs is recommended.

4.4 Serial Data Out (DO)

The data output driver is activated by a logical low-level at the CSN input and goes from high impedance to a low or high-level depending on the status bit 0 (fault condition). The first rising edge of the CLK input after a high to low transition of the CSN pin transfers the content of the selected status register into the data out shift register. Each subsequent falling edge of the CLK shifts the next bit out.

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L9954LXP Functional description of the SPI

4.5 Serial Clock (CLK)

The CLK input is used to synchronize the input and output serial bit streams. The data input (DI) is sampled at the rising edge of the CLK and the data output (DO) changes with the falling edge of the CLK signal.

4.6 Input Data Register

The device has two input registers. The first bit (bit 0) at the DI input is used to select one of the two input registers. All bits are first shifted into an input shift register. After the rising edge of CSN the contents of the input shift register is written to the selected input data register only if a frame of exact 24 data bits are detected. Depending on bit 0 the contents of the selected status register is transferred to DO during the current communication frame. Bit 1-17 controls the behavior of the corresponding driver.

If bit 23 is zero, the device goes into the standby mode. The bits 18 and 19 are used to control the current monitor multiplexer. Bit 22 is used to reset all status bits in both status registers. The bits in the status registers is cleared after the current communication frame (rising edge of CSN).

4.7 Status register

This devices uses two status registers to store and to monitor the state of the device. No error bit (bit 0) is used as a fault bit and is a logical-NOR combination of bits 1-22 in both status registers. The state of this bit can be polled by the microcontroller without the need of a full SPI communication cycle. If one of the over-current bits is set, the corresponding driver is disabled. If the over-current recovery bit of the output is not set the microcontroller has to clear the over-current bit to enable the driver. If the thermal shutdown bit is set, all drivers goes into a high impedance state. Again the microcontroller has to clear the bit to enable the drivers.

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Page 26

Functional description of the SPI L9954LXP

4.8 SPI - input data and status registers

Table 18. SPI - input data and status registers 0

Input register 0 (write) Status register 0 (read)

Bit

Name Comment Name Comment

If enable bit is set the

23 Enable bit

device switches in active mode. If enable bit is cleared the device goes into standby mode and all bits are cleared. After power-on reset device starts in standby mode.

Always 1

A broken VCC-or SPI connection of the L9954LXP can be detected by the microcontroller, because all 24 bits low or high is not a valid frame.

22 Reset bit

OC recovery

duty cycle

0: 12% 1: 25%

Overvoltage/

undervoltage

recovery

disable

Current monitor

select bits

If reset bit is set both status registers are cleared after rising edge of CSN input.

This bit defines in combination with the overcurrent recovery bit (input register 1) the duty cycle in overcurrent condition of an activated driver.

If this bit is set the microcontroller has to clear the status register after under voltage / overvoltage event to enable the outputs.

Depending on combination of bit 18 and 19 the current image (1/10.000) of the selected HS-output is multiplexed to the CM output:

Bit 19Bit

Output

00 OUT6

10 OUT1

01 OUT4

11 OUT5

overvoltage

undervoltage

Thermal

shutdown

Temperature

warning

Not ready bit

In case of an overvoltage or undervoltage event the corresponding bit is set and the outputs are deactivated. If

voltage recovers to normal

operating conditions outputs are reactivated automatically (if bit 20 of status register 0 is not set).

In case of a thermal shutdown all outputs are switched off. The microcontroller has to clear the TSD bit by setting the Reset Bit to reactivate the outputs.

The TW bit can be used for thermal management by the microcontroller to avoid a thermal shutdown. The microcontroller has to clear the TW bit.

After switching the device from standby mode to active mode an internal timer is started to allow charge pump to settle before the outputs can be activated. This bit is cleared automatically after start up time has finished. Since this bit is controlled by internal clock it can be used for synchronizing testing events (e.g. measuring filter times).

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L9954LXP Functional description of the SPI

Table 18. SPI - input data and status registers 0 (continued)

Input register 0 (write) Status register 0 (read)

Bit

Name Comment Name Comment

OUT6 – HS

on/off

OUT6 – HS

over-current

16 x (don’t care) 0

OUT5 – HS

on/off

OUT4 – HS

on/off

OUT5 – HS

over-current

OUT4 – HS

over-current

If a bit is set the selected

13 x (don’t care) 0

12 x (don’t care) 0

11 x (don’t care) 0

10 x (don’t care) 0

9 x (don’t care) 0

8 x (don’t care) 0

7 x (don’t care) 0

OUT3 – HS

on/off

OUT3 – LS

on/off

output driver is switched on. If the corresponding PWM enable bit is set (input register 1) the driver is only activated if PWM1 (PWM2) input signal is high. The outputs of OUT1-OUT3 are half bridges. If the bits of HSand LS-driver of the same half bridge are set, the internal logic prevents that both drivers of this output stage can be switched on simultaneously in order to

OUT3 – HS

over-current

OUT3 – LS

over-current

avoid a high internal

OUT2 – HS

on/off

OUT2 – LS

on/off

OUT1 – HS

on/off

current from V

to GND.

OUT2 – HS

over-current

OUT2 – LS

over-current

OUT1 – HS

over-current

In case of an over-current event the corresponding status bit is set and the output driver is disabled. If the over-current recovery enable bit is set (input register 1) the output is automatically reactivated after a delay time resulting in a PWM modulated current with a programmable duty cycle (bit

21). If the over-current recovery bit is not set the microcontroller has to clear the over-current bit (reset bit) to reactivate the output driver.

OUT1 – LS

on/off

OUT1 – LS

over-current

0 0 No error bit

Doc ID 16186 Rev 2 27/35

A logical NOR-combination of all bits 1 to 22 in both status registers.

Page 28

Functional description of the SPI L9954LXP

Table 19. SPI - input data and status registers 1

Bit

Input register 1 (write) Status register 1 (read)

Name Comment Name Comment

If enable bit is set the device is switched in active mode. If enable bit is cleared device

23 Enable bit

goes into standby mode and all

Always 1 bits are cleared. After poweron reset device starts in standby mode.

OUT6 OC

recovery

overvoltage

enable

21 x (don’t care) V

OUT5 OC

recovery

enable

In case of an over-current event the over-current status bit (status register 0) is set and

undervoltage

Thermal shutdown

the output is switched off. If the over current recovery enable bit is set the output is automatically reactivated after a delay time resulting in a PWM modulated current with a programmable duty cycle (bit

Temperature

warning

OUT4 OC

recovery

enable

21 of input data register 0). Depending on occurrence of overcurrent event and internal clock phase it is possible that one recovery cycle is executed even if this bit is set to zero.

18 x (don’t care) Not ready bit

A broken V

or SPI

connection of the L9954LXP can be detected by the microcontroller, because all 24 bits low or high is not a valid frame.

In case of an overvoltage or under voltage event the corresponding bit is set and the outputs are deactivated. If V

voltage

recovers to normal operating conditions outputs are reactivated automatically.

In case of a thermal shutdown all outputs are switched off. The microcontroller has to clear the TSD bit by setting the reset bit to reactivate the outputs.

The TW bit can be used for thermal management by the microcontroller to avoid a thermal shutdown. The microcontroller has to clear the TW bit.

After switching the device from standby mode to active mode an internal timer is started to allow charge pump to settle before the outputs can be activated. This bit is only present during start up time.

Since this bit is controlled by internal clock it can be used for synchronizing testing events(e.g. measuring filter times).

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L9954LXP Functional description of the SPI

Table 19. SPI - input data and status registers 1 (continued)

Bit

Enable high

DSon

16 x (don’t care) 0

15 x (don’t care)

OUT3 OC

recovery

enable

OUT2 OC

recovery

enable

OUT1 OC

recovery

enable

OUT6 PWM1

enable

10 x (don’t care) 0

OUT5 PWM2

enable

OUT4 PWM1

enable

7 x (don’t care) 0

Enable high

DSon

5 x (don’t care)

4 x (don’t care)

OUT3 PWM1

enable

OUT2 PWM1

enable

OUT1 PWM1

enable

0 1 No error bit

Input register 1 (write) Status register 1 (read)

Name Comment Name Comment

OUT6 – HS

OUT5

open-load

OUT5 – HS

open-load

After 50ms the bit can be cleared. If over-current condition still exists, a wrong

OUT4 – HS

open-load

load can be assumed.

The open-load detection monitors the load current in each activated output

stage. If the load current is below the open-load detection threshold for at

least 1 ms (t

dOL

) the corresponding open-load bit is set. Due to

mechanical/electrical inertia of typical loads a short activation of the

OUT4

If the PWM1/2 enable bit is set and the output is enabled (input register 0) the output is switched on if PWM1/2 input is high and switched off if PWM1/2 input is low. OUT5 is controlled by PWM2 input. All other outputs are controlled by PWM1 input.

OUT3 – HS

open-load

OUT3 – LS

open-load

OUT2 –HS

open-load

outputs (e.g. 3 ms) can be used to test the openload status without changing the mechanical/electrical state of the loads.

OUT2– LS

open-load

OUT1 – HS

open-load

OUT1 – LS

open-load

A logical NORcombination of all bits 1 to 22 in both status registers.

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Packages thermal data L9954LXP

5 Packages thermal data

Figure 10. Packages thermal data

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L9954LXP Package and packing information

6 Package and packing information

6.1 ECOPACK® packages

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK specifications, grade definitions and product status are available at: www.st.com

ECOPACK

packages, depending on their level of environmental compliance. ECOPACK®

is an ST trademark.

6.2 PowerSSO-36 package information

Figure 11. PowerSSO-36 package dimensions

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Package and packing information L9954LXP

Table 20. PowerSSO-36 mechanical data

Millimeters

Symbol

Min. Typ. Max.

A 2.15 - 2.47

A2 2.15 - 2.40

a1 0 - 0.075

b 0.18 - 0.36

c 0.23 - 0.32

D 10.10 - 10.50

E7.4 - 7.6

e-0.5-

e3 - 8.5 -

G- -0.1

G1 - - 0.06

H 10.1 - 10.5

h--0.4

L 0.55 - 0.85

N - - 10 deg

X4.3 - 5.2

Y6.9 - 7.5

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L9954LXP Package and packing information

6.3 PowerSSO-36 packing information

Figure 12. PowerSSO-36 tube shipment (no suffix)

Base Qty 49

Figure 13. PowerSSO-36

tape and reel shipment (suffix “TR”)

Bulk Qty 1225 Tube length (±0.5) 532 A 3.5 B 13.8 C (±0.1) 0.6

All dimensions are in mm.

Reel dimensions

Base Qty 1000 Bulk Qty 1000 A (max) 330 B (min) 1.5 C (±0.2) 13 F 20.2 G (+2 / -0) 24.4 N (min) 100 T (max) 30.4

Tape dimensions

According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb. 1986

Tape width W 24 Tape Hole Spacing P0 (±0.1) 4 Component Spacing P 12 Hole Diameter D (±0.05) 1.55 Hole Diameter D1 (min) 1.5 Hole Position F (±0.1) 11.5 Compartment Depth K (max) 2.85 Hole Spacing P1 (±0.1) 2

All dimensions are in mm.

Top

cover

tape

End

500mm min

No componentsNo components Components

Empty components pockets sealed with cover tape.

User direction of feed

Start

500mm min

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Revision history L9954LXP

7 Revision history

Table 21. Document revision history

Date Revision Description of changes

12-Feb-2010 1 Initial release.

Table 20: PowerSSO-36 mechanical data:

– Changed X: minimum value from 4.1 to 4.3 and maximum value

17-May-2010 2

from 4.7 to 5.2

– Changed Y: minimum value from 6.5 to 6.9 and maximum value

from 7.1 to 7.5

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L9954LXP

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