Page 1
L9953LXP
Door actuator driver
Features
■ Three half bridges for 0.75A loads
(R
■ Two configurable high side driver for up to 1.5A
load (R
(R
■ One full bridge for 6A load (R
■ One highside driver for 6A load (R
■ Programmable soft start function to drive loads
with higher inrush currents (i.e. current >6A,
>1.5A)
■ Very low current consumption in standby mode
(I
■ All outputs short circuit protected
■ Current monitor output for highside OUT1,
OUT4, OUT5 and OUT8
■ All outputs over temperature protected
■ Open-load diagnostic for all outputs
■ Overload diagnostic for all outputs
■ Separated half bridges for door lock motor
■ PWM control of all outputs
■ Charge pump output for reverse polarity
protection
=1600mΩ)
DSon
=500mΩ) or 0.35A load
DSon
=1800mΩ)
on
< 6µA typ; Tj ≤ 85 °C)
S
=150mΩ)
on
on
=100mΩ)
PowerSSO-36
Applications
■ Door actuator driver with bridges for door lock,
mirror axis control, mirror fold and highside
driver for mirror defroster and two 10W-light
bulbs and/or LEDs.
Description
The L9953LXP is a microcontroller driven
multifunctional door actuator driver for automotive
applications. Up to three DC motors and three
grounded resistive loads can be driven with five
half bridges and three highside drivers. The
integrated standard serial peripheral interface
(SPI) controls all operation modes (forward,
reverse, brake and high impedance). All
diagnostic informations are available via SPI.
Table 1. Device summary
Order codes
Package
Tube Tape and reel
PowerSSO-36 L9953LXP L9953LXPTR
May 2010 Doc ID 16185 Rev 2 1/35
www.st.com
1
Page 2
Contents L9953LXP
Contents
1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2 ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.5 SPI - electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.1 Dual power supply: VS and VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.2 Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.3 Inductive loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.4 Diagnostic functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.5 Overvoltage and under voltage detection . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.6 Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.7 Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . 21
3.8 Open-load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.9 Over load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.10 Current monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.11 PWM inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.12 Cross-current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.13 Programmable soft start function to drive loads with higher inrush current
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4 Functional description of the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.1 Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.2 Chip Select Not (CSN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.3 Serial Data In (DI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.4 Serial Data Out (DO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.5 Serial clock (CLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.6 Input data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2/35 Doc ID 16185 Rev 2
Page 3
L9953LXP Contents
4.7 Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.8 SPI - input data and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5 Packages thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.1 ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.2 PowerSSO-36 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.3 PowerSSO-36 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Doc ID 16185 Rev 2 3/35
Page 4
List of tables L9953LXP
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 4. ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 5. Operating junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 6. Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 7. Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 8. Overvoltage and under voltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 9. Current monitor output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 10. Charge pump output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 11. OUT1 - OUT8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 12. Delay time from standby to active mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 13. Inputs: CSN, CLK, PWM1/2 and DI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 14. DI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 15. DO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 16. DO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 17. CSN timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 18. SPI - input data and status registers 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 19. SPI - input data and status registers 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 20. PowerSSO-36 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 21. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4/35 Doc ID 16185 Rev 2
Page 5
L9953LXP List of figures
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 3. SPI - transfer timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 4. SPI - input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 5. SPI - DO valid data delay time and valid time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 6. SPI - DO enable and disable time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 7. SPI - driver turn on / off timing, minimum CSN hi time . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 8. SPI - timing of status bit 0 (fault condition) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 9. Programmable soft start function for inductive loads and incandescent bulbs . . . . . . . . . . 23
Figure 10. Packages thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 11. PowerSSO-36 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 12. PowerSSO-36
Figure 13. PowerSSO-36 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
tube shipment (no suffix). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Doc ID 16185 Rev 2 5/35
Page 6
Block diagram and pin description L9953LXP
1 Block diagram and pin description
Figure 1. Block diagram
V
BAT
Reverse Polarity
Protection
100k
*
100µF
* Note: Value of capacitor has to be choosen carefully to li mit the VS voltage below absolute
maximum ratings in case of an unexpected freewheeling condition ( e.g. TSD, POR)
VS
10k
VCC
Charge
Pump
VCC
**
1k
**
1k
**
1k
**
1k
**
1k
DO
CLK
CSN
PWM1
DI
SPI
Interface
µC
PWM2 / CM
**
1k
** Note: Resistors between µC and L9953LXP are recommended to lim it currents
for negative voltage transients at VBAT (e.g. ISO type 1 pulse)
Table 2. Pin definitions and functions
MUX
Driver Interface & Diagnostic
GND
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
M
M
M
Mirror Common
Mirror Vertical
Mirror Horizontal
Lock / Folder
Programmable
OUT7
OUT8
4
Bulb (10W) or
LED Mode
Defroster
Pin Symbol Function
Ground:
1, 18, 19, 36 GND
reference potential.
Important: for the capability of driving the full current at the outputs all
pins of GND must be externally connected.
Highside-driver-output 8
The output is built by a highside switch and is intended for resistive
loads, hence the internal reverse diode from GND to the output is
missing. For ESD reason a diode to GND is present but the energy
2, 35 OUT8
which can be dissipated is limited. The highside driver is a power
DMOS transistor with an internal parasitic reverse diode from the
output to VS (bulk-drain-diode). The output is over-current and openload protected.
Important: for the capability of driving the full current at the outputs both
pins of OUT8 must be externally connected.
6/35 Doc ID 16185 Rev 2
Page 7
L9953LXP Block diagram and pin description
Table 2. Pin definitions and functions (continued)
Pin Symbol Function
Half-bridge-output 1,2,3
3
4
5
6, 7, 14, 15,
23, 25, 28, 32
8DI
9
10 CSN
11 DO
12 VCC
13 CLK
OUT1
OUT2
OUT3
VS
CM/PWM2
The output is built by a highside and a lowside switch, which are
internally connected. The output stage of both switches is a power
DMOS transistor. Each driver has an internal parasitic reverse diode
(bulk-drain-diode: highside driver from output to VS, lowside driver from
GND to output). This output is over-current and open-load protected.
Power supply voltage (external reverse protection required)
For this input a ceramic capacitor as close as possible to GND is
recommended.
Important: for the capability of driving the full current at the outputs all
pins of VS must be externally connected.
Serial data input
The input requires CMOS logic levels and receives serial data from the
microcontroller. The data is an 24bit control word and the least
significant bit (LSB, bit 0) is transferred first.
Current monitor output/PWM2 input
Depending on the selected multiplexer bits of input data register this
output sources an image of the instant current through the
corresponding highside driver with a ratio of 1/10.000. This pin is
bidirectional. The microcontroller can overdrive the current monitor
signal to provide a second PWM input for the output OUT7.
Chip select not input / test mode
This input is low active and requires CMOS logic levels. The serial data
transfer between L9953LXP and micro controller is enabled by pulling
the input CSN to low level. If an input voltage of more than 7.5V is
applied to CSN pin the L9953LXP will be switched into a test mode.
Serial data output
The diagnosis data is available via the SPI and this 3-state output. The
output will remain in 3-state, if the chip is not selected by the input CSN
(CSN = high)
Logic supply voltage
For this input a ceramic capacitor as close as possible to GND is
recommended.
Serial clock input
This input controls the internal shift register of the SPI and requires
CMOS logic levels.
16, 17, 20, 21
26 CP
27 PWM1
OUT4
OUT5
Half-bridge-output 4,5:
Important: for the capability of driving the full current at the outputs both
pins of OUT4 (OUT5, respectively) must be externally connected.
Charge pump output
This output is provided to drive the gate of an external n-channel
PowerMOS used for reverse polarity protection
PWM1 input:
This input signal can be used to control the drivers OUT1-OUT6 and
OUT8 by an external PWM signal.
Doc ID 16185 Rev 2 7/35
→ see OUT1 (pin 3).
Page 8
Block diagram and pin description L9953LXP
/
Table 2. Pin definitions and functions (continued)
Pin Symbol Function
Highside-driver-output 6,7:
Each output is built by a highside switch and is intended for resistive
31
33
22, 24, 29,
30, 34
OUT6,
OUT7
NC Not connected pins.
loads, hence the internal reverse diode from GND to the output is
missing. For ESD reason a diode to GND is present but the energy
which can be dissipated is limited. Each highside driver is a power
DMOS transistor with an internal parasitic reverse diode from each
output to VS (bulk-drain-diode). Each output is over-current and openload protected.
Figure 2. Configuration diagram (top view)
1
CM
GND
OUT8
OUT1
OUT2
OUT3
Vs
Vs
DI
PWM2
CSN
DO
Vcc
CLK
Vs
Vs
OUT4
OUT4
GND
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
PowerSSO-36
35
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
GND 36
OUT8
NC 34
OUT7
Vs
OUT6
NC
NC
Vs
PWM1
CP
Vs
NC
Vs
NC
OUT5
OUT5
GND
8/35 Doc ID 16185 Rev 2
Page 9
L9953LXP Electrical specifications
2 Electrical specifications
2.1 Absolute maximum ratings
Stressing the device above the rating listed in the “Absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality document
Table 3. Absolute maximum ratings
Symbol Parameter Value Unit
V
S
V
CC
V
, V
DI
DO, VCLK
V
CSN, Vpwm1
V
CM
V
CP
I
OUT1,2,3,6,7
I
OUT4,5,8
,
2.2 ESD protection
Table 4. ESD protection
All pins ± 2
Output pins: OUT1 - OUT8 ± 8
1. HBM according to MIL 883C, Method 3015.7 or EIA/JESD22-A114-A.
2. HBM with all unzapped pins grounded.
DC supply voltage -0.3 to28 V
Single pulse t
< 400ms 40 V
max
Stabilized supply voltage, logic supply -0.3 to 5.5 V
Digital input / output voltage -0.3 to V
+ 0.3 V
CC
Current monitor output -0.3 to VCC + 0.3 V
Charge pump output -25 to VS + 11 V
Output current ±5 A
Output current ±10 A
Parameter Value Unit
(1)
(2)
kV
kV
2.3 Thermal data
Table 5. Operating junction temperature
Symbol Parameter Value Unit
T
Operating junction temperature -40 to 150 °C
j
Doc ID 16185 Rev 2 9/35
Page 10
Electrical specifications L9953LXP
Table 6. Temperature warning and thermal shutdown
Symbol Parameter Min. Typ. Max. Unit
T
jTW On
T
jSD On
T
jSD Off
T
jSD Hys
Temperature warning threshold junction
temperature
Thermal shutdown threshold junction
temperature
Thermal shutdown threshold junction
temperature
Thermal shutdown hysteresis 5 °K
2.4 Electrical characteristics
VS = 8 to 16V, VCC = 4.5 to 5.3V, Tj = - 40 to 150°C, unless otherwise specified.
The voltages are referred to GND and currents are assumed positive, when the current
flows into the pin.
Table 7. S upp l y
Symbol Parameter Test condition Min. Typ. Max. Unit
V
Operating supply voltage
S
range
VS DC supply current
increasing
decreasing
V
= 16V, VCC = 5.3V
S
active mode
OUT1 - OUT8 floating
130 150 °C
T
j
Tj
Tj
150 °C
170 °C
728V
720mA
I
S
quiescent supply current
V
S
VCC DC supply current
I
CC
quiescent supply
V
CC
current
IS + I
1. Guaranteed by design.
Sum quiescent supply
CC
current
V
= 16V, VCC = 0V
S
standby mode
OUT1 - OUT8 floating
= -40°C, 25°C
T
test
= 85°C
CC ,
CC
(1)
active mode
standby mode
T
test
V
= 16V, VCC = 5.3V
S
CSN = V
= 16V, VCC = 5.3V
V
S
CSN = V
OUT1 - OUT8 floating
VS = 16V, VCC = 5.3V
CSN = V
CC
standby mode
OUT1 - OUT8 floating
= 130°C
T
test
412µA
625µA
13mA
25 50 µA
50 200 µA
10/35 Doc ID 16185 Rev 2
Page 11
L9953LXP Electrical specifications
Table 8. Overvoltage and under voltage detection
Symbol Parameter Test condition Min. Typ. Max Unit
V
SUV On
V
SUV Off
V
SUV Hyst
V
SOV Off
V
SOV On
V
SOV Hyst
V
POR Off
V
POR On
V
POR Hyst
Table 9. Current monitor output
VS UV-threshold voltage VS increasing 5.7 7.2 V
VS UV-threshold voltage VS decreasing 5.5 6.9 V
VS UV-hysteresis V
SUV On
- V
SUV Off
0.5 V
VS OV-threshold voltage VS increasing 18 24.5 V
VS OV-threshold voltage VS decreasing 17.5 23.5 V
VS OV-hysteresis V
SOV Off
- V
SOV On
1V
Power-on reset threshold VCC increasing 4.4 V
Power-on reset threshold VCC decreasing 3.1 V
Power-on reset hysteresis V
POR Off
- V
POR On
0.3 V
Symbol Parameter Test condition Min. Typ. Max. Unit
V
I
CM,r
I
CM acc
Functional voltage range VCC = 5V 0 4 V
CM
Current monitor output
ratio:
I
CM/IOUT 4,5,8
Current monitor output
ratio:
I
CM/IOUT1
Current monitor accuracy
Acc ICM/I
OUT 4,5,8
Current monitor accuracy
Acc ICM/I
OUT 1
0V ≤ V
CM
0 V ≤ V
CM
= 5V,
V
CC
I
Out,min 4,5,8
I
Out max 4,5,8
0 V ≤ V
CM
= 5V,
V
CC
I
Out,min 1
I
Out max 1
= 60mA,
≤ 4V, VCC=5V
≤ 3.8V,
= 0.5A,
= 5.9A
≤ 3.8V,
= 0.6A
1
----------------
10000
1
------------ -
4000
4% +
1%FS
8% +
2%FS
-
-
-
Table 10. Charge pump output
Symbol Parameter Test condition Min. Typ. Max. Unit
VS = 8V, I
V
I
Charge pump output
CP
voltage
Charge pump output
CP
current
V
= 10V, I
S
≥ 12V, ICP = -100µA VS+10 VS+13 V
V
S
= VS+10V, VS =13.5V 95 150 300 µA
V
CP
= -60µA VS+6 VS+13 V
CP
= -80µA VS+8 VS+13 V
CP
Doc ID 16185 Rev 2 11/35
Page 12
Electrical specifications L9953LXP
Table 11. OUT1 - OUT8
Symbol Parameter Test condition Min. Typ. Max. Unit
= 13.5 V, Tj = 25 °C,
V
R
DSon OUT1,
R
DSon OUT2
R
DSon OUT3
R
DSon OUT4,
R
DSon OUT5
On resistance to supply or
GND
On resistance to supply or
GND
S
I
OUT1,2,3
V
I
OUT1,2,3
V
I
OUT4,5
V
I
OUT4,5
= ± 0.4A
= 13.5 V, Tj = 125 °C,
S
= ± 0.4 A
= 13.5 V, Tj = 25 °C,
S
= ± 3 A
= 13.5 V, Tj = 125 °C,
S
= ± 3 A
1600 2200 mΩ
2500 3400 mΩ
150 200 mΩ
225 300 mΩ
R
DSon OUT6,
R
DSon OUT7
RDSon OUT8
I
OUT1
I
OUT2
I
OUT3
I
OUT1
I
OUT2
I
OUT3
I
OUT4
I
OUT5
I
OUT4
I
OUT5
I
OUT6
I
OUT7
On resistance to supply in
DSon
mode
low R
On resistance in high
R
mode
DSon
On resistance to supply
Output current limitation
to GND
Output current limitation
to supply
Output current limitation
to GND
Output current limitation
to supply
Output current limitation
to GND
Output current limitation
to GND in high R
DSon
mode
VS = 13.5 V, Tj = 25 °C,
I
= − 0.8A
OUT6,7
V
= 13.5 V, Tj = 125 °C,
S
I
= −0.8 A
OUT6,7
= 25 °C, I
T
j
Tj = 125 °C,I
V
= 13.5 V, Tj = 25 °C,
S
I
= -3 A
OUT8
V
= 13.5 V, Tj = 125 °C,
S
I
= -3 A
OUT8
Source, V
Sink, V
Source, V
Sink, V
S
=13.5 V 0.75 1.25 A
S
S
=13.5 V 6 10.5 A
S
= - 0.2 A 1800 2500 mΩ
OUT6,7
= - 0.2 A 2700 3700 mΩ
OUT6,7
=13.5 V -1.25 -0.75 A
=13.5 V -10.5 -6 A
Source, VS=13.5 V
500 700 mΩ
700 950 mΩ
100 150 mΩ
150 200 mΩ
-3.0 -1.4 A
-0.65 -0.35 A
12/35 Doc ID 16185 Rev 2
Page 13
L9953LXP Electrical specifications
Table 11. OUT1 - OUT8 (continued)
Symbol Parameter Test condition Min. Typ. Max. Unit
I
OUT8
t
d On H
t
d Off H
t
d On L
t
d Off L
t
d HL
t
d LH
I
QLH
I
QLL
Output current limitation
to GND
Output delay time,
highside driver on
Output delay time,
highside driver off
Output delay time,
lowside driver on
Output delay time,
lowside driver off
Cross current protection
time, source to sink
Cross current protection
time, sink to source
Switched off output
current highside drivers of
OUT1-8
Switched off output
current lowside drivers of
OUT1-5
Source, V
=13.5 V, Rload=
V
S
=13.5 V -10.5 -6 A
S
(1)
corresponding lowside driver
is not active
=13.5 V, Rload=
V
S
=13.5 V, Rload=
V
S
(1)
(1)
corresponding highside
driver is not active
V
=13.5 V, Rload=
S
t
CC ONLS_OFFHS
t
CC ONHS_OFFLS
V
V
=0V, standby mode -3 0 3 µA
OUT1-8
OUT1-2-3-4-5-8
(1)
Off H
Off L
(2)
(2)
- td
- td
=0V, active
mode
V
V
V
=0V, active mode -10 -8 0 µA
OUT6-7
= VS, standby mode 0 80 120 µA
OUT1-5
= VS, active mode -40 -15 0 µA
OUT1-5
10 40 80 µs
15 150 300 µs
15 30 70 µs
20 100 200 µs
200 400 µs
200 400 µs
-40 -15 0 µA
I
OLD123
I
OLD45
I
OLD67
I
OLD8
t
d OL
t
ISC
Open-load detection
current of OUT1, OUT2
and OUT3
Open-load detection
current of OUT4 and
OUT5
Open-load detection
current of OUT6 and
OUT7
Open-load detection
current of OUT6 and
OUT7 in high R
DSon
mode
Open-load detection
current of OUT8
Minimum duration of
open-load condition to set
the status bit
Minimum duration of overcurrent condition to switch
off the driver
Doc ID 16185 Rev 2 13/35
Source and sink 10 20 30 mA
Source and sink 60 150 300 mA
15 40 60 mA
Source
51015mA
Source 30 150 300 mA
500 3000 µs
10 100 µs
Page 14
Electrical specifications L9953LXP
Table 11. OUT1 - OUT8 (continued)
Symbol Parameter Test condition Min. Typ. Max. Unit
f
rec0
OC recovery duty cycle
2 8 kHz
bit=0
Recovery frequency for
Recovery frequency for
f
rec1
OC recovery duty cycle
316kHz
bit=1
dV
/dt
OUT123
dV
OUT67
dV
OUT45
dV
OUT8
1. OUT1,2,3 32Ohm OUT4,5 4Ohm OUT6,7 16Ohm OUT6,7 high RDSon mode 63Ohm OUT8 4Ohm
2. t
CC ON
Slew rate of OUT
OUT
/dt
/dt
/dt
is the switch On delay time t
67
Slew rate of OUT4 and
OUT5
Slew rate of OUT
and
123
8
VS =13.5 V, Rload=
=13.5 V, Rload=
V
S
VS =13.5 V, Rload=
if complement in half bridge has to switch off.
d ON
(1)
(1)
(1)
0.1 0.4 0.9 V/µs
0.08 0.2 0.4 V/µs
0.08 0.2 0.4 V/µs
14/35 Doc ID 16185 Rev 2
Page 15
L9953LXP Electrical specifications
2.5 SPI - electrical characteristics
VS = 8 to 16V, VCC = 4.5 to 5.3V, Tj = - 40 to 150°C, unless otherwise specified. The
voltages are referred to GND and currents are assumed positive, when the current flows into
the pin).
Table 12. Delay time from standby to active mode
Symbol Parameter Test condition Min. Typ. Max. Unit
t
set
Table 13. Inputs: CSN, CLK, PWM1/2 and DI
Delay time
Symbol Parameter Test condition Min. Typ. Max. Unit
V
V
V
inHyst
I
CSN in
I
CLK in
I
DI in
I
PWM1 in
C
1. Value of input capacity is not measured in production test. Parameter guaranteed by design.
Input low level VCC = 5V 1.5 2.0 V
inL
Input high level VCC = 5V 3.0 3.5 V
inH
Input hysteresis VCC = 5V 0.5 V
Pull up current at input CSN V
Pull down current at input CLK V
Pull down current at input DI VDI = 1.5V 10 25 50 µA
Pull down current at input
PWM1
Input capacitance at input
(1)
in
CSN, CLK, DI and PWM1/2
Switching from standby to active mode.
Time until output drivers are enabled
= 3.5V VCC = 5V -40 -20 -5 µA
CSN
= 1.5V 10 25 50 µA
CLK
V
= 1.5V 10 25 50 µA
PWM
0 V < V
< 5.3V 10 15 pF
CC
160 300 µs
Table 14. DI timing
(1)
Symbol Parameter Test condition Min. Typ. Max. Unit
t
CLK
t
CLKH
t
CLKL
t
set CSN
t
set CLK
t
set DI
t
hold time
t
t
1. DI timing parameters tested in production by a passed / failed test:
Tj= -40°C / +25°C: SPI communication @ 2MHz.
Tj= +125°C SPI communication @ 1.25 MHz.
Clock period VCC = 5V 1000 ns
Clock high time VCC = 5V 400 ns
Clock low time VCC = 5V 400 ns
CSN setup time, CSN low
before rising edge of CLK
CLK setup time, CLK high
before rising edge of CSN
= 5V 400 ns
V
CC
= 5V 400 ns
V
CC
DI setup time VCC = 5V 200 ns
DI hold time VCC = 5V 200 ns
Rise time of input signal DI,
r in
CLK, CSN
Fall time of input signal DI,
f in
CLK, CSN
= 5V 100 ns
V
CC
= 5V 100 ns
V
CC
Doc ID 16185 Rev 2 15/35
Page 16
Electrical specifications L9953LXP
Table 15 . DO
Symbol Parameter Test condition Min. Typ. Max. Unit
V
V
DOH
I
DOLK
C
DO
1. Value of input capacity is not measured in production test. Parameter guaranteed by design.
Table 16. DO timing
Output low level VCC = 5 V, ID = -2mA 0.2 0.4 V
DOL
Output high level VCC = 5 V, ID = 2 mA V
V
= VCC,
3-state leakage current
3-state input
(1)
capacitance
CSN
0V < V
V
CSN
0V < V
< V
DO
= VCC,
< 5.3V
CC
CC
-0.4 VCC-0.2 V
CC
-10 10 µA
10 15 pF
Symbol Parameter Test condition Min. Typ. Max. Unit
t
r DO
t
f DO
t
en DO tri L
t
dis DO L tri
t
en DO tri H
t
dis DO H tri
DO rise time CL = 100 pF, I
DO fall time CL = 100 pF, I
DO enable time
from 3-state to low level
DO disable time
from low level to 3-state
DO enable time
from 3-state to high level
DO disable time
from high level to 3-state
CL = 100 pF, I
pull-up load to V
CL = 100 pF, I
pull-up load to V
CL =100 pF, I
pull-down load to GND
CL = 100 pF, I
pull-down load to GND
= -1mA 80 140 ns
load
= 1mA 50 100 ns
load
= 1mA
load
load
load
load
CC
= 4 mA
CC
= -1mA
= -4mA
100 250 ns
380 450 ns
100 250 ns
380 450 ns
t
d DO
Table 17. CSN timing
DO delay time
< 0.3 VCC, V
DO
CL = 100pF
> 0.7VCC,
DO
50 250 ns
V
Symbol Parameter Test condition Min. Typ. Max. Unit
t
CSN_HI,stb
t
CSN_HI,min
CSN HI time, switching from
standby mode
CSN HI time, active mode
Transfer of SPI command
to input register
Transfer of SPI command
to input register
20 µs
4µs
16/35 Doc ID 16185 Rev 2
Page 17
L9953LXP Electrical specifications
Figure 3. SPI - transfer timing diagram
CSN high to low: DO enabled
CSN high to low: DO enabled
CSN high to low: DO enabled
CSN
CSN
CSN
time
time
time
01
01
CLK
CLK
CLK
DI
DI
DI
DO
DO
DO
Input
Input
Input
Data
Data
Data
Register
Register
Register
X
X
X
123456 70
123456 70
123456 70
DI: data will be accepted on the rising edge of CLK signal
DI: data will be accepted on the rising edge of CLK signal
DI: data will be accepted on the rising edge of CLK signal
123 45670
123 45670
123 45670
DO: data will change on the falling edge of CLK signal
DO: data will change on the falling edge of CLK signal
DO: data will change on the falling edge of CLK signal
123 45670
123 45670
123 45670
fault bit
fault bit
fault bit
transfered to output power switches
transfered to output power switches
transfered to output power switches
X
XX
XX
XX
XX
CSN low to high: actual data is
CSN low to high: actual data is
CSN low to high: actual data is
old data new data
old data new data
old data new data
232221201918
232221201918
232221201918
232221201918
232221201918
232221201918
01
time
time
time
0 1
0 1
0 1
time
time
time
01
01
01
time
time
time
time
time
time
Figure 4. SPI - input timing
CSN
CLK
DI
t
set C SN
t
set DI
Valid
t
CLKH
t
hold DI
t
CLKL
Va lid
t
se t CLK
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
Doc ID 16185 Rev 2 17/35
Page 18
Electrical specifications L9953LXP
t
f
f
t
t
Figure 5. SPI - DO valid data delay time and valid time
t
in
CLK
t
r DO
DO
(low to high)
t
d DO
t
DO
DO
(high to low)
Figure 6. SPI - DO enable and disable time
f in r in
CSN
r i n
0.8 VCC
0.5 VCC
0.2 VCC
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
0.8 VCC
50%
0.2 VCC
pull-up load to VCC
DO
C = 100 pF
L
DO
pull-down load to GND
C = 100 pF
L
t t
en DO tri L
t t
50%
dis DO L tri
50%
18/35 Doc ID 16185 Rev 2
Page 19
L9953LXP Electrical specifications
t
r
f
OFF
t
OFF
t
t
FFstat
t
O
p
t
e
r
t
e
r
f
rom shif
t
r
r
r
Figure 7. SPI - driver turn on / off timing, minimum CSN hi time
CSN low to high: data
is
ansf e
ed to output powerswitches
tregister
t
in
t
CSN_HI,min
CSN
d
ut curren
out
output voltage
of a driv
of a driver
output curren
output voltage
of a driv
of a driver
eO
ON sta
dON
t
N
OFF state
Figure 8. SPI - timing of status bit 0 (fault condition)
CSN high to low and CLK stays low: status information of data bit 0 (fault condition) is transfered to DO
ON sta
t
in
80%
50%
20%
80%
e
50%
20%
80%
e
50%
20%
CSN
CLK
DI
DO
DI: data is not accepted
0
-
DO: status information of data bit 0 (fault condition) will stay as long as CSN is low
time
time
time
time
Doc ID 16185 Rev 2 19/35
Page 20
Application information L9953LXP
3 Application information
3.1 Dual power supply: VS and V
The power supply voltage VS supplies the half bridges and the highside drivers. An internal
charge-pump is used to drive the highside switches. The logic supply voltage V
5 V) is used for the logic part and the SPI of the device.
Due to the independent logic supply voltage the control and status information will not be
lost, if there are temporary spikes or glitches on the power supply voltage. In case of poweron (V
internally generated power-on-reset (POR). If the voltage V
minimum threshold (V
and the status registers are cleared.
increases from under voltage to V
CC
POR ON
= 3.4 V), the outputs are switched to 3-state (high impedance)
3.2 Standby mode
The standby mode of the L9953LXP is activated by clearing the bit 23 of the input data
register 0. All latched data will be cleared and the inputs and outputs are switched to high
impedance. In the standby mode the current at V
CSN = high (DO in 3-state). By switching the V
be achieved. If bit 23 is set, the device will be switched to active mode.
3.3 Inductive loads
Each half bridge is built by an internally connected highside and a lowside power DMOS
transistor. Due to the built-in reverse diodes of the output transistors, inductive loads can be
driven at the outputs OUT1 to OUT5 without external free-wheeling diodes. The highside
drivers OUT6 to OUT8 are intended to drive resistive loads. Hence only a limited energy
(E<1mJ) can be dissipated by the internal ESD diodes in freewheeling condition. For
inductive loads (L>100µH) an external free-wheeling diode connected to GND and the
corresponding output is needed.
CC
POR Off
CC
(stabilized
CC
= 4.2 V) the circuit is initialized by an
decreases under the
CC
(VCC) is less than 6 µA (50µA) for
S
voltage a very low quiescent current can
3.4 Diagnostic functions
All diagnostic functions (over/open-load, power supply over-/under voltage, temperature
warning and thermal shutdown) are internally filtered and the condition has to be valid for at
least 32 µs (open-load: 1ms, respectively) before the corresponding status bit in the status
registers will be set. The filters are used to improve the noise immunity of the device. Openload and temperature warning function are intended for information purpose and will not
change the state of the output drivers. On contrary, the overload condition will disable the
corresponding driver (over-current) and overtemperature will switch off all drivers (thermal
shutdown). Without setting the over-current recovery bits in the input data register, the
microcontroller has to clear the over-current status bits to reactivate the corresponding
drivers.
20/35 Doc ID 16185 Rev 2
Page 21
L9953LXP Application information
3.5 Overvoltage and under voltage detection
If the power supply voltage VS rises above the overvoltage threshold V
the outputs OUT1 to OUT8 are switched to high impedance state to protect the load. When
the voltage V
output stages are switched to the high impedance to avoid the operation of the power
devices without sufficient gate driving voltage (increased power dissipation). If the supply
voltage V
programmed state (input register 0: bit 20=0).
If the under voltage/overvoltage recovery disable bit is set, the automatic turn-On of the
drivers is deactivated. The microcontroller needs to clear the status bits to reactivate the
drivers. It is recommended to set bit 20 to avoid a possible high current oscillation in case of
a shorted output to GND and low battery voltage.
drops below the under voltage threshold V
S
recovers to normal operating voltage the outputs stages return to the
S
(UV-switch-Off voltage), the
SUV Off
3.6 Charge pump
The charge pump runs under all conditions in normal mode. In standby the charge pump is
disabled.
3.7 Temperature warning and thermal shutdown
If junction temperature rises above T
via the SPI. If junction temperature increases above the second threshold T
shutdown bit will be set and power DMOS transistors of all output stages are switched Off to
protect the device. Temperature warning flag and thermal shutdown bit are latched and must
be cleared by the microcontroller. The related bit is only cleared if the temperature
decreases below the trigger temperature. If the thermal shutdown bit has been cleared the
output stages are reactivated.
a temperature warning flag is set and is detectable
j TW
SOV Off
j SD
(typical 21 V),
, the thermal
3.8 Open-load detection
The open-load detection monitors the load current in each activated output stage. If the load
current is below the open-load detection threshold for at least 1 ms (t
open-load bit is set in the status register. Due to mechanical/electrical inertia of typical loads
a short activation of the outputs (e.g. 3ms) can be used to test the open-load status without
changing the mechanical/electrical state of the loads.
3.9 Over load detection
In case of an over-current condition a flag is set in the status register in the same way as
open-load detection. If the over-current signal is valid for at least t
current flag is set and the corresponding driver is switched off to reduce the power
dissipation and to protect the integrated circuit. If the over-current recovery bit of the output
is zero the microcontroller has to clear the status bits to reactivate the corresponding driver.
) the corresponding
dOL
= 32 µs, the over-
ISC
Doc ID 16185 Rev 2 21/35
Page 22
Application information L9953LXP
3.10 Current monitor
The current monitor output sources a current image at the current monitor output which has
a fixed ratio (1/10000) of the instantaneous current of the selected highside driver. The bits
18 and 19 of the input data register 0 control which of the outputs OUT1, OUT4, OUT5, and
OUT8 will be multiplexed to the current monitor output. The current monitor output allows a
more precise analysis of the actual state of the load rather than the detection of an open- or
overload condition. For example this can be used to detect the motor state (starting, freerunning, stalled). Moreover, it is possible to regulate the power of the defroster more precise
by measuring the load current. The current monitor output is bidirectional (c.f. PWM inputs).
3.11 PWM inputs
Each driver has a corresponding PWM enable bit which can be programmed by the SPI
interface. If the PWM enable bit in input data register 1 is set, the output is controlled by the
logically AND-combination of the PWM signal and the output control bit in input data
register 0. The outputs OUT1-OUT6 and OUT8 are controlled by the PWM1 input and the
output OUT7 is controlled by the bidirectional input CM/PMW2. For example, the two PWM
inputs can be used to dim two lamps independently by external PWM signals.
3.12 Cross-current protection
The six half-bridges of the device are cross-current protected by an internal delay time. If
one driver (LS or HS) is turned-off the activation of the other driver of the same half bridge
will be automatically delayed by the cross-current protection time. After the cross-current
protection time is expired the slew-rate limited switch-off phase of the driver will be changed
to a fast turn-off phase and the opposite driver is turned-on with slew-rate limitation. Due to
this behavior it is always guaranteed that the previously activated driver is totally turned-off
before the opposite driver will start to conduct.
22/35 Doc ID 16185 Rev 2
Page 23
L9953LXP Application information
3.13 Programmable soft start function to drive loads with higher inrush current
Loads with start-up currents higher than the over-current limits (e.g. inrush current of lamps,
start current of motors and cold resistance of heaters) can be driven by using the
programmable soft start function (i.e. overcurrent recovery mode). Each driver has a
corresponding over-current recovery bit. If this bit is set, the device will automatically switchon the outputs again after a programmable recovery time. The duty cycle in over-current
condition can be programmed by the SPI interface to be about 12% or 25%. The PWM
modulated current will provide sufficient average current to power up the load (e.g. heat up
the bulb) until the load reaches operating condition. The PWM frequency settles at 3kHz or
6kHz. The device itself cannot distinguish between a real overload and a non linear load like
a light bulb. A real overload condition can only be qualified by time. As an example the
microcontroller can switch on light bulbs by setting the over-current recovery bit for the first
50ms. After clearing the recovery bit the output will be automatically disabled if the overload
condition still exits.
Figure 9. Programmable soft start function for inductive loads and incandescent
Load Current
Overcurrent
detection
bulbs
Unlimited Inrush Current
Limited Inrush Current in
overcurren t recovery mode
with inductive load
Load Current
Overcurrent
detection
Unlimited Inrush Cu rrent
Limited Inrush Current in
overcurrent recovery mode with
incandescent bulb
t
t
Doc ID 16185 Rev 2 23/35
Page 24
Functional description of the SPI L9953LXP
4 Functional description of the SPI
4.1 Serial Peripheral Interface (SPI)
This device uses a standard SPI to communicate with a microcontroller. The SPI can be
driven by a microcontroller with its SPI peripheral running in following mode: CPOL = 0 and
CPHA = 0.
For this mode, input data is sampled by the low to high transition of the clock CLK, and
output data is changed from the high to low transition of CLK.
This device is not limited to microcontroller with a build-in SPI. Only three CMOS-compatible
output pins and one input pin will be needed to communicate with the device. A fault
condition can be detected by setting CSN to low. If CSN = 0, the DO-pin will reflect the
status bit 0 (fault condition) of the device which is a logical-or of all bits in the status registers
0 and 1. The microcontroller can poll the status of the device without the need of a full SPIcommunication cycle.
Note: In contrast to the SPI-standard the least significant bit (LSB) will be transferred first (see
Figure 3).
4.2 Chip Select Not (CSN)
The input pin is used to select the serial interface of this device. When CSN is high, the
output pin (DO) will be in high impedance state. A low signal will activate the output driver
and a serial communication can be started. The state when CSN is going low until the rising
edge of CSN will be called a communication frame. If the CSN-input pin is driven above
7.5V, the L9953LXP will go into a test mode. In the test mode the DO will go from 3-state to
active mode.
4.3 Serial Data In (DI)
The input pin is used to transfer data serial into the device. The data applied to the DI will be
sampled at the rising edge of the CLK signal and shifted into an internal 24 bit shift register.
At the rising edge of the CSN signal the contents of the shift register will be transferred to
data input register. The writing to the selected data input register is only enabled if exactly
24 bits are transmitted within one communication frame (i.e. CSN low). If more or less clock
pulses are counted within one frame the complete frame will be ignored. This safety function
is implemented to avoid an activation of the output stages by a wrong communication frame.
Note: Due to this safety functionality a daisy chaining of SPI is not possible. Instead, a parallel
operation of the SPI bus by controlling the CSN signal of the connected ICs is
recommended.
4.4 Serial Data Out (DO)
The data output driver is activated by a logical low level at the CSN input and will go from
high impedance to a low or high level depending on the status bit 0 (fault condition). The first
rising edge of the CLK input after a high to low transition of the CSN pin will transfer the
24/35 Doc ID 16185 Rev 2
Page 25
L9953LXP Functional description of the SPI
content of the selected status register into the data out shift register. Each subsequent
falling edge of the CLK will shift the next bit out.
4.5 Serial clock (CLK)
The CLK input is used to synchronize the input and output serial bit streams. The data input
(DI) is sampled at the rising edge of the CLK and the data output (DO) will change with the
falling edge of the CLK signal.
4.6 Input data register
The device has two input registers. The first bit (bit 0) at the DI-input is used to select one of
the two Input Registers. All bits are first shifted into an input shift register. After the rising
edge of CSN the contents of the input shift register will be written to the selected Input Data
Register only if a frame of exact 24 data bits are detected. Depending on bit 0 the contents
of the selected status register will be transferred to DO during the current communication
frame. Bit 1-17 controls the behavior of the corresponding driver.
If bit 23 is zero, the device will go into the standby-mode. The bits 18 and 19 are used to
control the current monitor multiplexer. Bit 22 is used to reset all status bits in both status
registers. The bits in the status registers will be cleared after the current communication
frame (rising edge of CSN).
4.7 Status register
This devices uses two status registers to store and to monitor the state of the device. Bit 0 is
used as a fault bit and is a logical-NOR combination of bits 1-22 in both status registers. The
state of this bit can be polled by the microcontroller without the need of a full SPI
communication cycle. If one of the over-current bits is set, the corresponding driver will be
disabled. If the over-current recovery bit of the output is not set the microcontroller has to
clear the over-current bit to enable the driver. If the thermal shutdown bit is set, all drivers
will go into a high impedance state. Again the microcontroller has to clear the bit to enable
the drivers.
Doc ID 16185 Rev 2 25/35
Page 26
Functional description of the SPI L9953LXP
4.8 SPI - input data and status registers
Table 18. SPI - input data and status registers 0
Input register 0 (write) Status register 0 (read)
Bit
Name Comment Name Comment
If enable bit is set the
23 Enable bit
device will be switched in
active mode. If enable bit
is cleared the device go
into standby mode and all
bits are cleared. After
power-on reset device
starts in standby mode.
Always 1
A broken VCC-or SPIconnection of the L9953LXP
can be detected by the
microcontroller, because all 24
bits low or high is not a valid
frame.
22 Reset bit
OC recovery
duty cycle
21
0: 12% 1: 25%
Overvoltage/
undervoltage
20
recovery
disable
19
Current monitor
select bits
18
If reset bit is set both
status registers will be
cleared after rising edge of
CSN input.
This bit defines in
combination with the overcurrent recovery bit (Input
register 1) the duty cycle
in over current condition of
an activated driver.
If this bit is set the
microcontroller has to
clear the status register
after
undervoltage/overvoltage
event to enable the
outputs.
Depending on
combination of bit 18 and
19 the current image
(1/10.000) of the selected
HS-output will be multiplexed to the CM output:
Bit 19Bit
18
Output
00 OUT8
10 OUT1
01 OUT5
11 OUT4
overvoltage
V
S
undervoltage
V
S
Thermal
shutdown
Temperature
warning
Not ready bit
In case of an overvoltage or
undervoltage event the
corresponding bit is set and
the outputs are deactivated. If
VS voltage recovers to normal
operating conditions outputs
are reactivated automatically
(if Bit 20 of status register 0 is
not set).
In case of a thermal shutdown
all outputs are switched off.
The microcontroller has to
clear the TSD bit by setting the
reset bit to reactivate the
outputs.
This TW bit is for information
purpose only. It can be used
for a thermal management by
the microcontroller to avoid a
thermal shutdown.
After switching the device from
standby mode to active mode
an internal timer is started to
allow charge pump to settle
before the outputs can be
activated. This bit is cleared
automatically after start up
time has finished. Since this bit
is controlled by internal clock it
can be used for synchronizing
testing events (e.g. measuring
filter times).
26/35 Doc ID 16185 Rev 2
Page 27
L9953LXP Functional description of the SPI
Table 18. SPI - input data and status registers 0 (continued)
Input register 0 (write) Status register 0 (read)
Bit
Name Comment Name Comment
17
OUT8 – HS
on/off
OUT8 – HS
over-current
16 x (don’t care) 0
15
14
OUT7 – HS
on/off
OUT6 – HS
on/off
OUT7 – HS
over-current
OUT6 – HS
over-current
13 x (don’t care) 0
12 x (don’t care) 0
11 x (don’t care)
OUT5 – HS
10
9
8
7
6
5
4
on/off
OUT5 – LS
on/off
OUT4 – HS
on/off
OUT4 – LS
on/off
OUT3 – HS
on/off
OUT3 – LS
on/off
OUT2 – HS
on/off
If a bit is set the selected
output driver is switched
On. If the corresponding
PWM enable bit is set
(input register 1) the driver
is only activated if PWM1
(PWM2) input signal is
high. The outputs of
OUT1-OUT5 are half
bridges. If the bits of HSand LS-driver of the same
half bridge are set, the
internal logic prevents that
both drivers of this output
stage can be switched on
simultaneously in order to
avoid a high internal
current from VS to GND.
OUT5 – HS
over-current
OUT5 – LS
over-current
OUT4 – HS
over-current
OUT4 – LS
over-current
OUT3 – HS
over-current
OUT3 – LS
over-current
OUT2 – HS
over-current
In case of an over-current
event the corresponding status
bit is set and the output driver
is disabled. If the over-current
recovery enable bit is set
(input register 1) the output will
be automatically reactivated
after a delay time resulting in a
PWM modulated current with a
programmable duty cycle (bit
21).
If the over-current recovery bit
is not set the microcontroller
has to clear the over-current
bit (reset bit) to reactivate the
output driver.
3
2
1
OUT2 – LS
on/off
OUT1 – HS
on/off
OUT1 – LS
on/off
OUT2 – LS
over-current
OUT1 – HS
over-current
OUT1 – LS
over-current
0 0 No error bit
Doc ID 16185 Rev 2 27/35
A logical NOR-combination of
all bits 1 to 22 in both status
registers.
Page 28
Functional description of the SPI L9953LXP
Table 19. SPI - input data and status registers 1
Bit
Name Comment Name Comment
Input register 1 (write) Status register 1 (read)
If enable bit is set the device
will be switched in active mode.
If enable bit is cleared device
23 Enable bit
goes into standby mode and all
Always 1
bits are cleared. After poweron reset device starts in
standby mode.
OUT8 OC
22
recovery
VS overvoltage
enable
21 0 / 1 VS undervoltage
20
OUT7 OC
recovery
enable
In case of an over-current
event the over-current status
bit (status register 0) is set and
Thermal shutdown
the output is switched off. If the
over-current recovery enable
bit is set the output will be
automatically reactivated after
a delay time resulting in a
PWM modulated current with a
programmable duty cycle (bit
Temperature
warning
19
OUT6 OC
recovery
enable
21 of input data register 0).
Depending on occurrence of
over-current event and internal
clock phase it is possible that
one recovery cycle is executed
even if this bit is set to zero.
18 0 / 1 Not ready bit
A broken VCC or SPI
connection of the
L9953LXP can be
detected by the
microcontroller, because
all 24 bits low or high is
not a valid frame.
In case of an overvoltage
or under voltage event
the corresponding bit is
set and the outputs are
deactivated. If Vs voltage
recovers to normal
operating conditions
outputs are reactivated
automatically.
In case of a thermal
shutdown all outputs are
switched off. The
microcontroller has to
clear the TSD bit by
setting the reset bit to
reactivate the outputs.
The TW bit can be used
for thermal management
by the microcontroller to
avoid a thermal
shutdown. The
microcontroller has to
clear the TW bit.
After switching the
device from standby
mode to active mode an
internal timer is started
to allow charge pump to
settle before the outputs
can be activated. This bit
is only present during
start up time
Since this bit is
controlled by internal
clock it can be used for
synchronizing testing
events(e.g. measuring
filter times).
28/35 Doc ID 16185 Rev 2
Page 29
L9953LXP Functional description of the SPI
Table 19. SPI - input data and status registers 1 (continued)
Bit
Name Comment Name Comment
Enable high
17
R
DSon
OUT5 OC
16
recovery
enable
OUT4 OC
15
recovery
enable
OUT3 OC
14
recovery
enable
OUT2 OC
13
recovery
enable
OUT1 OC
12
recovery
enable
OUT8 PWM1
11
enable
10 0 / 1
OUT7 PWM2
9
8
enable
OUT6 PWM1
enable
7
Enable high
6
R
DSon
OUT5 PWM1
5
4
3
2
1
enable
OUT4 PWM1
enable
OUT3 PWM1
enable
OUT2 PWM1
enable
OUT1 PWM1
enable
0 1 No error bit
Input register 1 (write) Status register 1 (read)
OUT8 – HS
OUT7
open-load
0
OUT7 – HS
After 50ms the bit can be
open-load
cleared. If over-current
condition still exists, a wrong
load can be assumed.
OUT6 – HS
open-load
0
The open-load detection
monitors the load current
0
in each activated output
stage. If the load current
is below the open-load
detection threshold for at
least 1 ms (t
corresponding open-load
bit is set. Due to
mechanical/electrical
inertia of typical loads a
short activation of the
outputs (e.g. 3ms) can
be used to test the openload status without
changing the
mechanical/electrical
state of the loads.
OUT6
If the PWM1/2 enable bit is set
and the output is enabled
(input register 0) the output is
switched On if PWM1/2 input is
high and switched off if
PWM1/2 input is low. OUT7 is
controlled by PWM2 input. All
other outputs are controlled by
PWM1 input.
0
OUT5 – HS
open-load
OUT5 – LS
open-load
OUT4 – HS
open-load
OUT4 – LS
open-load
OUT3 – HS
open-load
OUT3 – LS
open-load
OUT2 –HS
open-load
OUT2– LS
open-load
OUT1 – HS
open-load
OUT1 – LS
open-load
A logical NORcombination of all bits 1
to 22 in both status
registers.
dOL
) the
Doc ID 16185 Rev 2 29/35
Page 30
Packages thermal data L9953LXP
5 Packages thermal data
Figure 10. Packages thermal data
30/35 Doc ID 16185 Rev 2
Page 31
L9953LXP Package and packing information
6 Package and packing information
6.1 ECOPACK® packages
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
specifications, grade definitions and product status are available at: www.st.com
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK®
®
is an ST trademark.
6.2 PowerSSO-36 package information
Figure 11. PowerSSO-36 package dimensions
.
Doc ID 16185 Rev 2 31/35
Page 32
Package and packing information L9953LXP
Table 20. PowerSSO-36 mechanical data
Symbol
Min. Typ. Max.
A 2.15 - 2.47
A2 2.15 - 2.40
a1 0 - 0.075
b 0.18 - 0.36
c 0.23 - 0.32
D 10.10 - 10.50
E7.4 - 7.6
e-0.5-
e3 - 8.5 -
G- -0.1
G1 - - 0.06
Millimeters
H 10.1 - 10.5
h--0.4
L 0.55 - 0.85
N - - 10 deg
X4.3 - 5.2
Y6.9 - 7.5
32/35 Doc ID 16185 Rev 2
Page 33
L9953LXP Package and packing information
6.3 PowerSSO-36 packing information
Figure 12. PowerSSO-36 tube shipment (no suffix)
Base Qty 49
C
B
A
Figure 13. PowerSSO-36 tape and reel shipment (suffix “TR”)
Bulk Qty 1225
Tube length (±0.5) 532
A 3.5
B 13.8
C (±0.1) 0.6
All dimensions are in mm.
Reel dimensions
Base Qty 1000
Bulk Qty 1000
A (max) 330
B (min) 1.5
C (±0.2) 13
F 20.2
G (+2 / -0) 24.4
N (min) 100
T (max) 30.4
Tape dimensions
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
Tape width W 24
Tape Hole Spacing P0 (±0.1) 4
Component Spacing P 12
Hole Diameter D (±0.05) 1.55
Hole Diameter D1 (min) 1.5
Hole Position F (±0.1) 11.5
Compartment Depth K (max) 2.85
Hole Spacing P1 (±0.1) 2
All dimensions are in mm.
Top
cover
tape
End
500mm min
No componentsNo components Components
Empty components pockets
sealed with cover tape.
User direction of feed
Start
500mm min
Doc ID 16185 Rev 2 33/35
Page 34
Revision history L9953LXP
7 Revision history
Table 21. Document revision history
Date Revision Description of changes
31-Aug-2009 1 Initial release.
Table 20: PowerSSO-36 mechanical data:
– Changed X: minimum value from 4.1 to 4.3 and
14-May-2010 2
maximum value from 4.7 to 5.2
– Changed Y: minimum value from 6.5 to 6.9 and
maximum value from 7.1 to 7.5
34/35 Doc ID 16185 Rev 2
Page 35
L9953LXP
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