Datasheet L9951, L9951XP Datasheet (ST)

L9951

L9951XP

Rear door actuator driver

Features

Type Ou tputs

(1)

OUT1

L9951

L9951XP

OUT2
OUT3
OUT4
OUT5

1. See block diagram.

2. Typical values.

■ One half bridge for 7.4 A load (R

■ Two half bridges for 5 A load (R

■ Two highside drivers for 1.25 A load

(R

=800 mΩ)

on

■ Programmable softstart function to drive loads

with higher inrush currents (i.e.current > 7.4A,
>5A, >1.25A)

■ Very low current consumption in standby mode

(I

< 3µA, typ. Tj ≤ 85°C)

S

■ All outputs short circuit protected

■ Current monitor output for all highside drivers

■ All outputs over temperature protected

■ Open-load diagnostic for all outputs

■ Overload diagnostic for all outputs

■ Programmable PWM control of all outputs

■ Charge pump output for reverse polarity

protection

Table 1. Device summary

(2)

R

on

150 mΩ
200 mΩ
200 mΩ
800 mΩ
800 mΩ

I

OUT

7.4 A
5A
5A

1.25 A

1.25 A

= 150 mΩ)

on

= 200 mΩ)

on

V

S

28 V

PowerSO-36

PowerSSO-36

Applications

■ Rear door actuator driver with bridges for door

lock and safe lock and two 5W or 10W - light
bulbs.

Description

The L9951 and L9951XP are microcontroller
driven, multifunctional rear door actuator drivers
for automotive applications. Up to two DC motors
and two grounded resistive loads can be driven
with three half bridges and two hide side drivers.
The integrated standard serial peripheral interface
(SPI) controls all operation modes (forward,
reverse, brake and high impedance). All
diagnostic information is available via the SPI.

Order codes

Package

Tube Tape and reel

PowerSO-36 L9951 L9951TR

PowerSSO-36 L9951XP L9951XPTR

May 2010 Doc ID 14173 Rev 8 1/36

www.st.com

1

Contents L9951 / L9951XP

Contents

1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.2 ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.4 Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . 10

2.5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.6 SPI - electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.1 Dual power supply: VS and VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.2 Standby - mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.3 Inductive loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.4 Diagnostic functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.5 Over-voltage and under-voltage detection . . . . . . . . . . . . . . . . . . . . . . . . 20

3.6 Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . 20

3.7 Open-load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.8 Over load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.9 Current monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.10 PWM input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.11 Cross-current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.12 Programmable softstart function to drive loads with higher inrush current 21

4 Functional description of the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.1 Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.2 Chip Select Not (CSN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.3 Serial Data In (DI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.4 Serial Data Out (DO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.5 Serial clock (CLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.6 Input data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.7 Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2/36 Doc ID 14173 Rev 8

L9951 / L9951XP Contents

4.8 Test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5 Packages thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.1 ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.2 PowerSO-36™ package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.3 PowerSSO-36™ package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6.4 PowerSO-36™ packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

6.5 PowerSSO-36™ packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Doc ID 14173 Rev 8 3/36

List of tables L9951 / L9951XP

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 4. ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 5. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 6. Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 7. Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 8. Overvoltage and undervoltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 9. Current monitor output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 10. Charge pump output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 11. OUT 1 - OUT 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 12. Delay time from standby to active mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 13. Inputs: CSN, CLK, PWM1/2 and DI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 14. DI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 15. DO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 16. DO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 17. EN, CSN timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 18. Test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 19. SPI - Input data and status register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 20. SPI - Input data and status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 21. PowerSO-36™ mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 22. PowerSSO-36™ mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 23. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

4/36 Doc ID 14173 Rev 8

L9951 / L9951XP List of figures

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2. Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 3. SPI - transfer timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 4. SPI - input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 5. SPI - DO valid data delay time and valid time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 6. SPI - DO enable and disable time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 7. SPI - driver turn-on/off timing, minimum CSN HI time . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 8. SPI - timing of status bit 0 (fault condition) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 9. Example of programmable softstart function for inductive loads . . . . . . . . . . . . . . . . . . . . 21

Figure 10. Packages thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 11. PowerSO-36™ package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 12. PowerSSO-36™ package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 13. PowerSO-36
Figure 14. PowerSO-36
Figure 15. PowerSSO-36
Figure 16. PowerSSO-36

TM

tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

TM

tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

TM

tube shipment (no suffix). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

TM

tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Doc ID 14173 Rev 8 5/36

Block diagram and pin description L9951 / L9951XP

1 Block diagram and pin description

Figure 1. Block diagram

V

* Note: Value of capacitor has to be choosen carefully to limit the VS
voltage below absolute maximum ratings in case of an unexpected

freewheeling condition of inductive loads (e.g. TSD, POR)

Reverse

Polarity

Protection

100k

BAT

VREG

VCC

µC

*

100µF

100nF

EMC

Optimization

100 10

100nF

**

1k

**

1k

**

1k

**

1k

**

1k

CM / PWM

**

1k

VS

Charge

DO

Pump

VCC

DI

+

CLK
CSN

EN

10k

CP

OUT1

OUT2

Lock

M

Safe Lock

OUT3

SPI

Interface

OUT4

OUT5

M

Exterior Light

Driver Interface & Diagnostic

Safety Light

MUX

GND

5

** Note: Resistors between µC and L9951 are recommended to limit currents
for negative voltage transients at VBAT (e.g. ISO type 1 pulse)

+ Note: Using a ferrite instead of 10ohm will additionally improve EMC behavior

6/36 Doc ID 14173 Rev 8

L9951 / L9951XP Block diagram and pin description

Table 2. Pin definitions and functions

Pin Symbol Function

Ground .

1, 18, 19,

36

GND

6, 7, 14,

15, 23, 24,

VS

29, 32

3, 4, 34 OUT1

8DI

9CM/PWM

Reference potential.
Note: For the capability of driving the full current at the outputs all pins of

GND must be externally connected.

Power supply voltage (external reverse protection required).
For EMI reason a ceramic capacitor as close as possible to GND is

recommended.
Note: for the capability of driving the full current at the outputs all pins of

VS must be externally connected.

Half-bridge output 1.
The output is built by a high side and a low side switch, which are

internally connected. The output stage of both switches is a power
DMOS transistor. Each driver has an internal reverse diode (bulk-drain­diode: high side driver from output to VS, low side driver from GND to
output). This output is over-current and open-load protected.

Note: for the capability of driving the full current at the outputs all pins of
OUT1 must be externally connected.

Serial data input.
The input requires CMOS logic levels and receives serial data from the

microcontroller. The data is a 16bit control word and the least significant
bit (LSB, bit 0) is transferred first.

Current monitor output/PWM input.
Depending on the selected multiplexer bits (bit 9, 10, 11) of Input Data

Register this output sources an image of the instant current through the
corresponding high side driver with a ratio of 1/10.000. This pin is
bidirectional. The microcontroller can overwrite the current monitor signal
to provide a PWM input for all outputs.

Testmode:
If CSN is raised above 7.5V the device will enter the test mode. In test

mode this output can be used to measure some internal signals (see

Ta bl e 1 8 ).

Chip select not input / Testmode .
This input is low active and requires CMOS logic levels. The serial data

10 CSN

transfer between L9951 and micro controller is enabled by pulling the
input CSN to low level. If an input voltage of more than 7.5V is applied to
CSN pin the L9951 will be switched into a test mode.

Serial data output .

11 DO

The diagnosis data is available via the SPI and this tristate-output. The
output will remain in tristate, if the chip is not selected by the input CSN
(CSN = high).

Logic supply voltage .

12

VCC

For this input a ceramic capacitor as close as possible to GND is
recommended.

Serial clock input .

13

CLK

This input controls the internal shift register of the SPI and requires
CMOS logic levels.

Doc ID 14173 Rev 8 7/36

Block diagram and pin description L9951 / L9951XP

Table 2. Pin definitions and functions (continued)

Pin Symbol Function

Half-bridge output 2 (see OUT1 - pin 3, 4).

16, 17

20, 21 OUT3

26

27

33, 35 OUT4, OUT5

OUT2

CP

EN

Note: for the capability of driving the full current at the outputs all pins of
OUT2 must be externally connected.

Half-bridge output 3 (see OUT1 - pin 3, 4).
Note: for the capability of driving the full current at the outputs all pins of

OUT3 must be externally connected.

Charge Pump Output .
This output is provided to drive the gate of an external n-channel power

MOS used for reverse polarity protection (see Figure 1).

Enable input.
If Enable input is forced to GND the device will enter Standby-Mode. The

outputs will be switched off and all registers will be cleared

High side driver output 4, 5 .
The output is built by a high side switch and is intended for resistive

loads, hence the internal reverse diode from GND to the output is
missing. For ESD reason a diode to GND is present but the energy which
can be dissipated is limited. The high side driver is a power DMOS
transistor with an internal reverse diode from the output to VS (bulk­drain-diode). The output is over-current and open-load protected.

Figure 2. Configuration diagram (top view)

1

1

1

1

GND

GND

GND

GND

N.C.

N.C.

N.C.

N.C.

OUT1

OUT1

OUT1

OUT1

OUT1

OUT1

OUT1

OUT1

N.C.

N.C.

N.C.

N.C.

VS

VS

VS

VS

VS

VS

VS

VS

DI

DI

DI

DI

CM/PWM

CM/PWM

CM/PWM

CM/PWM

CSN

CSN

CSN

CSN

DO

DO

DO

DO

VCC

VCC

VCC

VCC

CLK

CLK

CLK

CLK

VS

VS

VS

VS

VS

VS

VS

VS

OUT2

OUT2

OUT2

OUT2

OUT2

OUT2

OUT2

OUT2

GND

GND

GND

GND

1

2

2

2

2

2

3

3

3

3

3

4

4

4

4

4

5

5

5

5

5

6

6

6

6

6

7

7

7

7

7

8

8

8

8

8

9

9

9

9

9

10

10

10

10

10

11

11

11

11

11

12

12

12

12

12

13

13

13

13

13

14

14

14

14

14

15

15

15

15

15

16

16

16

16

16

17

17

17

17

17

18

18

18

18

18

Chip

Chip

Chip

Chip

Leadframe

Leadframe

Leadframe

Leadframe

36

36

36

36

36

35

35

35

35

35

34

34

34

34

34

33

33

33

33

33

32

32

32

32

32

31

31

31

31

31

30

30

30

30

30

29

29

29

29

29

28

28

28

28

28

27

27

27

27

27

26

26

26

26

26

25

25

25

25

24

24

24

24

23

23

23

23

22

22

22

22

21

21

21

21

20

20

20

20

19

19

19

19

GND

GND

GND

GND

OUT5

OUT5

OUT5

OUT5

OUT1

OUT1

OUT1

OUT1

OUT4

OUT4

OUT4

OUT4

VS

VS

VS

VS

N.C.

N.C.

N.C.

N.C.

N.C.

N.C.

N.C.

N.C.

VS

VS

VS

VS

N.C.

N.C.

N.C.

N.C.

EN

EN

EN

EN

CP

CP

CP

CP

N.C.

N.C.

N.C.

N.C.

VS

VS

VS

VS

VS

VS

VS

VS

N.C.

N.C.

N.C.

N.C.

OUT3

OUT3

OUT3

OUT3

OUT3

OUT3

OUT3

OUT3

GND

GND

GND

GND

.

.

.

.

8/36 Doc ID 14173 Rev 8

L9951 / L9951XP Electrical specifications

2 Electrical specifications

2.1 Absolute maximum ratings

Stressing the device above the rating listed in the “Absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics sure
program and other relevant quality document

Table 3. Absolute maximum ratings

Symbol Parameter Value Unit

V

S

V

CC

V

DI,VDO,VCLK,VCSN,VEN

V

CM

V

CP

I

OUT1,2,3

I

OUT4,5

2.2 ESD protection

Table 4. ESD protection

Output pins: OUT1 - OUT5 ± 8

1. HBM according to CDF-AEC-Q100-002.

2. HBM with all unzapped pins grounded.

DC supply voltage -0.3 to 28 V

Single pulse t

< 400ms 40 V

max

Stabilized supply voltage, logic supply -0.3 to 5.5 V

Digital input / output voltage -0.3 to V

+ 0.3 V

CC

Current monitor output -0.3 to VCC + 0.3 V

Charge pump output -25 to VS + 11 V

Output current ±10 A

Output current ±5 A

Parameter Value Unit

All pins ± 4

(1)

(2)

kV

kV

2.3 Thermal data

Table 5. Thermal data

Symbol Parameter Value Unit

T

j

Operating junction temperature -40 to 150 °C

Doc ID 14173 Rev 8 9/36

Electrical specifications L9951 / L9951XP

2.4 Temperature warning and thermal shutdown

Table 6. Temperature warning and thermal shutdown

Symbol Parameter Min. Typ. Max. Unit

T

jTW ON

T

jTW OFF

T

jTW HYS

T

jSD ON

T

jSD OFF

T

jSD HYS

Temperature warning threshold junction
temperature

Temperature warning threshold junction
temperature

Temperature warning hysteresis 5 °K

Thermal shutdown threshold junction
temperature

Thermal shutdown threshold junction
temperature

Thermal shutdown hysteresis 5 °K

2.5 Electrical characteristics

VS = 8 to 16 V, VCC = 4.5 to 5.3 V, Tj = - 40 to 150 °C, unless otherwise specified.

The voltages are referred to GND and currents are assumed positive, when the current
flows into the pin.

Table 7. S u pply

Symbol Parameter Test condition Min. Typ. Max. Unit

V

Operating supply voltage

S

range

VS DC supply current

I

S

quiescent supply current

V

S

Tj

increasing

Tj

decreasing

130 °C

Tj

increasing

Tj

decreasing

150 °C

728V

V

= 13V, VCC = 5.0V

S

active mode

720mA

OUT1 - OUT5 floating

= 13V, VCC = 0V

V

S

standby mode
OUT1 - OUT5 floating

=-40°C, 25°C

T

test

T

= 130°C 6 20 µA

test

310µA

150 °C

170 °C

10/36 Doc ID 14173 Rev 8

L9951 / L9951XP Electrical specifications

Table 7. Supply (continued)

Symbol Parameter Test condition Min. Typ. Max. Unit

V

= 13V, VCC = 5.0V

S

V

DC supply current

CC

CSN = V

CC

active mode

I

CC

VCC quiescent supply
current

= 13V, VCC = 5.0V

V

S

CSN = V

CC

standby mode
OUT1 - OUT5 floating

VS = 13V, VCC = 5.0V

IS + I

Sum quiescent supply

CC

current

CSN = V

CC

standby mode
OUT1 - OUT5 floating

Table 8. Overvoltage and undervoltage detection

Symbol Parameter Test condition Min. Typ. Max. Unit

13mA

13µA

723µA

V

SUV ON

V

SUV OFF

V

SUV hyst

V

SOV OFF

V

SOV ON

V

SOV hyst

V

POR OFF

V

POR ON

V

POR hyst

Table 9. Current monitor output

VS UV-threshold voltage VS increasing 6.0 7.2 V

VS UV-threshold voltage VS decreasing 5.4 6.5 V

VS UV-hysteresis V

SUV ON

- V

SUV OFF

0.55 V

VS OV-threshold voltage VS increasing 18 24.5 V

VS OV-threshold voltage VS decreasing 17.5 V

VS OV-hysteresis V

SOV OFF

- V

SOV ON

0.5 V

Power-on-reset threshold VCC increasing 4.4 V

Power-on-reset threshold VCC decreasing 3.1 V

Power-on-reset hysteresis V

POR OFF

- V

POR ON

0.3 V

Symbol Parameter Test condition Min. Typ. Max. Unit

V

Functional voltage range VCC = 5V 0 4 V

CM

Current monitor output

I

CM,r

ratio:
I

CM/IOUT1,2,3,4,5

0V ≤ V

≤ 4V, VCC=5V

CM

1:10000

-

0V ≤ VCM≤ 4V,

=5V,

V

CC

I

OUT1-5,low

I

CM acc

Current monitor accuracy

I

OUT1,high

I

OUT2,3,high

I

OUT4,5,high

=500mA

=6A

=4.9A
=1.2A

4% +

1%FS

8% +

2%FS

-

(FS=full scale=600 μA)

Doc ID 14173 Rev 8 11/36

Electrical specifications L9951 / L9951XP

Table 10. Charge pump output

Symbol Parameter Test condition Min. Typ. Max. Unit

V

I

Table 11. OUT 1 - OUT 5

Charge pump output

CP

voltage

Charge pump output

CP

current

V

S

V

S

V

S

=8V, I

=10V, I

≥12V, I

V

CP

VS =13.5V

= -60µA 6 13 V

CP

= -80µA 8 13 V

CP

= -100µA 10 13 V

CP

= VS+10V

100 150 300 µA

Symbol Parameter Test condition Min. Typ. Max. Unit

= 13.5 V, Tj = 25 °C,

V

R

ON OUT1

R

ON OUT2

R

ON OUT3

r

ON OUT4,

r

ON OUT5

|I

OUT1

|I

OUT2

|I

OUT3

|I

OUT4

|I

OUT5

t

d ON H

On-resistance to supply
or GND

On-resistance to supply
or GND

On-resistance to supply
or GND

Output current limitation

|

to supply or GND

Output current limitation

|,

|

to supply or GND

|,

Output current limitation

|

to GND

Output delay time,
highside driver on

S

= ± 3 A

I

OUT1

= 13.5 V, Tj = 125 °C,

V

S

= ± 3 A

I

OUT1

V

= 8.0 V, Tj = 25 °C,

S

I

= ± 3 A

OUT1

VS = 13.5 V, Tj = 25 °C,
I

V
I

V
I

= ± 3 A

OUT2,3

= 13.5 V, Tj = 125 °C,

S

= ± 3 A

OUT2,3

= 8.0 V, Tj = 25 °C,

S

= ± 3 A

OUT2,3

VS = 13.5 V, Tj = 25 °C,
I

V
I

V
I

= ± 0.8 A

OUT4,5

= 13.5 V, Tj = 125 °C,

S

= ± 0.8 A

OUT4,5

= 8.0 V, Tj = 25 °C,

S

= ± 0.8 A

OUT4,5

Sink and source 7.4 15.5 A

Sink and source 5.0 10.5 A

Source 1.25 2.6 A

VS = 13.5 V,
corresponding lowside

20 40 90 µs

driver is not active

150 200 mΩ

225 300 mΩ

150 200 mΩ

200 270 mΩ

300 400 mΩ

200 270 mΩ

800 1100 mΩ

1250 1700 mΩ

800 1100 mΩ

t

d OFF H

t

d ON L

Output delay time,
highside driver off

Output delay time,
lowside driver on

VS = 13.5 V 80 200 300 µs

VS = 13.5 V,
corresponding highside
driver is not active

12/36 Doc ID 14173 Rev 8

20 60 80 µs

L9951 / L9951XP Electrical specifications

Table 11. OUT 1 - OUT 5 (continued)

Symbol Parameter Test condition Min. Typ. Max. Unit

t

d OFF L

t

t

I

I

I

OLD1

I

OLD23

I

OLD45

t

dV

OUT1

dV

OUT23

dV

OUT45

D HL

D LH

QLH

QLL

dOL

t

ISC

Output delay time,
lowside driver off

Cross current protection
time, source to sink

Cross current protection
time, sink to source

Switched-off output
current highside drivers of
OUT1-5

Switched-off output
current lowside drivers of
OUT1-3

Open-load detection
current of OUT1

Open-load detection
current of OUT2, OUT3

Open-load detection
current of OUT4 and
OUT5

Minimum duration of
open-load condition to set
the status bit

Minimum duration of
over-current condition to
switch off the driver

/dt

Slew rate of OUT1

/dt

Slew rate of OUT2, OUT3

/dt

Slew rate of OUT4, OUT5

= 13.5 V 80 150 300 µs

V

S

t

d ON L

t

d ON H

V

OUT1-5

mode

V

OUT1-5

V

OUT1-3

mode

V

OUT1-3

- t

d OFF H,

- t

d OFF L

= 0V, standby

0-2-5µA

= 0V, active mode -40 -15 0 µA

= VS, standby

0 50 100 µA

= VS, active mode -40 -15 0 µA

200 400 µs

200 400 µs

70 160 240 mA

70 160 240 mA

51540mA

500 3000 µs

10 100 µs

V

=13.5 V

S

= ±1.5 A

I

load

V

= 13.5 V

S

= ±1.5 A

I

load

V

= 13.5 V

S

= - 0.8 A

I

load

0.1 0.2 0.4 V/µs

0.1 0.2 0.4 V/µs

0.1 0.2 0.4 V/µs

Doc ID 14173 Rev 8 13/36

Electrical specifications L9951 / L9951XP

2.6 SPI - electrical characteristics

(VS = 8 to 16 V, VCC = 4.5 to 5.3 V, Tj = - 40 to 150 °C, unless otherwise specified. The
voltages are referred to GND and currents are assumed positive, when the current flows into
the pin).

Table 12. Delay time from standby to active mode

Symbol Parameter Test condition Min. Typ. Max. Unit

Switching from standby

t

set

Table 13. Inputs: CSN, CLK, PWM1/2 and DI

Internal startup time

Symbol Parameter Test condition Min. Typ. Max. Unit

to active mode. Time
until not Ready Bit goes
low.

80 300 µs

V

V

V

inHyst

I

CSN in

I

CLK in

I

DI in

I

EN in

C

Input low level VCC = 5V 1.5 2.0 V

inL

Input high level VCC = 5V 3.0 3.5 V

inH

Input hysteresis VCC = 5V 0.5 V

Pull up current at input CSN V

Pull down current at input CLK V

= 3.5V VCC = 5V -50 -25 -10 µA

CSN

= 1.5V 10 25 50 µA

CLK

Pull down current at input DI VDI = 1.5V 10 25 50 µA

Pull down resistance at input
EN

Input capacitance at input

in

CLK, DI and PWM

= 0 to 5.3V 10 15 pF

V

CC

100 210 480 kΩ

Note: Value of input capacity is not measured in production test. Parameter guaranteed by design.

Table 14. DI timing

Symbol Parameter Test condition Min. Typ. Max. Unit

t

CLK

t

CLKH

t

CLKL

t

set CSN

Clock period VCC = 5V 1000 ns

Clock high time VCC = 5V 400 ns

Clock low time VCC = 5V 400 ns

CSN setup time, CSN low
before rising edge of CLK

(1)

V

= 5V 400 ns

CC

t

set CLK

t

set DI

t

hold time

CLK setup time, CLK high
before rising edge of CSN

DI setup time VCC = 5V 200 ns

DI hold time VCC = 5V 200 ns

14/36 Doc ID 14173 Rev 8

= 5V 400 ns

V

CC

L9951 / L9951XP Electrical specifications

Table 14. DI timing

(1)

(continued)

Symbol Parameter Test condition Min. Typ. Max. Unit

t

t

1. See Figure 3 and Figure 4

Rise time of input signal DI,

r in

CLK, CSN

Fall time of input signal DI,

f in

CLK, CSN

= 5V 100 ns

V

CC

V

= 5V 100 ns

CC

Note: DI timing parameters tested in production by a passed/failed test:

Tj= -40°C/+25°C: SPI communication @2MHZ.
Tj= +125°C: SPI communication @1.25MHZ.

Table 15. D O

Symbol Parameter Test condition Min. Typ. Max. Unit

V

V

I

DOLK

C

DO

Output low level VCC = 5 V, ID = -4mA 0.2 0.4 V

DOL

Output high level VCC = 5 V, ID = 4 mA

DOH

V

= VCC,

Tristate leakage current

(1)

Tristate input capacitance

CSN

0V < V

V

CSN

< V

DO

= VCC,

CC

0V < VCC < 5.3V

V

-0.4

CC

V

CC

-0.2

-10 10 µA

10 15 pF

V

1. Value of input capacity is not measured in production test. Parameter guaranteed by design.

Table 16. DO timing

(1)

Symbol Parameter Test condition Min. Typ. Max. Unit

t

r DO

t

f DO

t

en DO tri L

t

dis DO L tri

t

en DO tri H

t

dis DO H tri

t

d DO

1. See Figure 5 and Figure 6.

DO rise time CL = 100 pF, I

DO fall time CL = 100 pF, I

DO enable time
from tristate to low level

DO disable time
from low level to tristate

DO enable time
from tristate to high level

DO disable time
from high level to tristate

DO delay time

CL = 100 pF, I
pull-up load to V

CL = 100 pF, I
pull-up load to V

CL =100 pF, I
pull-down load to GND

CL = 100 pF, I
pull-down load to GND

V

< 0.3 VCC, V

DO

= 100pF

C

L

= -1mA 80 140 ns

load

= 1mA 50 100 ns

load

= 1mA

load

load

load

load

CC

= 4 mA

CC

= -1mA

= -4mA

> 0.7VCC,

DO

100 250 ns

380 450 ns

100 250 ns

380 450 ns

50 250 ns

Doc ID 14173 Rev 8 15/36

Electrical specifications L9951 / L9951XP

010

Table 17. EN, CSN timing

(1)

Symbol Parameter Test condition Min. Typ. Max. Unit

Minimum EN high before

t

EN_CSN_LO

sending first SPI frame, i.e.
CSN going low

t

CSN_HI,min

1. See Figure 7

Minimum CSN HI time
between two SPI frames

Transfer of SPI-command
to input register

Transfer of SPI-command
to input register

20 50 µs

24µs

Figure 3. SPI - transfer timing diagram

CSN high to low: DO enabled

CSN

CLK

DI

DO

e.g.OUT1

123 456789101101213141510

DI: data will be accepted on the rising edge of CLK signal

actual data

123 45 6 7 8 91011012131415

new data

DO: data will change on the falling edge of CLK signal

status information

123 45 6 7 8 91011012131415

1

fault bit CSN low to high: actual data is

transfered to output power switches

old data

actual data

time

time

time

time

time

Figure 4. SPI - input timing

CSN

t

set CSN

CLK

t

set DI

DI

16/36 Doc ID 14173 Rev 8

Valid

t

t

hold DI

CLKH

t

CLKL

Valid

t

set CLK

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

L9951 / L9951XP Electrical specifications

t

f

t

f

t

t

C

C

Figure 5. SPI - DO valid data delay time and valid time

in

CLK

t

r DO

DO

(low to high)

t

d DO

t

DO

DO

(high to low)

Figure 6. SPI - DO enable and disable time

f in r in

CSN

r i n

0.8 VCC

0.5 VCC

0.2 VCC

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

0.8 VC
50%

0.2 VC

DO

50%

pull-up load to VCC

C = 100 pF

L

DO

t t

en DO tri L

dis DO L tri

50%

pull-down load to GND

C = 100 pF

L

t t

en DO tri H

dis DO H tri

Doc ID 14173 Rev 8 17/36

Electrical specifications L9951 / L9951XP

CS

O

Figure 7. SPI - driver turn-on/off timing, minimum CSN HI time

CSN low to high: data from shift register
is transferred to output power switches

t

r in f in

t

CSN_HI,min

CSN

t

dOFF

output current
of a driver

output current
of a driver

ON state OFF state

t

OFF

t

dON

t

ON

OFF state

Figure 8. SPI - timing of status bit 0 (fault condition)

N high to low and CLK stays low: status information of data bit 0 (fault condition) is transfered to D

ON state

t

80%

50%

20%

80%

50%

20%

80%

50%

20%

CSN

time

CLK

time

DI

time

DI: data is not accepted

DO

0

-

time

DO: status information of data bit 0 (fault condition) will stay as long as CSN is low

18/36 Doc ID 14173 Rev 8

L9951 / L9951XP Application information

3 Application information

3.1 Dual power supply: VS and V

The power supply voltage VS supplies the half bridges and the high side drivers. An internal
charge-pump is used to drive the high side switches. The logic supply voltage V
(stabilized 5V) is used for the logic part and the SPI of the device. Due to the independent
logic supply voltage the control and status information will not be lost, if there are temporary
spikes or glitches on the power supply voltage. In case of power-on (V
under voltage to V

POR OFF

= 4.0V, typical) the circuit is initialized by an internally generated

power-on-reset (POR).

If the voltage V

decreases under the minimum threshold (V

CC

outputs are switched to tristate (high impedance) and the status registers are cleared.

3.2 Standby - mode

The standby mode of the L9951 is activated by switching the EN input do GND. All latched
data will be cleared and the inputs and outputs are switched to high impedance. In the
standby mode the current at V

(VCC) is less than 3 µA (1µA) for CSN = high (DO in tristate).

S

If EN is switched to 5V the device will enter the active mode. In the active mode the charge­pump and the supervisor functions are activated.

3.3 Inductive loads

Each half bridge is built by an internally connected high side and a low side power DMOS
transistor. Due to the built-in reverse diodes of the output transistors, inductive loads can be
driven at the outputs OUT1 to OUT3 without external free-wheeling diodes. The high side
drivers OUT4 to OUT5 are intended to drive resistive loads. Hence only a limited energy
(E<0.5mJ) can be dissipated by the internal ESD-diodes in freewheeling condition. For
inductive loads (L > 50µH) an external free-wheeling diode connected to GND and the
corresponding output is needed.

CC

POR ON

CC

increases from

CC

=3.6V, typical), the

3.4 Diagnostic functions

All diagnostic functions (over/open-load, power supply over-/undervoltage, temperature
warning and thermal shutdown) are internally filtered and the condition has to be valid for at
least 32µs (open-load: 1ms, respectively) before the corresponding status bit in the status
registers will be set. The filters are used to improve the noise immunity of the device. Open­load and temperature warning function are intended for information purpose and will not
change the state of the output drivers. On contrary, the over load and thermal shutdown
condition will disable the corresponding driver (over load) or all drivers (thermal shutdown),
respectively. Without setting the over-current recovery bit in the Input Data Register to logic
high, the microcontroller has to clear the over-current status bit to reactivate the
corresponding driver. Each driver has a corresponding over-current recovery bit. If this bit is
set, the device will automatically switch-on the outputs again after a short recovery time. The
duty cycle in over-current condition can be programmed by the SPI interface (12% or 25%).
With this feature the device can drive loads with start-up currents higher than the over­current limits (e.g. inrush current of lamps, cold resistance of motors and heaters).

Doc ID 14173 Rev 8 19/36

Application information L9951 / L9951XP

3.5 Over-voltage and under-voltage detection

If the power supply voltage VS rises above the over-voltage threshold V
21V), the outputs OUT1 to OUT5 are switched to high impedance state to protect the load
and the internal charge-pump is turned-off. When the voltage V
undervoltage threshold V

SUV OFF

(UV-switch-OFF voltage), the output stages are switched

drops below the

S

to the high impedance to avoid the operation of the power devices without sufficient gate
driving voltage (increased power dissipation). If the supply voltage V
operating voltage the output stages return to the programmed state (input register 0: bit
12=0). If the undervoltage / overvoltage recovery disable bit is set, the automatic turn-on of
the drivers is deactivated. The microcontroller needs to clear the status bits to reactivate the
drivers.

3.6 Temperature warning and thermal shutdown

If junction temperature rises above T
via the SPI. If junction temperature increases above the second threshold T
shutdown bit will be set and power DMOS transistors of all output stages are switched off to
protect the device. In order to reactivate the output stages the junction temperature must
decrease below T

jSD

- T

jSD HYS

and the thermal shutdown bit has to be cleared by the

microcontroller.

a temperature warning flag is set and is detectable

j TW

3.7 Open-load detection

The open-load detection monitors the load current in each activated output stage. If the load
current is below the open-load detection threshold for at least 1 ms (t
open-load bit is set in the status register. Due to mechanical/electrical inertia of typical loads
a short activation of the outputs (e.g. 3ms) can be used to test the open-load status without
changing the mechanical/electrical state of the loads.

SOV OFF

recovers to normal

S

) the corresponding

dOL

(typical

, the thermal

j SD

3.8 Over load detection

In case of an over-current condition a flag is set in the status register in the same way as
open-load detection. If the over-current signal is valid for at least t
flag is set and the corresponding driver is switched off to reduce the power dissipation and
to protect the integrated circuit. If the over-current recovery bit of the output is zero the
microcontroller has to clear the status bits to reactivate the corresponding driver.

3.9 Current monitor

The current monitor output sources a current image at the current monitor output which has
a fixed ratio (1/10000) of the instantaneous current of the selected high side driver. The bits
9, 10 and 11 of the input data register 0 control which of the outputs OUT1 to OUT5 will be

20/36 Doc ID 14173 Rev 8

multiplexed to the current monitor output. The current monitor output allows a more precise
analysis of the actual state of the load rather than the detection of an open- or overload
condition. For example this can be used to detect the motor state (starting, free-running,
stalled). Moreover, it is possible to regulate the power of the defroster more precise by
measuring the monitor current.

=32µs, the over-current

ISC

L9951 / L9951XP Application information

3.10 PWM input

Each driver has a corresponding PWM enable bit which can be programmed by the SPI
interface. If the PWM enable bit is set, the outputs OUT1 to OUT5 are controlled by the
logically AND-combination of the signal applied to the PWM input and the output control bit
in input data register1.

3.11 Cross-current protection

The three half-brides of the device are cross-current protected by an internal delay time. If
one driver (LS or HS) is turned-off the activation of the other driver of the same half bridge
will be automatically delayed by the cross-current protection time. After the cross-current
protection time is expired the slew-rate limited switch-off phase of the driver will be changed
to a fast turn-off phase and the opposite driver is turned-on with slew-rate limitation. Due to
this behavior it is always guaranteed that the previously activated driver is totally turned-off
before the opposite driver will start to conduct.

3.12 Programmable softstart function to drive loads with higher inrush current

Loads with start-up currents higher than the over-current limits (e.g. inrush current of lamps,
start current of motors and cold resistance of heaters) can be driven by using the
programmable softstart function (i.e. overcurrent recovery mode). Each driver has a
corresponding over-current recovery bit. If this bit is set, the device will automatically switch­on the outputs again after a programmable recovery time. The duty cycle in over-current
condition can be programmed by the SPI interface to be about 12% or 25%. The PWM
modulated current will provide sufficient average current to power up the load (e.g. heat up
the bulb) until the load reaches operating condition.

The device itself cannot distinguish between a real overload and a non linear load like a light
bulb. A real overload condition can only be qualified by time. As an example the
microcontroller can switch on light bulbs by setting the over-current Recovery bit for the first
50ms. After clearing the recovery bit the output will be automatically disabled if the overload
condition still exits.

Figure 9. Example of programmable softstart function for inductive loads

Doc ID 14173 Rev 8 21/36

Functional description of the SPI L9951 / L9951XP

4 Functional description of the SPI

4.1 Serial Peripheral Interface (SPI)

This device uses a standard SPI to communicate with a microcontroller. The SPI can be
driven by a microcontroller with its SPI peripheral running in following mode: CPOL = 0 and
CPHA = 0.

For this mode, input data is sampled by the low to high transition of the clock CLK, and
output data is changed from the high to low transition of CLK.

This device is not limited to microcontroller with a build-in SPI. Only three CMOS-compatible
output pins and one input pin will be needed to communicate with the device. A fault
condition can be detected by setting CSN to low. If CSN = 0, the DO-pin will reflect the
status bit 0 (fault condition) of the device which is a logical-or of all bits in the status registers
0 and 1. The microcontroller can poll the status of the device without the need of a full SPI­communication cycle.

Note: In contrast to the SPI-standard the least significant bit (LSB) will be transferred first (see

Figure 3).

4.2 Chip Select Not (CSN)

The input pin is used to select the serial interface of this device. When CSN is high, the
output pin (DO) will be in high impedance state. A low signal will activate the output driver
and a serial communication can be started.

The state when CSN is going low until the rising edge of CSN will be called a
communication frame. If the CSN-input pin is driven above 7.5V, the L9951 will go into a test
mode. In the test mode the DO will go from tristate to active mode.

4.3 Serial Data In (DI)

The input pin is used to transfer data serial into the device. The data applied to the DI will be
sampled at the rising edge of the CLK signal and shifted into an internal 16 bit shift register.
At the rising edge of the CSN signal the contents of the shift register will be transferred to
Data Input Register.

The writing to the selected Data Input Register is only enabled if exactly 16 bits are
transmitted within one communication frame (i.e. CSN low). If more or less clock pulses are
counted within one frame the complete frame will be ignored. This safety function is
implemented to avoid an activation of the output stages by a wrong communication frame.

Note: Due to this safety functionality a daisy chaining of SPI is not possible. Instead, a parallel

operation of the SPI bus by controlling the CSN signal of the connected ICs is
recommended.

22/36 Doc ID 14173 Rev 8

L9951 / L9951XP Functional description of the SPI

4.4 Serial Data Out (DO)

The data output driver is activated by a logical low level at the CSN input and will go from
high impedance to a low or high level depending on the status bit 0 (fault condition). The first
rising edge of the CLK input after a high to low transition of the CSN pin will transfer the
content of the selected status register into the data out shift register. Each subsequent
falling edge of the CLK will shift the next bit out.

4.5 Serial clock (CLK)

The CLK input is used to synchronize the input and output serial bit streams. The data input
(DI) is sampled at the rising edge of the CLK and the data output (DO) will change with the
falling edge of the CLK signal.

4.6 Input data register

The device has two input registers. The first bit (bit 0) at the DI-input is used to select one of
the two input registers. All bits are first shifted into an input shift register. After the rising
edge of CSN the contents of the input shift register will be written to the selected input data
register only if a frame of exact 16 data bits are detected. Depending on bit 0 the contents of
the selected status register will be transferred to DO during the current communication
frame. Bit 1-8 control the behavior of the corresponding driver. The bits 9,10 and 11 are
used to control the current monitor multiplexer. Bit 15 is used to reset all status bits in both
status registers. The bits in the status registers will be cleared after the current
communication frame (rising edge of CSN).

4.7 Status register

This devices uses two status registers to store and to monitor the state of the device. Bit 0 is
used as a fault bit and is a logical-NOR combination of bits 1-14 in both status registers. The
state of this bit can be polled by the microcontroller without the need of a full SPI­communication cycle (see Figure 8.). If one of the over-current bits is set, the corresponding
driver will be disabled. If the over-current recovery bit of the output is not set the
microcontroller has to clear the over-current bit to enable the driver. If the thermal shutdown
bit is set, all drivers will go into a high impedance state. Again the microcontroller has to
clear the bit to enable the drivers.

4.8 Test mode

The test mode can be entered by rising the CSN input to a voltage higher than 7.5V. In the
test mode the inputs CLK, DI, PWM and the internal 2MHz CLK can be multiplexed to data
output DO for testing purpose. Furthermore the over-current thresholds are reduced by a
factor of 4 to allow EWS testing at lower current. The internal logic prevents that the Hi-Side
and Low-Side driver of the same half-bridge can be switched-on at the same time. In the test
mode this combination is used to multiplex the desired signals to the CM output according to
table 18 and 19.

Doc ID 14173 Rev 8 23/36

Functional description of the SPI L9951 / L9951XP

Table 18. Test mode

LS1 HS1 LS2 HS2 LS3 HS3 DO LS1 HS1 LS2 HS2 LS3 HS3 CM

! (both HI) ! (both HI) ! (both HI) NoError ! (both HI) ! (both HI) ! (both HI) N.C

both HI ! (both HI) ! (both HI) DI both HI ! (both HI) ! (both HI) Tsense1

! (both HI) both HI ! (both HI) CLK ! (both HI) both HI ! (both HI) Tsense2

both HI both HI ! (both HI) INT_CLK both HI both HI ! (both HI) Tsense3

! (both HI) ! (both HI) both HI PWM ! (both HI) ! (both HI) both HI Tsense4

both HI ! (both HI) both HI N.C

! (both HI) both HI both HI 5µA Iref

both HI both HI both HI Vbandgap

Table 19. SPI - Input data and status register 0

Input register 0 (write) Status register 0 (read)

Bit Name Comment Name Comment

A broken VCC-or SPI­connection of the L9951 can
be detected by the
microcontroller, because all 16
bits low or high is not a valid
frame.

In case of an over-voltage or
undervoltage event the
corresponding bit is set and
the outputs are deactivated.

15 Reset bit

Disable open-

14

load

If reset bit is set both status
registers will be cleared after
rising edge of CSN input.

If the disable open-load bit is
set, the open-load status
bits will be ignored for the
NonErrorBit calculation.

Always 1

V

S

over-voltage

This bit defines in

OC recovery

duty cycle

combination with the over­current recovery bit (input
register 1) the duty cycle in

13

over-current condition of an
activated driver. If
temperature warning bit is

0: 12% 1: 25%

set, L9951 will always use
the lower duty cycle

Overvoltage/
under-voltage

12

recovery
disable

If this bit is set the
microcontroller has to clear
the status register after
undervoltage/overvoltage
event to enable the outputs.

24/36 Doc ID 14173 Rev 8

V

S

undervoltage

Thermal

shutdown

If VS voltage recovers to
normal operating conditions
outputs are reactivated
automatically.

In case of an thermal
shutdown all outputs are
switched off. The
microcontroller has to clear the
TSD bit by setting the reset bit
to reactivate the outputs.

L9951 / L9951XP Functional description of the SPI

Table 19. SPI - Input data and status register 0 (continued)

Input register 0 (write) Status register 0 (read)

Bit Name Comment Name Comment

11

Following current image
(1/10.000) of the HS driver
will be multiplexed to CM
output:

Temperature

warning

This bit is for information
purpose only. It can be used
for a thermal management by
the microcontroller to avoid a
thermal shutdown.

After switching the device from
standby mode to active mode

Bit 11 Bit 10 Bit 9 Output

Current monitor

select bits

10 Not ready bit

000OUT1
001OUT2
010OUT3
011OUT4
100OUT5

an internal timer is started to
allow charge pump to settle
before the outputs can be
activated. This bit is cleared
automatically after start up
time has finished. Since this bit
is controlled by internal clock it
can be used for synchronizing
testing events (e.g. measuring
filter times).

9 0 Not used

8

7

6

5

4

3

2

1

OUT5 - HS

on/off

OUT4 - HS

on/off

OUT3 - HS

on/off

OUT3 - LS

on/off

OUT2 - HS

on/off

OUT2 - LS

on/off

OUT1 - HS

on/off

OUT1 - LS

on/off

If a bit is set the selected
output driver is switched on.
If the corresponding PWM
enable bit is set (Input
Register 1) the driver is only
activated if PWM input
signal is high. The outputs of
OUT1-OUT3 are half
bridges. If the bits of HS­and LS-driver of the same
half bridge are set, the
internal logic prevents that
both drivers of this output
stage can be switched on
simultaneously in order to
avoid a high internal current
from VS to GND.

OUT5-HS

over - current

OUT4-HS

over - current

OUT3-HS

over - current

OUT3-LS

over - current

OUT2-HS

over - current

OUT2-LS

over - current

OUT1-HS

over - current

OUT1-LS

over - current

In case of an over-current
event the corresponding status
bit is set and the output driver
is disabled. If the over-current
recovery enable bit is set
(Input Register 1) the output
will be automatically
reactivated after a delay time
resulting in a PWM modulated
current with a programmable
duty cycle (Bit 13).

If the over-current recovery bit
is not set the microcontroller
has to clear the over-current bit
(reset bit) to reactivate the
output driver.

A logical NOR-combination of
all bits 1 to 14 in both status

0 0 No error bit

registers. If bit 14 (disable
open-load) is set, the open­load status will be ignored.

Doc ID 14173 Rev 8 25/36

Functional description of the SPI L9951 / L9951XP

Table 20. SPI - Input data and status register 1

Input register 1 (write) Status register 1 (read)

Bit Name Comment Name Comment

A broken VCC-or SPI­connection of the L9951 can

15 Not used Always 1

14 Not used V

13 Not used V

12 Not used

11 Not used

over-voltage

S

undervoltage

S

Thermal

shutdown

Temperature

warning

be detected by the
microcontroller, because all
16 bits low or high is not a
valid frame.

In case of an over-voltage or
undervoltage event the
corresponding bit is set and
the outputs are deactivated.

In case of an over-voltage or
undervoltage event the
corresponding bit is set and
the outputs are deactivated.

In case of an thermal
shutdown all outputs are
switched off. The
microcontroller has to clear
the TSD bit by setting the
reset bit to reactivate the
outputs.

This bit is for information
purpose only. It can be used
for a thermal management by
the microcontroller to avoid a
thermal shutdown.

26/36 Doc ID 14173 Rev 8

L9951 / L9951XP Functional description of the SPI

Table 20. SPI - Input data and status register 1 (continued)

Input register 1 (write) Status register 1 (read)

Bit Name Comment Name Comment

In case of an over-current
event the over-current
status bit (status register

0) is set and the output is
switched off. If the over-

10

OUT5 OC

recovery enable

current recovery enable bit
is set the output will be
automatically reactivated

Not ready bit

after a delay time resulting
in a PWM modulated
current with a
programmable duty cycle
(Bit 13 of Input data

9

8

7

6

5

4

3

2

1

OUT4 OC

recovery enable

OUT3 OC

recovery enable

OUT2 OC

recovery enable

OUT1 OC

recovery enable

OUT5 PWM

enable

OUT4 PWM

enable

OUT3 PWM

enable

OUT2 PWM

enable

OUT1 PWM

enable

register 1).

Depending on occurrence
of overcurrent event and
internal clock phase it is
possible that one recovery
cycle is executed even if
this bit is set to zero.

If the PWM enable bit is
set and the output is
enabled (input register 0)
the output is switched on if
PWM input is high and
switched off if PWM input
is low.

0 Not used.

OUT5-HS
open-load

OUT4-HS
open-load

OUT3-HS
open-load

OUT3-LS

open-load

OUT2-HS
open-load

OUT2-LS

open-load

OUT1-HS
open-load

OUT1-LS

open-load

0 1 No error bit

After switching the device
from standby mode to active
mode an internal timer is
started to allow charge pump
to settle before the outputs
can be activated. This bit is
cleared automatically after
start up time has finished.
Since this bit is controlled by
internal clock it can be used
for synchronizing testing
events(e.g. measuring filter
times).

The open-load detection
monitors the load current in
each activated output stage. If
the load current is below the
open-load detection threshold
for at least 1 ms (t

dOL

) the
corresponding open-load bit
is set. Due to mechanical
/electrical inertia of typical
loads a short activation of the
outputs (e.g. 3ms) can be
used to test the open-load
status without changing the
mechanical/electrical state of
the loads.

A logical NOR-combination of
all bits 1 to 14 in both status
registers. If bit 14 (Disable
Open-Load) is set, the open­load status will be ignored

Doc ID 14173 Rev 8 27/36

Packages thermal data L9951 / L9951XP

5 Packages thermal data

Figure 10. Packages thermal data

28/36 Doc ID 14173 Rev 8

L9951 / L9951XP Package and packing information

6 Package and packing information

6.1 ECOPACK® packages

In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK

®

packages, depending on their level of environmental compliance. ECOPACK®

specifications, grade definitions and product status are available at: www.st.com

ECOPACK

®

is an ST trademark.

6.2 PowerSO-36™ package information

Figure 11. PowerSO-36™ package dimensions

.

Table 21. PowerSO-36™ mechanical data

Millimeters

Symbol

Min. Typ. Max.

A 3.60

a1 0.10 0.30

a2 3.30

a3 0 0.10

b 0.22 0.38

c 0.23 0.32

Doc ID 14173 Rev 8 29/36

Package and packing information L9951 / L9951XP

Table 21. PowerSO-36™ mechanical data (continued)

Millimeters

Symbol

Min. Typ. Max.

D * 15.80 16.00

D1 9.40 9.80

E 13.90 14.5

E1 * 10.90 11.10

E2 2.90

E3 5.80 6.20

e0.65

e3 11.05

G 0 0.10

H 15.50 15.90

h 1.10

L 0.8 1.10

M

N 10 deg

R

s 8 deg

30/36 Doc ID 14173 Rev 8

L9951 / L9951XP Package and packing information

6.3 PowerSSO-36™ package information

Figure 12. PowerSSO-36™ package dimensions

Table 22. PowerSSO-36™ mechanical data

Millimeters

Symbol

Min. Typ. Max.

A- -2.45

A2 2.15 - 2.35

a1 0 - 0.1

b 0.18 - 0.36

c 0.23 - 0.32

D * 10.10 - 10.50

E * 7.4 - 7.6

e-0.5-

e3 - 8.5 -

F2.3

G- -0.1

G1 - - 0.06

H 10.1 - 10.5

h--0.4

k0° 8°

L 0.55 - 0.85

N - - 10 deg

Doc ID 14173 Rev 8 31/36

Package and packing information L9951 / L9951XP

Table 22. PowerSSO-36™ mechanical data (continued)

Symbol

Min. Typ. Max.

X4.3 - 5.2

Y6.9 - 7.5

Millimeters

6.4 PowerSO-36™ packing information

Figure 13. PowerSO-36

TM

tube shipment (no suffix)

32/36 Doc ID 14173 Rev 8

L9951 / L9951XP Package and packing information

Figure 14. PowerSO-36

TM

tape and reel shipment (suffix “TR”)

TAPE DIMENSIONS

A0 15.20 ± 0.1
B0 16.60 ± 0.1
K0 3.90 ± 0.1
K1 3.50 ± 0.1
F 11.50 ± 0.1
P1 24.00 ± 0.1
W 24.00 ± 0.3

REEL DIMENSIONS

Base Qty 600
Bulk Qty 600
A (max) 330
B (min) 1.5
C (±0.2) 13
D (min) 20.2
G (+2 / -0) 24.4
N (min) 60

All dimensions are in mm.

T (max) 30.4

Doc ID 14173 Rev 8 33/36

Package and packing information L9951 / L9951XP

6.5 PowerSSO-36™ packing information

Figure 15. PowerSSO-36

C

B

A

Figure 16. PowerSSO-36

TM

tube shipment (no suffix)

Base Qty 49
Bulk Qty 1225
Tube length (±0.5) 532
A 3.5
B 13.8
C (±0.1) 0.6

All dimensions are in mm.

TM

tape and reel shipment (suffix “TR”)

REEL DIMENSIONS

Base Qty 1000
Bulk Qty 1000
A (max) 330
B (min) 1.5
C (±0.2) 13
F 20.2
G (+2 / -0) 24.4
N (min) 100
T (max) 30.4

TAPE DIMENSIONS

According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986

Tape width W 24
Tape Hole Spacing P0 (±0.1) 4
Component Spacing P 12
Hole Diameter D (±0.05) 1.55
Hole Diameter D1 (min) 1.5
Hole Position F (±0.1) 11.5
Compartment Depth K (max) 2.85
Hole Spacing P1 (±0.1) 2

End

All dimensions are in mm.

Start

Top

cover

tape

500mm min

Empty components pockets
sealed with cover tape.

User direction of feed

No componentsNo components Components

500mm min

34/36 Doc ID 14173 Rev 8

L9951 / L9951XP Revision history

7 Revision history

Table 23. Document revision history

Date Revision Description of changes

Mar-2004 1 First issue

Jun-2005 2

Added PowerSO-36™ package information, PowerSO-36™ package

information.

Jul-2005 3 Updated Figure 1.: Block diagram .

Sep-2005 4

Note 1 removal;
Updated Figure 10.: Packages thermal data.

Feb-2006 5 Updated Table 4.: ESD protection.

Document restructured and reformatted.

15-Nov-2007 6

Added PowerSO-36™ packing information and PowerSSO-36™

packing information.

Table 22: PowerSSO-36™ mechanical data:

– Deleted A (min) value

24-Jun-2009 7

– Changed A (max) value from 2.47 to 2.45
– Changed A2 (max) value from 2.40 to 2.35
– Changed a1 (max) value from 0.075 to 0.1
– Added F and k rows

Table 22: PowerSSO-36™ mechanical data:

– Changed X: minimum value from 4.1 to 4.3 and

14-May-2010 8

maximum value from 4.7 to 5.2

– Changed Y: minimum value from 6.5 to 6.9 and

maximum value from 7.1 to 7.5

Doc ID 14173 Rev 8 35/36

L9951 / L9951XP

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36/36 Doc ID 14173 Rev 8