lellatchand the shiftregisterinsidetheL9822NSP.
Thispin isactivelowandit mustnotbe left floating.
Apoweronclearfunctionmaybe implementedconnectingthis pin to V
withan externalresistorand
CC
to groundwith an externalcapacitor.
CE
ChipEnable. Datais transferredfromthe shift registerstotheoutputson the risingedgeof thissignal.
Thefalling edgeof this signalsets the shiftregister
with the outputvoltagesensebits coming from the
output stages.The output driver for the SO pin is
enabledwhen this pinis low.
SO
SerialOutput.This pin is theserialoutputfrom the
shift register andit is tri-stated when CE is high.A
highfor a data biton thispin indicatesthat the par-
ticularoutput is high. A low on thispin for adatabit
indicatesthat the outputis low.
Comparing the serial output bits with the previous
serial input bits the external microcontroller implementsthediagnosticdata supplied by theL9822.
SI
SerialInput.Thispin is theserialdata input.A high
pondingto07 aresentandreceivedfirstviatheSPI
bus and 00is thelast.
The outputs are provided with current limiting and
voltagesensefunctionsfor fault indicationand protection.The nominal load current for theseoutputs
is 500mA. Theoutputsalsohave on boardclamps
set at about 36V for recirculation of inductiveload
current.
ELECTRICALCHARACTERISTICS (V
SymbolParameterTest ConditionsMin.Typ.Max.Unit
Output Clamping Volt.IO= 0.5A, Output Programmed OFF303540V
Out. Clamping EnergyIO= 0.5A, When ON20mJ
Out. Leakage CurrentVO= 24V, Output Progr. OFF1mA
On ResistanceOutput Progr. ON
Turn-on DelayIO= 500mA
Turn-off DelayIO= 500mA
Fault Refer. VoltageOutput Progr. OFF
Fault Reset Delay
(after CE L to H
transition)
Output OFF VoltageOutput Pin Floating.cOutput Progr. OFF,1.0V
Output LOW VoltageIO= 1.6mA0.4V
Output HIGH VoltageIO= 0.8mAV
Output Tristate Leakage
Current
Output Capacitance0 < VO<V
0<VO<VCC, CE Pin Held High,
V
= 5.25V
CC
CC
CE Pin Held High
Quiescent Supply
Current at V
CC
Pin
All Outputs Progr. ON. I
O
per Output Simultaneously
= 0.5A
SERIALPERIPHERAL INTERFACE (see fig.2, timingdiagram)
f
op
t
lead
t
lag
t
wSCKH
t
wSCKL
t
su
t
H
t
EN
t
DIS
t
t
rSO
t
fSO
t
rSI
t
fSI
t
ho
V
Operating FrequencyD.C.2MHz
Enable Lead Time250ns
Enable Lag Time250ns
Clock HIGH Time200ns
Clock LOW Time200ns
Data Setup Time75ns
Data Hold Time75ns
Enable Time250ns
Disable Time250ns
Data Valid Time100ns
Rise Time (SO output)VCC= 20 to 70% CL= 200pF50ns
Fall Time (SO output)VCC= 70 to 20% CL= 200pF50ns
Rise Time SPI
VCC= 20 to 70% CL= 200pF200ns
Inputs (SCK, SI, CE)
Fall Time SPI
VCC= 70 to 20% CL= 200pF200ns
Inputs (SCLK, SI, CE)
Output Data Hold Time0ns
0.2V
CC
0.7V
1.45V
–10+10
CC
– 1.3V
–1010
V
V
CC
µ
20pF
V
µA
20pF
10mA
A
4/9
Page 5
FUNCTIONALDESCRIPTION
TheL9822NDMOSoutputis a low operatingpower
device featu-ring, eight 1Ω R
DMOS drivers
DSON
with transient protection circuits in output stages.
Eachchannelis independentlycontrolledbyan outputlatchanda commonRESETlinewhichdisables
all eightoutputs.The driver has low saturationand
shortcircuitprotectionandcandriveinductiveandresistive loads such as solenoids, lamps and relais.
DataistransmittedtothedeviceseriallyusingtheSerialPeripheralInterface(SPI)protocol.Thecircuitreceives8 bit serialdata by meansof the serial input
(SI)which is storedin an internal register to control
theoutputdrivers.Theserialoutput(SO)provides 8
bit ofdiagnosticdata representingthe voltage level
at thedriver output.Thisallows themicroprocessor
to diagnosetheconditionof theoutputdrivers.
The output saturation voltage is monitored by a
comparatorfor an outof saturationconditionandis
abletounlatchtheparticulardriverthroughthefault
resetline. Thiscircuitis also cascadablewith another octal driver in orderto jam 8 bit multiple data.
The device is selected when the chip enable (CE)
lineis low.
Additionallythe (SO) is placed in a tri-state mode
when the deviceis deselected.The negativeedge
of the(CE) transfersthe voltagelevelof thedrivers
tothe shiftregisterand thepositiveedgeofthe(CE)
latchesthenewdatafromtheshiftregistertothedrivers. WhenCE is Low, data bit containedinto the
shift register is transferred to SO output at every
SCLKpositivetransitionwhiledatabitpresentat SI
inputis latchedintotheshiftregisteroneverySCLK
negativetransition.
InternalBlocks Description
The internalarchitectureof the deviceis based on
the threeinternalmajorblocks: the octalshiftregisterfortalkingto the SPIbus,the octallatchfor holdingcontrolbits writtenintothe deviceandthe octal
load driverarray.
L9822N
Individualregisters in the latch may be clearedby
fault conditions in order to protectthe overloaded
outputstages.The entire latchmay also becleared
by theRESET signal.
OutputStages
Theoutputstagesprovidean activelowdrivesignal
suitable for 0.75A continuous loads. The outputs
haveinternalzeners set to 36voltsto clampinductive transients at turn-off. Each output also has a
voltagecomparatorobservingtheoutputnode.Ifthe
voltageexceeds1.8V on an ON outputpin, a fault
conditionis assumedand thelatchdriving thisparticularstageis reset,turningthe outputOFFtoprotect it. The timing of this actionis describedbelow.
These comparators also provide diagnostic feedbackdatatothe shiftregister.Additionally,thecomparatorscontainan internalpulldowncurrentwhich
will cause the cell to indicatea lowoutputvoltageif
the outputis programmed OFF and the output pin
is open circuited.
TIMINGDATA TRANSFER
Figure#2 showsthe overall timing diagramfrom a
byte transfer to and fromthe L9822NSPusing the
SPIbus.
CE Highto LowTransition
Theactionbeginswhenthe ChipEnable(CE)pinis
pulledlow.Thetri-stateSerialOutput(SO)pin driver
willbeenabledentire timethatCE islow.Atthefallingedge of theCEpin,thediagnosticdata fromthe
voltagecomparatorsin theoutputstageswillbelatched into the shift register.If a particularoutput is
high, a logic one will be jammedinto that bit in the
shiftregister.Iftheoutputis low,a logiczerowillbe
loadedthere.Themostsignificantbit(07)shouldbe
presentedat theSerialInput(SI) pin. A zeroat this
pin will programan outputON,whilea one will programthe outputOFF.
Shift Register
The shiftregisterhas bothserialandparallelinputs
and serial and parallel outputs.Theserial input acceptsdatafromthe SPIbusandtheserialoutputsimultaneously sends data into the SPI bus. The
paralleloutputsarelatchedintotheparallellatchinside the L9822N at the end of a datatransfer.The
parallelinputs jam diagnosticdata intothe shift registerat thebeginningof a datatransfercycle.
ParallelLatch
The parallellatchholdstheinputdatafromtheshift
register.This data then actuatestheoutputstages.
SCLK Transitions
The Serial Clock(SCLK) pin shouldthenbe pulled
high.Atthispointthediagnosticbit fromthe mostsignificantoutput(07)willappearattheSOpin.Ahigh
here indicates that the 07 pin is higher than 1.8V.
TheSCLKpinshouldthenbe toggledlowthenhigh.
NewSOdatawillappearfollowingeveryrisingedge
of SCLK and new SI data will be latched into the
L9822Nshift register on the falling edges.An unlimitedamountofdatamaybeshiftedthroughthedeviceshiftregister(intotheSIpinandouttheSOpin),
allowingthe otherSPI devicesto be cascadedin a
daisychainwiththe L9822N.
5/9
Page 6
L9822N
CELow to HighTransition
Once the last data bit has been shifted into the
L9822NSP,theCE pin shouldbe pulled high.
Attherisingedgeof CE the shiftregisterdataislatchedintotheparallellatchandtheoutputstageswill
beactuatedbythe newdata.An internal160µsdelaytimerwillalso be startedat thisrisingedge (see
). During the 160µs period, the outputs will be
t
UD
protectedonlyby the analogcurrentlimiting circuits
since the resetting of the parallel latches by faults
conditionswillbeinhibitedduringthisperiod.Thisallowsthe part toovercomeany highinrushcurrents
that may flow immediately after turn on. Once the
delay period has elapsed, the outputvoltages are
sensedbythe comparatorsand anyoutputwithvoltageshigherthan1.8VarelatchedOFF.Itshouldbe
notedthat the SCLK pin shouldbe low at both transitionsof the CE pin to avoidany false clocking of
theshiftregister.TheSCLKinputis gatedbytheCE
Figure 1 : ByteTiming withAsynchronousReset.
pin, so that the SCLK pin is ignored whenever the
CE pinis high.
lowing way. Clock in a new controlbyte. Wait 160
microseconds or so to allow the outputsto settle.
Clockinthesamecontrolbyteandobservethediagnosticdata that comes outof the device.The diagnostic bits should beidentical to the bits that were
firstclockedin. Anydifferenceswouldpointtoa fault
onthatoutput.IftheoutputwasprogrammedONby
clockingina zero,anda one camebackas the diagnosticbitforthatoutput,theoutputpinwasstillhigh
anda shortcircuit oroverloadconditionexists.Ifthe
output was programmedOFF by clocking in a one,
and a zerocameback as thediagnosticbit for that
output,nothinghad pulledtheoutputpin highandit
must befloating,so an open circuitconditionexists
for that output.
(1) ”D and E1” do not include mold flash or protrusions
- Mold flash or protrusions shall not exceed 0.15mm (0.006”)
E2
hx45°
NN
a2
A
b
DETAILA
e3
e
R
DETAILB
D
1120
E1
T
110
PSO20MEC
lead
a3
Gage Plane
E
DETAILB
0.35
S
a1
L
c
DETAIL A
slug
-C-
SEATING PLANE
GC
(COPLANARITY)
8/9
Page 9
L9822N
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for
the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its
use. No license is granted by implicationor otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specification
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously
supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems
withoutexpress written approval of SGS-THOMSON Microelectronics.
Australia - Brazil - Canada - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco -
The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
1997 SGS-THOMSON Microelectronics – Printed in Italy– AllRights Reserved
PowerSO-20 is a Trademark of SGS-THOMSON Microelectronics
SGS-THOMSON Microelectronics GROUP OF COMPANIES
9/9
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