Datasheet L7981 Datasheet (ST)

Features

■ 3 A DC output current

■ 4.5 V to 28 V input voltage

■ Output voltage adjustable from 0.6 V

■ 250 kHz switching frequency, programmable

up to 1 MHz

■ Internal soft-start and enable

■ Low dropout operation: 100% duty cycle

■ Voltage feed-forward

■ Zero load current operation

■ Overcurrent and thermal protection

■ VFQFPN3x3-8L and HSOP8 package

Applications

■ Consumer:

STB, DVD, DVD recorder, car audio, LCD TV
and monitors

■ Industrial:

PLD, PLA, FPGA, chargers

■ Networking: XDSL, modems, DC-DC modules

■ Computer:

Optical storage, hard disk drive, printers,
audio/graphic cards

■ Suitable for LED driving

L7981

3 A step-down switching regulator

VFQFPN8 3x3

Description

The L7981 is a step down switching regulator with

3.7 A (minimum) current limited embedded power
MOSFET, so it si able to deliver up to 3 A current
to the load depending on the application
conditions.

The input voltage can range from 4.5 V to 28 V,
while the output voltage can be set starting from

0.6 V to V

Requiring a minimum set of external components,
the device includes an internal 250 kHz switching
frequency oscillator that can be externally
adjusted up to 1 MHz.

The QFN and the HSOP packages with exposed
pad allow reducing the R
40°C/W respectively.

.

IN

HSOP8 exposed pad

down to 60°C/W and

thJA

Figure 1. Application circuit

July 2010 Doc ID 15182 Rev 3 1/44

www.st.com

44

Contents L7981

Contents

1 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.1 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

5 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

5.1 Oscillator and synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

5.2 Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

5.3 Error amplifier and compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5.4 Overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5.5 Enable function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.6 Hysteretic thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6 Application informations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6.1 Input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6.2 Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.3 Output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.4 Compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6.4.1 Type III compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.4.2 Type II compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

6.5 Thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.6 Layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.7 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

7 Application ideas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7.1 Positive buck-boost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7.2 Inverting buck-boost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

2/44 Doc ID 15182 Rev 3

L7981 Contents

8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

9 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Doc ID 15182 Rev 3 3/44

Pin settings L7981

1 Pin settings

1.1 Pin connection

Figure 2. Pin connection (top view)

OUT

OUT

OUT

1.2 Pin description

OUT

SYNCH

SYNCH

SYNCH

SYNCH

EN

EN

COMP

COMP

COMP

COMP

V

V

V

V

CC

CC

CC

CC

GND

GND

GND

GND

FSW

FSW

FSW

FSW

FB

FB

FB

FB

Table 1. Pin description

N. Type Description

1 OUT Regulator output

Master/Slave synchronization. When it is left floating, a signal with a
phase shift of half a period respect to the power turn on is present at the
pin. When connected to an external signal at a frequency higher than the

2 SYNCH

3EN

4 COMP Error amplifier output to be used for loop frequency compensation

5FB

6F

SW

7 GND Ground

8VCCUnregulated DC input voltage

internal one, then the device is synchronized by the external signal, with
zero phase shift.

Connecting together the SYNCH pin of two devices, the one with higher
frequency works as master and the other one as slave; so the two
powers turn on have a phase shift of half a period.

A logical signal (active high) enable the device. With EN higher than 1.2
V the device is ON and with EN is lower than 0.3 V the device is OFF.

Feedback input. Connecting the output voltage directly to this pin the
output voltage is regulated at 0.6 V. To have higher regulated voltages an
external resistor divider is required from Vout to FB pin.

The switching frequency can be increased connecting an external
resistor from FSW pin and ground. If this pin is left floating the device
works at its free-running frequency of 250 kHz.

4/44 Doc ID 15182 Rev 3

L7981 Maximum ratings

2 Maximum ratings

Table 2. Absolute maximum ratings

Symbol Parameter Value Unit

Vcc Input voltage 30

OUT Output DC voltage -0.3 to V

FSW, COMP, SYNCH Analog pin -0.3 to 4

CC

V

EN Enable pin -0.3 to V

FB Feedback voltage -0.3 to 1.5

P

TOT

T

J

T

stg

3 Thermal data

Table 3. Thermal data

Symbol Parameter Value Unit

R

thJA

1. Package mounted on demonstration board.

Maximum thermal resistance
junction-ambient

CC

Power dissipation

< 60°C

at T

A

Junction temperature range -40 to 150 °C

Storage temperature range -55 to 150 °C

(1)

VFQFPN 1.5.

W

HSOP 2

VFQFPN 60

°C/W

HSOP 40

Doc ID 15182 Rev 3 5/44

Electrical characteristics L7981

4 Electrical characteristics

TJ=25 °C, VCC=12 V, unless otherwise specified.

Table 4. Electrical characteristics

Val ues

Symbol Parameter Test condition

Min Typ Max

Unit

V

CC

V

CCON

V

CCHYSVCC

Operating input voltage
range

Tu r n o n VCC threshold

UVLO Hysteresis

(1)

(1)

(1)

4.5 28

0.12 0.35

160 180

R

DSON

I

LIM

Mosfet on resistance

(1)

160 250

Maximum limiting current 3.7 4.2 4.7 A

Oscillator

225 250 275

V

F

FSW

SW

Switching frequency

(1)

220 275

FSW pin voltage 1.254 V

D Duty Cycle 0 100 %

F

ADJ

Adjustable switching
frequency

=33kΩ 1000 KHz

R

FSW

Dynamic characteristics

V

FB

Feedback voltage 4.5V<VCC<28V

(1)

0.593 0.6 0.607 V

DC characteristics

I

Q

I

QST-BY

Quiescent current

Total stand-by quiescent
current

Duty Cycle=0,
V

=0.8V

FB

20 30 μA

4.4

V

mΩ

KHz

2.4 mA

Enable

Device OFF level 0.3

EN threshold voltage

Device ON level 1.2

EN current EN=V

CC

Soft-start

FSW pin floating 7.4 8.2 9.1

T

SS

Soft-start duration

FSW=1MHz,

=33kΩ

R

FSW

Error amplifier

6/44 Doc ID 15182 Rev 3

V

7.5 10 μA

ms

2

L7981 Electrical characteristics

Table 4. Electrical characteristics (continued)

Val ues

Symbol Parameter Test condition

Min Typ Max

Unit

V

CH

V

CL

I

O SOURCE

I

O SINK

G

High level output voltage VFB<0.6V 3

Low level output voltage VFB>0.6V 0.1

Source COMP pin VFB=0.5V, V

Sink COMP pin VFB=0.7V, V

Open loop voltage gain

V

(2)

=1V 17 mA

COMP

=1V 25 mA

COMP

100 dB

Synchronization function

High input voltage 2 3.3

Low input voltage 1

Slave sink current V

Master output amplitude I

=2.9V 0.7 0.9 mA

SYNCH

SOURCE

=4.5mA 2.0 V

Output pulse width SYNCH floating 110

Input pulse width 70

Protection

Thermal shutdown 150

T

SHDN

1. Specification referred to TJ from -40 to +125°C. Specification in the -40 to +125°C temperature range are
assured by design, characterization and statistical correlation.

2. Guaranteed by design.

Hysteresis 30

V

V

ns

°C

Doc ID 15182 Rev 3 7/44

Functional description L7981

5 Functional description

The L7981 is based on a “voltage mode”, constant frequency control. The output voltage
V

is sensed by the feedback pin (FB) compared to an internal reference (0.6 V) providing

OUT

an error signal that, compared to a fixed frequency sawtooth, controls the on and off time of
the power switch.

The main internal blocks are shown in the block diagram in Figure 3. They are:

● A fully integrated oscillator that provides sawtooth to modulate the duty cycle and the

synchronization signal. Its switching frequency can be adjusted by an external resistor.
The voltage and frequency feed forward are implemented.

● The soft-start circuitry to limit inrush current during the start up phase.

● The voltage mode error amplifier

● The pulse width modulator and the relative logic circuitry necessary to drive the internal

power switch.

● The high-side driver for embedded p-channel power MOSFET switch.

● The peak current limit sensing block, to handle over load and short circuit conditions.

● A voltage regulator and internal reference. It supplies internal circuitry and provides a

fixed internal reference.

● A voltage monitor circuitry (UVLO) that checks the input and internal voltages.

● A thermal shutdown block, to prevent thermal run away.

Figure 3. Block diagram

TRIMMING UVLO

TRIMMING UVLOUVLO

EN

EN

COMP

COMP

0.6V

0.6V

SOFT-

SOFT-

START

START

EN

EN

FB

FB

REGULATOR

REGULATOR

REGULATOR

&

&

&

BANDGAP

BANDGAP

BANDGAP

1.254V 3.3V

1.254V 3.3V

THERMAL

THERMAL

SHUTDOWN

SHUTDOWN

E/A

E/A

OSCILLATOR

OSCILLATOR

FSW

FSW

PWM

PWM

GND

GND

PEAK

PEAK

CURRENT

CURRENT

LIMIT

LIMIT

SRQ

SRQ

SYNCH

SYNCH

&

&

PHASE SHIFT

PHASE SHIFT

SYNCH

SYNCH

DRIVER

DRIVER

VCC

VCC

OUT

OUT

8/44 Doc ID 15182 Rev 3

L7981 Functional description

5.1 Oscillator and synchronization

Figure 4 shows the block diagram of the oscillator circuit. The internal oscillator provides a

constant frequency clock. Its frequency depends on the resistor externally connect to FSW
pin. In case the FSW pin is left floating the frequency is 250 kHz; it can be increased as
shown in Figure 6 by external resistor connected to ground.

To improve the line transient performance, keeping the PWM gain constant versus the input
voltage, the voltage feed forward is implemented by changing the slope of the sawtooth
according to the input voltage change (see Figure 5.a).

The slope of the sawtooth also changes if the oscillator frequency is increased by the
external resistor. In this way a frequency feed forward is implemented (Figure 5.b) in order to
keep the PWM gain constant versus the switching frequency (see Section 6.4 for PWM gain
expression).

On the SYNCH pin the synchronization signal is generated. This signal has a phase shift of
180° with respect to the clock. This delay is useful when two devices are synchronized
connecting the SYNCH pin together. When SYNCH pins are connected, the device with
higher oscillator frequency works as Master, so the Slave device switches at the frequency
of the Master but with a delay of half a period. This minimizes the RMS current flowing
through the input capacitor [see L5988D Data sheet].

Figure 4. Oscillator circuit block diagram

Clock

ClockClock

FSW

FSW

The device can be synchronized to work at higher frequency feeding an external clock
signal. The synchronization changes the sawtooth amplitude, changing the PWM gain
(Figure 5.c). This changing has to be taken into account when the loop stability is studied.
To minimize the change of the PWM gain, the free running frequency should be set (with a
resistor on FSW pin) only slightly lower than the external clock frequency. This pre-adjusting
of the frequency will change the sawtooth slope in order to get negligible the truncation of
sawtooth, due to the external synchronization.

Clock

Clock

Generator

Generator

Synchronization

Synchronization

Ramp

Ramp

Generator

Generator

SYNCH

SYNCH

Sawtooth

Sawtooth

Doc ID 15182 Rev 3 9/44

Functional description L7981

Figure 5. Sawtooth: voltage and frequency feed forward; external synchronization

Figure 6. Oscillator frequency versus FSW pin resistor

10/44 Doc ID 15182 Rev 3

L7981 Functional description

5.2 Soft-start

The soft-start is essential to assure correct and safe start up of the step-down converter. It
avoids inrush current surge and makes the output voltage increases monothonically.

The soft -start is performed by a staircase ramp on the non-inverting input (V

REF

) of the

error amplifier. So the output voltage slew rate is:

Equation 1

VREF

⋅=

⎛⎞

1

------- -+

⎝⎠

R2

where SR

SR

is the slew rate of the non-inverting input, while R1and R2 is the resistor

VREF

OUT

SR

R1

divider to regulate the output voltage (see Figure 7). The soft-start stair case consists of 64
steps of 9.5 mV each one, from 0 V to 0.6 V. The time base of one step is of 32 clock cycles.
So the soft-start time and then the output voltage slew rate depend on the switching
frequency.

Figure 7. Soft-start scheme

Soft-start time results:

Equation 2

SS

TIME

32 64⋅

-----------------=

Fsw

For example with a switching frequency of 250kHz the SS

Doc ID 15182 Rev 3 11/44

TIME

is 8ms.

Functional description L7981

5.3 Error amplifier and compensation

The error amplifier (E/A) provides the error signal to be compared with the sawtooth to
perform the pulse width modulation. Its non-inverting input is internally connected to a 0.6 V
voltage reference, while its inverting input (FB) and output (COMP) are externally available
for feedback and frequency compensation. In this device the error amplifier is a voltage
mode operational amplifier so with high DC gain and low output impedance.

The uncompensated error amplifier characteristics are the following:

Table 5. Uncompensated error amplifier characteristics

Low frequency gain 100dB

GBWP 4.5MHz

Slew rate 7V/μs

Output voltage swing 0 to 3.3V

Maximum source/sink current 17mA/25mA

In continuos conduction mode (CCM), the transfer function of the power section has two
poles due to the LC filter and one zero due to the ESR of the output capacitor. Different
kinds of compensation networks can be used depending on the ESR value of the output
capacitor. In case the zero introduced by the output capacitor helps to compensate the
double pole of the LC filter a type II compensation network can be used. Otherwise, a type
III compensation network has to be used (see Chapter 6.4 for details about the
compensation network selection).

Anyway the methodology to compensate the loop is to introduce zeros to obtain a safe
phase margin.

12/44 Doc ID 15182 Rev 3

L7981 Functional description

5.4 Overcurrent protection

The L7981 implements the over current protection sensing current flowing through the
power MOSFET. Due to the noise created by the switching activity of the power MOSFET,
the current sensing is disabled during the initial phase of the conduction time. This avoids an
erroneous detection of a fault condition. This interval is generally known as “masking time”
or “blanking time”. The masking time is about 200 ns.

When the over current is detected, two different behaviors are possible depending on the
operating condition.

1. Output voltage in regulation. When the over current is sensed, the power MOSFET is

switched off and the internal reference (V
error amplifier, is set to zero and kept in this condition for a soft-start time (T
clock cycles). After this time, a new soft-start phase takes place and the internal
reference begins ramping (see Figure 8.a).

2. Soft-start phase. If the over current limit is reached the power MOSFET is turned off

implementing the pulse by pulse over current protection. During the soft-start phase,
under over current condition, the device can skip pulses in order to keep the output
current constant and equal to the current limit. If at the end of the “masking time” the
current is higher than the over current threshold, the power MOSFET is turned off and it
will skip one pulse. If, at the next switching on at the end of the “masking time” the
current is still higher than the threshold, the device will skip two pulses. This
mechanism is repeated and the device can skip up to seven pulses. While, if at the end
of the “masking time” the current is lower than the over current threshold, the number of
skipped cycles is decreased of one unit. At the end of soft-start phase the output
voltage is in regulation and if the over current persists the behavior explained above
takes place. (see Figure 8.b)

), that biases the non-inverting input of the

REF

SS

, 2048

So the over current protection can be summarized as an “hiccup” intervention when the
output is in regulation and a constant current during the soft-start phase. If the output is
shorted to ground when the output voltage is on regulation, the over current is triggered and
the device starts cycling with a period of 2048 clock cycles between “hiccup” (power
MOSFET off and no current to the load) and “constant current” with very short on-time and
with reduced switching frequency (up to one eighth of normal switching frequency). See

Figure 32. for short circuit behavior.

Doc ID 15182 Rev 3 13/44

Functional description L7981

Figure 8. Over current protection strategy

5.5 Enable function

The enable feature allows to put in stand-by mode the device.With EN pin lower than 0.3 V
the device is disabled and the power consumption is reduced to less than 30 µA. With EN
pin lower than 1.2 V, the device is enabled. If the EN pin is left floating, an internal pull down
ensures that the voltage at the pin reaches the inhibit threshold and the device is disabled.
The pin is also V

compatible.

CC

5.6 Hysteretic thermal shutdown

The thermal shutdown block generates a signal that turns off the power stage if the junction
temperature goes above 150°C. Once the junction temperature goes back to about 130°C,
the device restarts in normal operation. The sensing element is very close to the PDMOS
area, so ensuring an accurate and fast temperature detection.

14/44 Doc ID 15182 Rev 3

L7981 Application informations

6 Application informations

6.1 Input capacitor selection

The capacitor connected to the input has to be capable to support the maximum input
operating voltage and the maximum RMS input current required by the device. The input
capacitor is subject to a pulsed current, the RMS value of which is dissipated over its ESR,
affecting the overall system efficiency.

So the input capacitor must have a RMS current rating higher than the maximum RMS input
current and an ESR value compliant with the expected efficiency.

The maximum RMS input current flowing through the capacitor can be calculated as:

Equation 3

2

⋅

2D

I

RMSIO

-------------- -–

D

η

Where Io is the maximum DC output current, D is the duty cycle, η is the efficiency.
Considering η=1, this function has a maximum at D=0.5 and it is equal to Io/2.

2

D

------ -+⋅=

2

η

In a specific application the range of possible duty cycles has to be considered in order to
find out the maximum RMS input current. The maximum and minimum duty cycles can be
calculated as:

Equation 4

V

+

OUTVF

D

MAX

------------------------------------ -=

V

–

INMINVSW

and

Equation 5

V

+

OUTVF

--------------------------------------=

V

–

INMAXVSW

Where V

D

MIN

is the forward voltage on the freewheeling diode and VSW is voltage drop across

F

the internal PDMOS.

The peak to peak voltage across the input capacitor can be calculated as:

Equation 6

I

PP

-------------------------

CINFSW⋅

V

O

D

⎛⎞

1

--- -–

⎝⎠

η

D

--- -

D

1D–()⋅+⋅ ESR I

η

⋅+⋅=

O

where ESR is the equivalent series resistance of the capacitor.

Doc ID 15182 Rev 3 15/44

Application informations L7981

Given the physical dimension, ceramic capacitors can meet well the requirements of the
input filter sustaining an higher input RMS current than electrolytic / tantalum types. In this
case the equation of C

as a function of the target VPP can be written as follows:

IN

Equation 7

C

IN

I

O

-------------------------- -

VPPFSW⋅

D

⎛⎞

1

--- -–

⎝⎠

η

D

--- -

D

1D–()⋅+⋅⋅=

η

neglecting the small ESR of ceramic capacitors.
Considering η=1, this function has its maximum in D=0.5, thus, given the maximum peak to

peak input voltage (V

PP_MAX

), the minimum input capacitor (C

IN_MIN

) value is:

Equation 8

I

O

⋅⋅

PP_MAXFSW

Typically C
V

INMAX

C

IN_MIN

is dimensioned to keep the maximum peak-peak voltage in the order of 1% of

IN

----------------------------------------------- -=

2V

In Table 6. some multi layer ceramic capacitors suitable for this device are reported

Table 6. Input MLCC capacitors

Manufacture Series Cap value (μF) Rated voltage (V)

Ta i y o Yu d e n

Murata GRM32ER71H475K 4.7 50

UMK325BJ106MM-T 10 50

GMK325BJ106MN-T 10 35

A ceramic bypass capacitor, as close to the VCC and GND pins as possible, so that
additional parasitic ESR and ESL are minimized, is suggested in order to prevent instability
on the output voltage due to noise. The value of the bypass capacitor can go from 100 nF to
1 µF.

6.2 Inductor selection

The inductance value fixes the current ripple flowing through the output capacitor. So the
minimum inductance value in order to have the expected current ripple has to be selected.
The rule to fix the current ripple value is to have a ripple at 20%-40% of the output current.

In the continuos current mode (CCM), the inductance value can be calculated by the
following equation:

16/44 Doc ID 15182 Rev 3

L7981 Application informations

Equation 9

VINV

ΔI

L

–

OUT

----------------------------- -

L

T

⋅

ON

+

V

OUTVF

--------------------------- -

L

T

⋅==

OFF

Where T
time of the external diode (in CCM, F
fixed Vout, is obtained at maximum T
to calculate minimum duty). So fixing ΔI

is the conduction time of the internal high side switch and T

ON

=1/(TON + T

SW

that is at minimum duty cycle (see previous section

OFF

=20% to 30% of the maximum output current, the

L

minimum inductance value can be calculated:

Equation 10

V

+

OUTVF

MIN

--------------------------- -

ΔI

MAX

where F

is the switching frequency, 1/(TON + T

SW

For example for V
value to have ΔI

L

L

=5 V, VIN=24 V, IO=3 A and FSW=250 kHz the minimum inductance

OUT

= 30% of IO is about 18 μH.

The peak current through the inductor is given by:

Equation 11

I

LPK,

I

O

is the conduction

)). The maximum current ripple, at

OFF

1D

–

MIN

---------------------- -

⋅=

F

SW

).

OFF

ΔI

L

--------+=

2

OFF

So if the inductor value decreases, the peak current (that has to be lower than the current
limit of the device) increases. The higher is the inductor value, the higher is the average
output current that can be delivered, without reaching the current limit.

In the table below some inductor part numbers are listed.

Table 7. Inductors

Manufacturer Series Inductor value (μH) Saturation current (A)

Coilcraft

Wurth

SUMIDA

MSS1038 3.8 to 10 3.9 to 6.5

MSS1048 12 to 22 3.84 to 5.34

PD Type L 8.2 to 15 3.75 to 6.25

PD Type M 2.2 to 4.7 4 to 6

CDRH6D226/HP 1.5 to 3.3 3.6 to 5.2

CDR10D48MN 6.6 to 12 4.1 to 5.7

Doc ID 15182 Rev 3 17/44

Application informations L7981

6.3 Output capacitor selection

The current in the capacitor has a triangular waveform which generates a voltage ripple
across it. This ripple is due to the capacitive component (charge or discharge of the output
capacitor) and the resistive component (due to the voltage drop across its ESR). So the
output capacitor has to be selected in order to have a voltage ripple compliant with the
application requirements.

The amount of the voltage ripple can be calculated starting from the current ripple obtained
by the inductor selection.

Equation 12

ΔI

MAX

ΔV

OUT

ESR ΔI

⋅

Usually the resistive component of the ripple is much higher than the capacitive one, if the
output capacitor adopted is not a multi layer ceramic capacitor (MLCC) with very low ESR
value.

The output capacitor is important also for loop stability: it fixes the double LC filter pole and
the zero due to its ESR. In Chapter 6.4, it will be illustrated how to consider its effect in the
system stability.

MAX

------------------------------------ -+=

8C

⋅⋅

OUTfSW

For example with V
have a ΔV

OUT

=0.01·V

=5 V, VIN=24 V, ΔIL=0.9 A (resulting by the inductor value), in order to

OUT

, if the multi layer ceramic capacitor are adopted, 10uF are needed

OUT

and the ESR effect on the output voltage ripple can be neglected. In case of not negligible
ESR (electrolytic or tantalum capacitors), the capacitor is chosen taking into account its
ESR value. So in case of 330 µF with ESR=30 mΩ, the resistive component of the drop
dominates and the voltage ripple is 28 mV.

The output capacitor is also important to sustain the output voltage when a load transient
with high slew rate is required by the load. When the load transient slew rate exceeds the
system bandwidth the output capacitor provides the current to the load. So if the high slew
rate load transient is required by the application the output capacitor and system bandwidth
have to be chosen in order to sustain the load transient.

In the table below some capacitor series are listed.

Table 8. Output capacitors

Manufacturer Series Cap value (μF) Rated voltage (V) ESR (mΩ)

MURATA

PANASONIC

SANYO TPA/B/C 100 to 470 4 to 16 40 to 80

TDK C3225 22 to 100 6.3 < 5

GRM32 22 to 100 6.3 to 25 < 5

GRM31 10 to 47 6.3 to 25 < 5

ECJ 10 to 22 6.3 < 5

EEFCD 10 to 68 6.3 15 to 55

18/44 Doc ID 15182 Rev 3

L7981 Application informations

6.4 Compensation network

The compensation network has to assure stability and good dynamic performance. The loop
of the L7981 is based on the voltage mode control. The error amplifier is a voltage
operational amplifier with high bandwidth. So selecting the compensation network the E/A
will be considered as ideal, that is, its bandwidth is much larger than the system one.

The transfer functions of PWM modulator and the output LC filter are studied (see Figure

10.). The transfer function of the PWM modulator, from the error amplifier output (COMP

pin) to the OUT pin, results:

Equation 13

V

G

PW0

IN

-------- -=

V

s

where V

is the sawtooth amplitude. As seen in Chapter 5.1, the voltage feed forward

S

generates a sawtooth amplitude directly proportional to the input voltage, that is:

Equation 14

V

KVIN⋅=

S

In this way the PWM modulator gain results constant and equals to:

Equation 15

V

1

IN

-------- -

G

PW0

V

s

--- - 13===
K

The synchronization of the device with an external clock provided trough SYNCH pin can
modifies the PWM modulator gain (see Chapter 5.1 to understand how this gain changes
and how to keep it constant in spite of the external synchronization).

Figure 9. The error amplifier, the PWM modulation and the LC output filter

V

V

CC

CC

V

V

S

S

V

V

REF

FB

FB

REF

E/A

E/A

COMP

COMP

PWM

PWM

OUT

OUT

L

L

G

G

PW0

PW0

The transfer function on the LC filter is given by:

Doc ID 15182 Rev 3 19/44

ESR

ESR

G

G

LC

LC

C

C

OUT

OUT

Application informations L7981

Equation 16

GLCs()

1

------------------------------------------------------------------------ -=

1

----------------------------

++

2π Qf⋅LC⋅

s

s

------------------------- -+

2π f

⋅

zESR

⎛⎞

-------------------

⎝⎠

2π f

2

s

⋅

LC

where:

Equation 17

f

----------------------------------------------------------------------- -= f

LC

2π LC

1

⋅ 1

OUT

ESR

-------------- -+⋅⋅

R

OUT

zESR

------------------------------------------- -=,

2π ESR C

1

⋅⋅

OUT

Equation 18

R

LC

Q

LC

OUT

------------------------------------------------------------------------------------------

OUTROUT

OUTROUT

ESR+()⋅⋅ ⋅

ESR⋅⋅+

R

OUT

V

--------------=,=

I

OUT

OUT

As seen in Chapter 5.3 two different kind of network can compensate the loop. In the two
following paragraph the guidelines to select the Type II and Type III compensation network
are illustrated.

6.4.1 Type III compensation network

The methodology to stabilize the loop consists of placing two zeros to compensate the effect
of the LC double pole, so increasing phase margin; then to place one pole in the origin to
minimize the dc error on regulated output voltage; finally to place other poles far away the
zero dB frequency.

If the equivalent series resistance (ESR) of the output capacitor introduces a zero with a
frequency higher than the desired bandwidth (that is: 2π∗ESR∗COUT<1/BW), the type III
compensation network is needed. Multi Layer Ceramic capacitors (MLCC) have very low
ESR (<1mΩ), with very high frequency zero, so type III network is adopted to compensate
the loop.

In Figure 10 the type III compensation network is shown. This network introduces two zeros
(f

, fZ2) and three poles (fP0, fP1, fP2). They expression are:

Z1

Equation 19

------------------------------------------------= f

f

Z1

2π C

1

3R1R3

+()⋅⋅

Z2

⋅⋅

2π R

4C4

1

----------------------------- -=,

20/44 Doc ID 15182 Rev 3

L7981 Application informations

Equation 20

1

f

0= f

P0

----------------------------- -= f

P1

⋅⋅

2π R

3C3

P2

------------------------------------------- -=,,

2π R

1

C4C5⋅

--------------------

⋅⋅

4

C

+

4C5

Figure 10. Type III compensation network

In Figure 11 the Bode diagram of the PWM and LC filter transfer function (G
and the open loop gain (G

LOOP

(f) = G

· GLC(f) · G

PW0

(f)) are drawn.

TYPEIII

PW0

· GLC(f))

Figure 11. Open loop gain: module Bode diagram

The guidelines for positioning the poles and the zeroes and for calculating the component
values can be summarized as follow:

1. Choose a value for R

2. Choose a gain (R

, usually between 1 kΩ and 5 kΩ.

1

) in order to have the required bandwidth (BW), that means:

4/R1

Doc ID 15182 Rev 3 21/44

Application informations L7981

Equation 21

BW

--------- -

R

4

⋅⋅=

KR

f

LC

1

where K is the feed forward constant and 1/K is equals to 9.

3. Calculate C

by placing the zero at 50% of the output filter double pole frequency (fLC):

4

Equation 22

1

---------------------------=

C

4

⋅⋅

π R

4fLC

4. Calculate C

by placing the second pole at four times the system bandwidth (BW):

5

Equation 23

C

C

------------------------------------------------------------- -=

5

2π R4C44BW⋅ 1–⋅⋅⋅

4

5. Set also the first pole at four times the system bandwidth and also the second zero at

the output filter double pole:

Equation 24

R

R

3

1

-------------------------- -= C
4BW⋅

----------------- 1–
f

LC

3

1

---------------------------------------- -=,

2π R34BW⋅⋅⋅

The suggested maximum system bandwidth is equals to the switching frequency divided by

3.5 (F

For example with V

/3.5), anyway lower than 100 kHz if the FSW is set higher than 500 kHz.

SW

=5 V, VIN=24 V, IO=3 A, L=18 μH, C

OUT

=22 μF, ESR<1 mΩ, the type

OUT

III compensation network is:

4.99kΩ= R2680Ω= R3200Ω= R43.3kΩ= C33.3nF= C422nF= C5220pF=,,,, ,,

R

1

In Figure 12 is shown the module and phase of the open loop gain. The bandwidth is about
58 kHz and the phase margin is 50°.

22/44 Doc ID 15182 Rev 3

L7981 Application informations

Figure 12. Open loop gain bode diagram with ceramic output capacitor

Doc ID 15182 Rev 3 23/44

Application informations L7981

6.4.2 Type II compensation network

If the equivalent series resistance (ESR) of the output capacitor introduces a zero with a
frequency lower than the desired bandwidth (that is: 2π∗ESR∗COUT>1/BW), this zero helps
stabilize the loop. Electrolytic capacitors show not negligible ESR (>30 mΩ), so with this
kind of output capacitor the type II network combined with the zero of the ESR allows
stabilizing the loop.

In Figure 13 the type II network is shown.

Figure 13. Type II compensation network

The singularities of the network are:

----------------------------- -= f

f

Z1

⋅⋅

2π R

1

4C4

P0

0= f

P1

------------------------------------------- -=,,

2π R

1

C4C5⋅

--------------------

⋅⋅

4

C

+

4C5

In Figure 14 the Bode diagram of the PWM and LC filter transfer function (G
and the open loop gain (G

LOOP

(f) = G

· GLC(f) · G

PW0

(f)) are drawn.

TYPEII

PW0

· GLC(f))

24/44 Doc ID 15182 Rev 3

L7981 Application informations

Figure 14. Open loop gain: module bode diagram

The guidelines for positioning the poles and the zeroes and for calculating the component
values can be summarized as follow:

1. Choose a value for R

, usually between 1kΩ and 5kΩ, in order to have values of C4

1

and C5 not comparable with parasitic capacitance of the board.

2. Choose a gain (R

) in order to have the required bandwidth (BW), that means:

4/R1

Equation 25

Where f

is the ESR zero:

ESR

R

4

2

f

ESR

⎛⎞

----------- -

⎝⎠

⋅⋅⋅=

f

LC

BW

----------- -

f

ESR

V

-------- -

V

IN

S

R

1

Equation 26

f

ESR

------------------------------------------- -=

2π ESR C

1

⋅⋅

OUT

and Vs is the saw-tooth amplitude. The voltage feed forward keeps the ratio Vs/Vin constant.

3. Calculate C

by placing the zero one decade below the output filter double pole:

4

Equation 27

------------------------------ -=

⋅⋅

2π R

10

4fLC

4. Then calculate C

C

4

in order to place the second pole at four times the system bandwidth

3

(BW):

Doc ID 15182 Rev 3 25/44

Application informations L7981

Equation 28

C

------------------------------------------------------------- -=

C

5

2π R4C44BW⋅ 1–⋅⋅⋅

4

For example with V

=5 V, VIN=24 V, IO=3 A, L=18 μH, C

OUT

=330 μF, ESR=35 mΩ, the

OUT

type II compensation network is:

R

1.1k Ω= R2150Ω= R44.99k Ω= C482nF= C568pF=,, ,,

1

In Figure 15 is shown the module and phase of the open loop gain. The bandwidth is about
21 kHz and the phase margin is 45°.

26/44 Doc ID 15182 Rev 3

L7981 Application informations

Figure 15. Open loop gain bode diagram with electrolytic/tantalum output capacitor

Doc ID 15182 Rev 3 27/44

Application informations L7981

6.5 Thermal considerations

The thermal design is important to prevent the thermal shutdown of device if junction
temperature goes above 150°C. The three different sources of losses within the device are:

a) conduction losses due to the not negligible R

equal to:

Equation 29

of the power switch; these are

DSon

P

Where D is the duty cycle of the application and the maximum R
220 mΩ. Note that the duty cycle is theoretically given by the ratio between V

ON

R

()2D⋅⋅=

DSONIOUT

over temperature is

DSon

OUT

and VIN,
but actually it is quite higher to compensate the losses of the regulator. So the conduction
losses increases compared with the ideal case.

b) switching losses due to power MOSFET turn ON and OFF; these can be

calculated as:

Equation 30

T

+()

RISETFALL

Where T

RISE

P

SWVINIOUT

and T

FAL L

------------------------------------------ -

2

are the overlap times of the voltage across the power switch (VDS)

Fsw⋅⋅ ⋅ V

⋅⋅⋅==

INIOUTTSWFSW

and the current flowing into it during turn ON and turn OFF phases, as shown in Figure 16.
T

is the equivalent switching time. For this device the typical value for the equivalent

SW

switching time is 30 ns.

c) Quiescent current losses, calculated as:

Equation 31

VINIQ⋅=

P

Q

where I

The junction temperature T

is the quiescent current (IQ=2.4 mA).

Q

can be calculated as:

J

Equation 32

T

JTA

Where T

Rth

is the ambient temperature and P

A

is the equivalent thermal resistance junction to ambient of the device; it can be

JA

RthJAP

TOT

calculated as the parallel of many paths of heat conduction from the junction to the ambient.
For this device the path through the exposed pad is the one conducting the largest amount

28/44 Doc ID 15182 Rev 3

⋅+=

TOT

is the sum of the power losses just seen.

L7981 Application informations

of heat. The RthJA measured on the demonstration board described in the following
paragraph is about 60°C/W for the VFQFPN package and about 40°C/W for the HSOP
package.

Figure 16. Switching losses

6.6 Layout considerations

The PC board layout of switching DC/DC regulator is very important to minimize the noise
injected in high impedance nodes and interferences generated by the high switching current
loops.

In a step down converter the input loop (including the input capacitor, the power MOSFET
and the free wheeling diode) is the most critical one. This is due to the fact that the high
value pulsed current are flowing through it. In order to minimize the EMI, this loop has to be
as short as possible.

The feedback pin (FB) connection to external resistor divider is a high impedance node, so
the interferences can be minimized placing the routing of feedback node as far as possible
from the high current paths. To reduce the pick up noise the resistor divider has to be placed
very close to the device.

To filter the high frequency noise, a small bypass capacitor (220 nF - 1 µF) can be added as
close as possible to the input voltage pin of the device.

Thanks to the exposed pad of the device, the ground plane helps to reduce the thermal
resistance junction to ambient; so a large ground plane enhances the thermal performance
of the converter allowing high power conversion.

In Figure 17 a layout example is shown.

Doc ID 15182 Rev 3 29/44

Application informations L7981

Figure 17. Layout example

30/44 Doc ID 15182 Rev 3

L7981 Application informations

6.7 Application circuit

In Figure 18 the demonstration board application circuit is shown.

Figure 18. Demonstration board application circuit (rev 1.0)

Table 9. Component list (rev 1.0)

Reference Part number Description Manufacturer

C1 UMK325BJ106MM-T 10 μF, 50V Taiyo Yuden

C2 GRM32ER61E226KE15 22 μF, 25V Murata

C3 2.2 nF, 50V

C4 22 nF, 50V

C5 470 pF, 50V

C6 470 nF, 50V

R1 4.99 kΩ, 1%, 0.1W 0603

R2 1.1 kΩ, 1%, 0.1W 0603

R3 249 Ω, 1%, 0.1W 0603

R4 1.5 kΩ, 1%, 0.1W 0603

R5 220 kΩ, 1%, 0.1W 0603

D1 STPS3L40 3A DC, 40V STMicroelectronics

L1 MSS1038-103NL

10μH, 30%, 3.9A,

MAX

=35mΩ

DCR

Coilcraft

Doc ID 15182 Rev 3 31/44

Application informations L7981

Figure 19. PCB layout: L7981 and L7981A (component side)

Figure 20. PCB layout: L7981 and L7981A (bottom side)

Figure 21. PCB layout: L7981 and L7981A (front side)

32/44 Doc ID 15182 Rev 3

L7981 Application informations

Figure 22. Junction temperature vs. output

current

Figure 23. Junction temperature vs. output

current

Figure 24. Junction temperature vs. output

Figure 26. Efficiency vs.output current Figure 27. Efficiency vs. output current

current

95

90

85

80

Eff [%]

75

70

65

0.0 0.5 1.0 1 .5 2.0 2 .5 3.0

VIN=5V

VIN=12V

VIN=24V

Io [A]

V

=3.3 V

OUT

fsw=250 kHz

Figure 25. Efficiency vs. output current

92

VIN=12V

VIN=18V

87

VIN=24V

82

Eff [%]

77

V

=5.0 V

OUT

fsw=250 kHz

72

0.0 0.5 1.0 1.5 2.0 2.5 3.0

85

VIN=5V

80

VIN=12V

75

70

Eff [%]

65

60

55

50

0.0 0.5 1.0 1.5 2.0 2.5 3.0

VIN=24V

Io [A]

Io [A]

V

=1.8 V

OUT

fsw=250 kHz

Doc ID 15182 Rev 3 33/44

Application informations L7981

Figure 28. Load regulation Figure 29. Line regulation

1.6

1.4

1.2

1

[%]

FB

0.8

/V

FB

V

Δ

0.6

Vcc=5V

Vcc=12V

Vcc=24V

0.4

0.2

0

0 0.5 1 1.5 2 2.5 3

Figure 30. Load transient: from 0.4 A to 3 A Figure 31. Soft-start

V

OUT

200mV/div
AC coupled

0.1

0.0

-0.1

-0.2

[%]

FB

/V

FB

-0.3

V

Δ

-0.4

-0.5

-0.6
5 10152025

Io=1 A

Io=2 A

Io=3 A

IL1A/div

IL1A/div

[V]

V

CC

V

V

OUT

OUT

1V/div

0.5V/div

V

=24V

IN

=3.3V

V

OUT

=47uF

C

OUT

I

L

1A/div

L=10uH

=520k

F

SW

Time base 200us/div

Figure 32. Short-circuit behavior

OUT 10V/div

OUT 10V/div

1V/div

1V/div

V

V

OUT

OUT

SHORTED OUTPUT

SHORTED OUTPUT

IL1A/div

IL1A/div

Time base 5ms/div

Time base 5ms/div

Time base 1ms/div

Time base 1ms/div

34/44 Doc ID 15182 Rev 3

L7981 Application ideas

7 Application ideas

7.1 Positive buck-boost

The L7981 can implement the step up/down converter with a positive output voltage.

Figure 33. shows the schematic: one power MOSFET and one Schottky diode are added to

the standard buck topology to provide 12 V output voltage with input voltage from 4.5 V to 28
V.

Figure 33. Positive buck-boost regulator

The relationship between input and output voltage is:

Equation 33

D

-------------

V

OUTVIN

⋅=

1D–

So the duty cycle is:

Equation 34

V

D

OUT

----------------------------- -=

V

OUTVIN

+

The output voltage isn’t limited by the maximum operating voltage of the device (28 V),
because the output voltage is sense only through the resistor divider. The external power
MOSFET maximum drain to source voltage, must be higher than output voltage; the
maximum gate to source voltage must be higher than the input voltage (in Figure 33., if V

IN

is higher than 16V, the gate must be protected through zener diode and resistor)

The current flowing through the internal power MOSFET is transferred to the load only
during the OFF time, so according to the maximum DC switch current (3.0 A), the maximum
output current for the buck boost topology can be calculated from the following equation.

Doc ID 15182 Rev 3 35/44

Application ideas L7981

Equation 35

I

OUT

I

SW

-------------

1D–

3 A<=

where I

is the average current in the embedded power MOSFET in the on time.

SW

To chose the right value of the inductor and to manage transient output current, that for short
time can exceed the maximum output current calculated by Equation 35, also the peak
current in the power MOSFET has to be calculated. The peak current, showed in Equation

36, must be lower than the minimum current limit (3.7 A)

Equation 36

I

SW,PK

r

OUT

-------------

1D–

V

OUT

------------------------------------

I

LF

⋅⋅

OUT

1

⋅=

SW

r

-- -+ 3.7A<⋅=
2

2

1D–()

I

Where r is defined as the ratio between the inductor current ripple and the inductor DC
current:

So in the buck boost topology the maximum output current depends on the application
conditions (firstly input and output voltage, secondly switching frequency and inductor
value).

In Figure 34. the maximum output current for the above configuration is depicted varying the
input voltage from 4.5 V to 28 V.

The dashed line considers a more accurate estimation of the duty cycles given by Equation

37, where power losses across diodes, external power MOSFET, internal power MOSFET

are taken into account.

36/44 Doc ID 15182 Rev 3

L7981 Application ideas

Figure 34. Maximum output current according to max DC switch current (3.0 A):

V

=12 V

O

Equation 37

D

where V

is the voltage drop across diodes, VSW and V

D

power MOSFET.

7.2 Inverting buck-boost

The L7981 can implement the step up/down converter with a negative output voltage.

Figure 33. shows the schematic to regulate -5 V: no further external components are added

to the standard buck topology.

The relationship between input and output voltage is:

Equation 38

So the duty cycle is:

Equation 39

V

V

OUT

------------------------------------------------------------------------------------------- -=

V

INVSWVSWEVOUT

OUT

2VD⋅+

++––

-------------

VIN–

⋅=

1D–

2V⋅

D

across the internal and external

SWE

D

V

OUT

----------------------------- -=

D

V

–

OUTVIN

Doc ID 15182 Rev 3 37/44

Application ideas L7981

As in the positive one, in the inverting buck-boost the current flowing through the power
MOSFET is transferred to the load only during the OFF time. So according to the maximum
DC switch current (3.0 A), the maximum output current can be calculated from the Equation

35, where the duty cycle is given by Equation 39.

Figure 35. Inverting buck-boost regulator

The GND pin of the device is connected to the output voltage so, given the output voltage,
input voltage range is limited by the maximum voltage the device can withstand across VCC
and GND (28 V). Thus if the output is -5 V the input voltage can range from 4.5 V to 23 V.

As in the positive buck-boost, the maximum output current according to application
conditions is shown in Figure 36. The dashed line considers a more accurate estimation of
the duty cycles given by Equation 40, where power losses across diodes and internal power
MOSFET are taken into account.

Equation 40

V

–

---------------------------------------------------------------- -=

D

OUTVD

V–

INVSWVOUTVD

–+–

Figure 36. Maximum output current according to switch max peak current (3.0 A):

V

=-5 V

O

38/44 Doc ID 15182 Rev 3

L7981 Package mechanical data

8 Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.

®

packages, depending on their level of environmental compliance. ECOPACK

®

Doc ID 15182 Rev 3 39/44

Package mechanical data L7981

Table 10. VFQFPN8 (3x3x1.08mm) mechanical data

mm inch

Dim.

Min Typ Max Min Typ Max

A 0.80 0.90 1.00 0.0315 0.0354 0.0394

A1 0.02 0.05 0.0008 0.0020

A2 0.70 0.0276

A3 0.20 0.0079

b 0.18 0.23 0.30 0.0071 0.0091 0.0118

D 2.95 3.00 3.05 0.1161 0.1181 0.1200

D2 2.23 2.38 2.48 0.0878 0.0937 0.0976

E 2.95 3.00 3.05 0.1161 0.1181 0.1200

E2 1.65 1.70 1.75 0.0649 0.0669 0.0689

e 0.50 0.0197

L 0.35 0.40 0.45 0.0137 0.0157 0.0177

ddd 0.08 0.0031

Figure 37. Package dimensions

40/44 Doc ID 15182 Rev 3

L7981 Package mechanical data

Table 11. HSOP8 mechanical data

mm inch

Dim

Min Typ Max Min Typ Max

A 1.70 0.0669

A1 0.00 0.15 0.00 0.0059

A2 1.25 0.0492

b 0.31 0.51 0.0122 0.0201

c 0.17 0.25 0.0067 0.0098

D 4.80 4.90 5.00 0.1890 0.1929 0.1969

E 5.80 6.00 6.20 0.2283 0.2441

E1 3.80 3.90 4.00 0.1496 0.1575

e1.27

h 0.25 0.50 0.0098 0.0197

L 0.40 1.27 0.0157 0.0500

k0 8 0.3150

ccc 0.10 0.0039

Figure 38. Package dimensions

Doc ID 15182 Rev 3 41/44

Order codes L7981

9 Order codes

Table 12. Order codes

Order codes Package Packaging

L7981 VFQFPN8 Tube

L7981A HSOP8 Tube

L7981TR VFQFPN8) Tape and reel

L7981ATR HSOP8 Tape and reel

42/44 Doc ID 15182 Rev 3

L7981 Revision history

10 Revision history

Table 13. Document revision history

Date Revision Changes

19-Nov-2008 1 Initial release.

17-Mar-2009 2 Content reworked to improve readability, no technical changes

01-Jul-2010 3 Added application information

Doc ID 15182 Rev 3 43/44

L7981

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