Page 1
Single phase PWM controller with PowerGOOD
Features
■ Flexible power supply from 5V to 12V
■ Power conversion input as low as 1.5V
■ 0.8V internal reference
■ 0.8% output voltage accuracy
■ High-Current integrated drivers
■ PowerGOOD output
■ Sensorless and programmable OCP across
Low-Side R
■
OV / UV protections
■ VSEN disconnection protection
■ Oscillator internally fixed at 300kHz
■ LS-LESS to manage pre-bias start-up
■ Adjustable output voltage
■ Disable function
■ Internal Soft-Start
■ VFQFPN 10 package
Applications
dsON
L6728
VFQFPN 10
Description
L6728 is a single-phase step-down controller with
integrated high-current drivers that provides
complete control logic and protection to realize in
a simple way general DC-DC converters by using
a compact VFQFPN 10 package.
Device flexibility allows managing conversions
with power input V
supply voltage ranging from 5V to 12V.
L6728 provides simple control loop with voltage
mode EA. The integrated 0.8V reference allows
regulating output voltages with ±0.8% accuracy
over line and temperature variations. Oscillator is
internally fixed to 300kHz.
as low as 1.5V and device
IN
■ Memory and termination supply
■ Subsystem power supply (MCH, IOCH, PCI...)
■ CPU & DSP power supply
■ Distributed power supply
■ General DC / DC converters
L6728 provides programmable dual level over
current protection as well as over and under
voltage protection. Current information is
monitored across the Low-Side MOSFET RdsON
saving the use of expensive and spaceconsuming sense resistors.
PGOOD output easily provides real-time
information on Output Voltage status, through
VSEN dedicated output monitor.
Table 1. Device summary
Order codes Package Packaging
L6728 VFQFPN 10 Tube
L6728TR VFQFPN 10 Tape & Reel
September 2007 Rev 2 1/32
www.st.com
1
Page 2
Content L6728
Content
1 Typical application circuit and block diagram . . . . . . . . . . . . . . . . . . . . 4
1.1 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 Pins description and connection diagrams . . . . . . . . . . . . . . . . . . . . . . 5
2.1 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5 Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
6 Driver section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6.1 Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
7 Soft start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
7.1 Low-Side-Less Start up (LSLess) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
8 Over current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
8.1 Over current threshold setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
9 Output voltage setting and protections . . . . . . . . . . . . . . . . . . . . . . . . 14
10 Application details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
10.1 Compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
10.2 Layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
11 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
11.1 Inductor design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
11.2 Output capacitor(s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
11.3 Input capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2/32
Page 3
L6728 Content
12 20A demo board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
12.1 Board description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
12.1.1 Power input (Vin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
12.1.2 Output (Vout) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
12.1.3 Signal input (Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
12.1.4 Test points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
12.1.5 Board characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
13 5A demo board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
13.1 Board description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
13.1.1 Power input (Vin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
13.1.2 Output (Vout) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
13.1.3 Signal input (Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
13.1.4 Test points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
13.1.5 Board characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
14 Mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . 30
15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3/32
Page 4
Typical application circuit and block diagram L6728
1 Typical application circuit and block diagram
1.1 Application circuit
Figure 1. Typical application circuit
C
HF
VIN = 1.5V to 12V
L
C
BULK
Vout
C
OUT
LOAD
VCC = 5V to 12V
PGOOD
C
P
R
OS
C
DEC
R
PG
10
PGOOD
7
COMP
C
F
R
F
/ DIS
8
FB
VSEN
R
9
FB
VCC
GND
6
BOOT
UGATE
PHASE
L6728
LGATE
/ OC
5
R
1
3
2
4
OCSET
HS
LS
L6728 Reference Schematic
1.2 Block diagram
Figure 2. Block diagram
V
VSEN
PGOOD
OUT
OSCILLATOR
R
OS
MONITOR
300 kHz
L6728
CLOCK
R
FB
VCC
CONTROL LOGIC
PROTECTIONS
ERROR AMPLIFIER
V
OC
&
OCTH
BOOT
CROSS CONDUCTION
ADAPTIVE ANTI
HS
UGATE
PHASE
PWM
VCC
LS
LGATE
/ OC
GND
+
0.8V
I
OCSET
/ DIS
COMP
4/32
FB
Page 5
L6728 Pins description and connection diagrams
2 Pins description and connection diagrams
Figure 3. Pins connection (top view)
2.1 Pin descriptions
Table 2. Pins description
Pin # Name Function
HS Driver Supply.
1BOOT
Connect through a capacitor (100nF) to the floating node (LS-Drain) pin
and provide necessary bootstrap diode from VCC.
HS Driver return path, current-reading and adaptive-dead-time monitor.
2 PHASE
3 UGATE HS Driver Output. Connect directly to HS MOSFET gate.
4 LGATE / OC
5GND
6VCC
7 COMP / DIS
8FB
Connect to the LS drain to sense RdsON drop to measure the output
current. This pin is also used by the adaptive-dead-time control circuitry to
monitor when HS MOSFET is OFF.
LGATE. LS Driver Output. Connect directly to LS MOSFET gate.
OC. Over Current threshold set. During a short period of time following
VCC rising over UVLO threshold, a 10µA current is sourced from this pin.
Connect to GND with an R
Threshold. The resulting voltage at this pin is sampled and held internally
as the OC set point. Maximum programmable OC threshold is 0.55V. A
voltage greater than 0.6V activates an internal clamp and causes OC
threshold to be set at the maximum value.
All internal references, logic and drivers are connected to this pin.
Connect to the PCB ground plane.
Device and Drivers power supply.
Operative range from 5V to 12V. Filter with at least TBD nF MLCC to GND.
COMP. Error Amplifier Output. Connect with an R
compensate the device control loop.
DIS. The device can be disabled by pushing this pin lower than 0.75V(typ).
Setting free the pin, the device enables again.
Error Amplifier Inverting Input.
Connect with a resistor R
divider may be used to regulate voltages higher than the reference.
FB
resistor greater than 5kΩ to program OC
OCSET
- CF // CP to FB to
F
to the output regulated voltage. Output resistor
5/32
Page 6
Thermal data L6728
Table 2. Pins description (continued)
Pin # Name Function
Regulated voltage sense pin for OVP and UVP protections and PGOOD.
9 VSEN
Connect to the output regulated voltage, or to the output resistor divider if
the regulated voltage is higher than the reference.
Open Drain Output set free after SS has finished and pulled low when
10 PGOOD
VSEN is outside the relative window. Pull up to a voltage equal or lower
than VCC. If not used it can be left floating.
3 Thermal data
Table 3. Thermal data
Symbol Parameter Value Unit
R
R
T
T
P
th(JA)
th(JC)
MAX
STG
T
J
TOT
Thermal resistance junction to ambient
(Device soldered on 2s2p, 67mm x 69mm board)
45 °C/W
Thermal resistance junction to case 5 °C/W
Maximum junction temperature 150 °C
Storage temperature range -40 to 150 °C
Junction temperature range -40 to 125 °C
Maximum power dissipation at TA = 25°C 2.25 W
6/32
Page 7
L6728 Electrical specifications
4 Electrical specifications
4.1 Absolute maximum ratings
Table 4. Absolute maximum ratings
Symbol Parameter Value Unit
VCC to GND -0.3 to 15 V
V
BOOT, VUGATE
V
PHASE
V
LGATE
to PHASE
to GND
to GND; t < 200ns
to GND
to GND; t < 200ns
to GND -0.3 to VCC+0.3 V
FB, COMP, VSEN to GND -0.3 to 3.6 V
PGOOD to GND -0.3 to VCC+0.3 V
15
33
45
-5 to 18
-8 to 30
V
V
4.2 Electrical characteristics
Table 5. Electrical characteristics
(V
= 5V to 12V; T
CC
Symbol Parameter Test conditions Min. Typ. Max. Unit
Supply current and power-ON
I
CC
I
BOOT
VCC supply current UGATE and LGATE = OPEN 6 mA
BOOT supply current UGATE = OPEN; PHASE to GND 0.7 mA
VCC Turn-ON VCC Rising 4.1 V
UVLO
Hysteresis 0.2 V
OSCILLATOR
F
∆V
d
SW
OSC
MAX
Main oscillator accuracy 270 300 330 kHz
PWM ramp amplitude 1.4 V
Maximum duty cycle 80 %
Reference and error amplifier
Output voltage accuracy -0.8 - 0.8 %
A
0
DC Gain
(1)
GBWP Gain-bandwidth product
SR Slew-rate
(1)
= 0° to 70°C unless otherwise specified).
j
(1)
120 dB
15 MHz
8V/µs
DIS Disable threshold COMP Falling 0.70 0.85 V
7/32
Page 8
Electrical specifications L6728
Table 5. Electrical characteristics (continued)
(V
= 5V to 12V; T
CC
Symbol Parameter Test conditions Min. Typ. Max. Unit
Gate drivers
= 0° to 70°C unless otherwise specified).
j
I
UGATE
R
UGATE
I
LGATE
R
LGATE
HS source current BOOT - PHASE = 5V 1.5 A
HS sink resistance BOOT - PHASE = 5V 1.1 Ω
LS source current VCC = 5V 1.5 A
LS sink resistance VCC = 5V 0.65 Ω
Over-current protection
I
OCSET
V
OC_SW
OCSET current source
OC switch-over threshold V
Sourced from LGATE pin, during OC
setting phase.
LGATE/OC
rising 600 mV
91011µA
Over & under-voltage protections
VSEN Rising 0.90 1.00 1.10 V
OVP OVP threshold
un-latch, VSEN Falling 0.35 0.40 0.45 V
UVP UVP threshold VSEN Falling 0.50 0.60 0.70 V
VSEN VSEN bias current Sourced from VSEN 100 nA
PGOOD
Upper threshold VSEN Rising 0.860 0.890 0.920 V
PGOOD
Lower threshold VSEN Falling 0.680 0.710 0.740 V
V
PGOODL
1. Guaranteed by design, not subject to test.
PGOOD Voltage Low I
= -4mA 0.4 V
PGOOD
8/32
Page 9
L6728 Device description
5 Device description
L6728 is a single-phase PWM controller with embedded high-current drivers that provides
complete control logic and protections to realize in an easy and simple way a general DCDC step-down converter. Designed to drive N-channel MOSFETs in a synchronous buck
topology, with its high level of integration this 10-pin device allows reducing cost and size of
the power supply solution also providing real-time PGOOD in a compact VFQFPN10
3x3mm.
L6728 is designed to operate from a 5V or 12V supply. The output voltage can be precisely
regulated to as low as 0.8V with ±0.8% accuracy over line and temperature variations. The
switching frequency is internally set to 300kHz.
This device provides a simple control loop with a voltage-mode error-amplifier. The erroramplifier features a 15MHz gain-bandwidth product and 8V/µs slew rate, allowing high
regulator bandwidth for fast transient response.
To avoid load damages, L6728 provides over current protection as well as over voltage,
under voltage and feedback disconnection protection. The over current trip threshold is
programmable by a simple resistor connected from Lgate to GND. Output current is
monitored across Low-Side MOSFET R
consuming sense resistor. Output voltage is monitored through dedicated VSEN pin.
, saving the use of expensive and space-
dsON
L6728 implements soft-start increasing the internal reference in closed loop regulation.
Low-Side-Less feature allows the device to perform soft-start over pre-biased output
avoiding high current return through the output inductor and dangerous negative spike at the
load side.
L6728 is available in a compact VFQFN10 3x3mm package with exposed pad.
9/32
Page 10
Driver section L6728
6 Driver section
The integrated high-current drivers allow using different types of power MOSFET (also
multiple MOSFETs to reduce the equivalent R
The driver for the high-side MOSFET uses BOOT pin for supply and PHASE pin for return.
The driver for low-side MOSFET uses the VCC pin for supply and GND pin for return.
The controller embodies an anti-shoot-through and adaptive dead-time control to minimize
low side body diode conduction time, maintaining good efficiency while saving the use of
Schottky diode:
● to check high-side MOSFET turn off, PHASE pin is sensed. When the voltage at
PHASE pin drops down, the low-side MOSFET gate drive is suddenly applied;
● to check low-side MOSFET turn off, LGATE pin is sensed. When the voltage at LGATE
has fallen, the high-side MOSFET gate drive is suddenly applied.
If the current flowing in the inductor is negative, voltage on PHASE pin will never drop. To
allow the low-side MOSFET to turn-on even in this case, a watchdog controller is enabled: if
the source of the high-side MOSFET doesn't drop, the low side MOSFET is switched on so
allowing the negative current of the inductor to recirculate. This mechanism allows the
system to regulate even if the current is negative.
), maintaining fast switching transition.
dsON
Power conversion input is flexible: 5V, 12V bus or any bus that allows the conversion (See
maximum duty cycle limitations) can be chosen freely.
6.1 Power dissipation
L6728 embeds high current MOSFET drivers for both high side and low side MOSFETs: it is
then important to consider the power that the device is going to dissipate in driving them in
order to avoid overcoming the maximum junction operative temperature.
Two main terms contribute in the device power dissipation: bias power and drivers' power.
● Device Bias Power (P
supply pins and it is simply quantifiable as follow (assuming to supply HS and LS
drivers with the same VCC of the device):
● Drivers power is the power needed by the driver to continuously switch on and off the
external MOSFETs; it is a function of the switching frequency and total gate charge of
the selected MOSFETs. It can be quantified considering that the total power P
dissipated to switch the MOSFETs (easy calculable) is dissipated by three main
factors: external gate resistance (when present), intrinsic MOSFET resistance and
intrinsic driver resistance. This last term is the important one to be determined to
calculate the device power dissipation. The total power dissipated to switch the
MOSFETs results:
) depends on the static consumption of the device through the
DC
P
DC
V
CCICCIBOOT
+()⋅=
SW
P
SW
External gate resistors helps the device to dissipate the switching power since the same
power P
resulting in a general cooling of the device.
10/32
will be shared between the internal driver impedance and the external resistor
SW
F
SW
Q
gHSVBOOT
Q
⋅+⋅()⋅=
gLSVCC
Page 11
L6728 Soft start
7 Soft start
L6728 implements a soft start to smoothly charge the output filter avoiding high in-rush
currents to be required from the input power supply. The device gradually increases the
internal reference from 0V to 0.8V in 4.5ms (typ.), in closed loop regulation, linearly charging
the output capacitors to the final regulation voltage.
In the event of an over current triggering during soft start, the over current logic will override
the soft start sequence and will shut down the PWM logic and both the high side and low
side gates. This condition is latched, cycle VCC to recover.
The device begins soft start phase only when VCC power supply is above UVLO threshold
and over current threshold setting phase has been completed.
7.1 Low-Side-Less Start up (LSLess)
In order to avoid any kind of negative undershoot and dangerous return from the load during
start-up, L6728 performs a special sequence in enabling LS driver to switch: during the softstart phase, the LS driver results disabled (LS = OFF) until the HS starts to switch. This
avoid the dangerous negative spike on the output voltage that can happen if starting over a
pre-biased output.
If the output voltage is pre-biased to a voltage higher than the final one, the HS would never
start to switch. In this case, at the end of soft start time, LS is enabled and discharge the
output to the final regulation value.
This particular feature of the device masks the LS turn-on only from the control loop point of
view: protections by-pass this turning ON the LS mosfet in case of need.
Figure 4. LSLess Startup (left) vs. Non-LSLess Startup (right)
11/32
Page 12
Over current protection L6728
8 Over current protection
The over current function protects the converter from a shorted output or overload, by
sensing the output current information across the Low Side MOSFET drain-source onresistance, R
the use of expensive and space-consuming sense resistors.
. This method reduces cost and enhances converter efficiency by avoiding
dsON
The low side R
current sense is implemented by comparing the voltage at the PHASE
dsON
node when LS MOSFET is turned on with the programmed OCP thresholds voltages,
internally held. If the monitored voltage is bigger than these thresholds, an Over Current
Event is detected.
For maximum safety and load protection, L6728 implements a Dual Level Over Current
Protection System:
st
● 1
level threshold: it is the user externally set threshold. If the monitored voltage on
PHASE exceeds this threshold, a 1
st
level over current is detected. If four 1st level OC
events are detected in four consecutive switching cycles, Over Current Protection will
be triggered.
nd
● 2
level threshold: it is an internal threshold whose value is equal to 1st level
threshold multiplied by a factor 1.5. If the monitored voltage on PHASE exceeds this
threshold, Over Current Protection will be triggered immediately.
When Over Current Protection is triggered, the device turns off both LS and HS MOSFETs
in a latched condition.
To recover from over current protection triggered condition, VCC power supply must be
cycled.
12/32
Page 13
L6728 Over current protection
8.1 Over current threshold setting
L6728 allows to easily program a 1st level Over Current Threshold ranging from 50mV to
550mV, simply by adding a resistor (R
will be automatically set accordingly.
During a short period of time (about 5ms) following VCC rising over UVLO threshold, an
internal 10µA current (I
across R
level Over Current Threshold. The OC setting procedure overall time length is about 5ms.
. This voltage drop will be sampled and internally held by the device as 1st
OCSET
) is sourced from LGATE pin, determining a voltage drop
OCSET
) between LGATE and GND. 2nd level threshold
OCSET
Connecting a R
threshold will be:
I
I
OCth1
the programmed 2
I
OCth2
R
OCSET
In case R
values: an internal safety clamp on LGATE is triggered as soon as LGATE voltage reaches
600mV, setting the maximum threshold and suddenly ending OC setting phase.
OCSETROCSET
------------------------------------------- -=
1.5
values range from 5kΩ to 55kΩ.
OCSET
resistor between LGATE and GND, the programmed 1st level
OCSET
⋅
R
dsON
nd
level threshold will be:
I
OCSETROCSET
------------------------------------------- -
⋅=
is not connected, the device sets the OCP thresholds to the maximum
R
⋅
dsON
13/32
Page 14
Output voltage setting and protections L6728
9 Output voltage setting and protections
L6728 is capable to precisely regulate an output voltage as low as 0.8V. In fact, the device
comes with a fixed 0.8V internal reference that guarantee the output regulated voltage to be
within ±0.8% tolerance over line and temperature variations (excluding output resistor
divider tolerance, when present).
Output voltage higher than 0.8V can be easily achieved by adding a resistor R
FB pin and ground. Referring to Figure 1, the steady state DC output voltage will be:
R
V
OUT
where V
L6728 monitors the voltage at VSEN pin and compares it to internal reference voltage in
order to provide Under Voltage and Over Voltage protections as well as PGOOD signal.
According to the level of VSEN, different actions are performed from the controller:
● PGOOD
If the voltage monitored through VSEN exits from the PGOOD window limits, the device
de-asserts the PGOOD signal still continuing switching and regulating. PGOOD is
asserted at the end of the soft-start phase.
● Under Voltage Protection
If the voltage at VSEN pin drops below UV threshold, the device turns off both HS and
LS MOSFETs, latching the condition. Cycle VCC to recover.
● Over Voltage Protection
If the voltage at VSEN pin rises over OV threshold (1V typ), over voltage protection
turns off HS MOSFET and turns on LS MOSFET. The LS MOSFET will be turned off as
soon as VSEN goes below Vref/2 (0.4V). The condition is latched, cycle VCC to
recover. Notice that, even if the device is latched, the device still controls the LS
MOSFET and can switch it on whenever VSEN rises above 0.4V.
● Feedback Disconnection Protection
In order to provide load protection even if VSEN pin is not connected, a 100nA bias
current is always sourced from this pin. If VSEN pin is not connected, this current will
permanently pull it up causing the device to detect an OV: thus LS will be latched on
preventing output voltage from rising out of control.
REF
is 0.8V.
V
⎛⎞
⋅=
REF
⎝⎠
FB
1
-----------+
R
OS
between
OS
14/32
Page 15
L6728 Application details
10 Application details
10.1 Compensation network
The control loop showed in Figure 5 is a voltage mode control loop. The output voltage is
regulated to the internal reference (when present, offset resistor between FB node and GND
can be neglected in control loop calculation).
Error Amplifier output is compared to oscillator saw-tooth waveform to provide PWM signal
to the driver section. PWM signal is then transferred to the switching node with V
amplitude. This waveform is filtered by the output filter.
The converter transfer function is the small signal transfer function between the output of the
EA and V
resonance and a zero at F
modulator is simply the input voltage V
∆V
OSC
. This function has a double pole at frequency FLC depending on the L-C
OUT
depending on the output capacitor ESR. The DC Gain of the
ESR
divided by the peak-to-peak oscillator voltage
IN
.
Figure 5. PWM control loop
V
OSC
∆V
OSC
_
+
PWM
COMPARA TOR
ERROR
AMPLIFIE R
+
_
V
IN
L R
C
OUT
ESR
REF
R
FB
V
OUT
IN
OUT
R
C
F
F
C
P
The compensation network closes the loop joining V
function ideally equal to -Z
F/ZFB
.
C
R
S
S
Z
Z
F
FB
and EA output with transfer
OUT
Compensation goal is to close the control loop assuring high DC regulation accuracy, good
dynamic performances and stability. To achieve this, the overall loop needs high DC gain,
high bandwidth and good phase margin.
High DC gain is achieved giving an integrator shape to compensation network transfer
function. Loop bandwidth (F
stability, it should not exceed F
) can be fixed choosing the right RF/RFB ratio, however, for
0dB
/2π. To achieve a good phase margin, the control loop gain
SW
has to cross 0dB axis with -20dB/decade slope.
As an example, Figure 6 shows an asymptotic bode plot of a type III compensation.
15/32
Page 16
Application details L6728
Figure 6. Example of type III compensation.
Gain
[dB]
open loop
EA gain
FZ1F
Z2FP1FP2
closed
loop ga in
compensation
gain
open loop
converter gain
0dB
● Open loop converter singularities:
F
0dB
F
F
LC
ESR
20 log ( RF/RFB)
20log (V
/∆V
IN
Log (Fre q)
OSC
)
F
a)
LC
F
b)
ESR
● Compensation Network singularities frequencies:
F
a)
Z1
F
b)
Z2
F
c)
P1
F
d)
P2
1
--------------------------------- -=
2π LC
⋅
OUT
------------------------------------------- -=
2π C
------------------------------=
2π R
---------------------------------------------------- -=
2π R
--------------------------------------------------=
2π R
------------------------------ -=
2π RSC
1
ESR⋅⋅
OUT
1
⋅⋅
FCF
1
+()C
⋅⋅
FBRS
S
1
CFCP⋅
⎛⎞
-------------------- -
⋅⋅
F
⎝⎠
C
+
FCP
1
⋅⋅
S
To place the poles and zeroes of the compensation network, the following suggestions may
be followed:
a) Set the gain R
in order to obtain the desired closed loop regulator bandwidth
F/RFB
according to the approximated formula (suggested values for R
some kΩ):
∆V
F
R
----------
R
16/32
FB
0dB
F
------------
F
LC
------------------ -
⋅=
V
OSC
IN
is in the range of
FB
Page 17
L6728 Application details
b) Place FZ1 below FLC (typically 0.5*FLC):
1
-----------------------------=
C
F
⋅⋅
π R
FFLC
c) Place F
C
P
d) Place F
R
S
C
S
at F
P1
ESR
----------------------------------------------------------=
2π RFCFF
Z2
---------------------------=
F
----------------- - 1–
2F⋅
-------------------------------=
⋅⋅
π R
C
at FLC and FP2 at half of the switching frequency:
R
FB
SW
LC
1
SFSW
e) Check that compensation network gain is lower than open loop EA gain before
;
F
0dB
f) Check phase margin obtained (it should be greater than 45°) and repeat if
necessary.
10.2 Layout guidelines
L6728 provides control functions and high current integrated drivers to implement highcurrent step-down DC-DC converters. In this kind of application, a good layout is very
important.
The first priority when placing components for these applications has to be reserved to the
power section, minimizing the length of each connection and loop as much as possible. To
minimize noise and voltage spikes (EMI and losses) power connections (highlighted in
Figure 7) must be a part of a power plane and anyway realized by wide and thick copper
traces: loop must be anyway minimized. The critical components, i.e. the power MOSFETs,
must be close one to the other. The use of multi-layer printed circuit board is recommended.
:
F
1–⋅⋅⋅
ESR
The input capacitance (C
), or at least a portion of the total capacitance needed, has to be
IN
placed close to the power section in order to eliminate the stray inductance generated by the
copper traces. Low ESR and ESL capacitors are preferred, MLCC are suggested to be
connected near the HS drain.
Use proper VIAs number when power traces have to move between different planes on the
PCB in order to reduce both parasitic resistance and inductance. Moreover, reproducing the
same high-current trace on more than one PCB layer will reduce the parasitic resistance
associated to that connection.
Connect output bulk capacitors (C
) as near as possible to the load, minimizing parasitic
OUT
inductance and resistance associated to the copper trace, also adding extra decoupling
capacitors along the way to the load when this results in being far from the bulk capacitors
bank.
17/32
Page 18
Application details L6728
Figure 7. Power connections (heavy lines)
V
IN
UGATE
PHASE
C
IN
L
L6728
C
LGATE
GND
OUT
LOAD
Gate traces and phase trace must be sized according to the driver RMS current delivered to
the power MOSFET. The device robustness allows managing applications with the power
section far from the controller without losing performances. Anyway, when possible, it is
recommended to minimize the distance between controller and power section.
Small signal components and connections to critical nodes of the application, as well as
bypass capacitors for the device supply, are also important. Locate bypass capacitor (VCC
and Bootstrap capacitor) and feedback compensation components as close to the device as
practical. For over current programmability, place R
close to the device and avoid
OCSET
leakage current paths on COMP/OC pin, since the internal current source is only 60µA.
Systems that do not use Schottky diode in parallel to the Low-Side MOSFET might show big
negative spikes on the phase pin. This spike must be limited within the absolute maximum
ratings (for example, adding a gate resistor in series to HS MOSFET gate), as well as the
positive spike, but has an additional consequence: it causes the bootstrap capacitor to be
over-charged. This extra-charge can cause, in the worst case condition of maximum input
voltage and during particular transients, that boot-to-phase voltage overcomes the absolute
maximum ratings also causing device failures. It is then suggested in this cases to limit this
extra-charge by adding a small resistor in series to the boot capacitor (one resistor in series
to BOOT).
Figure 8. Drivers turn-on and turn-off paths
LS DRIVER LS MOSFET
VCC
C
GD
R
GATERINT
LGATE
C
GS
GND
18/32
C
HS DRIVER HS MOSFET
BOOT
C
GD
R
GATERINT
UGATE
DS
PHASE
C
GS
C
DS
Page 19
L6728 Application information
11 Application information
11.1 Inductor design
The inductance value is defined by a compromise between the dynamic response time, the
efficiency, the cost and the size. The inductor has to be calculated to maintain the ripple
current (∆I
value can be calculated with the following relationship:
) between 20% and 30% of the maximum output current (typ). The inductance
L
VINV
----------------------------- -
L
F
SW∆IL
Where F
–
SW
V
OUT
OUT
--------------
⋅=
⋅
V
IN
is the switching frequency, VIN is the input voltage and V
is the output
OUT
voltage. Figure 9 shows the ripple current vs. the output voltage for different values of the
inductor, with V
= 5V and VIN = 12V.
IN
Increasing the value of the inductance reduces the current ripple but, at the same time,
increases the converter response time to a dynamic load change. The response time is the
time required by the inductor to change its current from initial to final value. Until the inductor
has not finished its charging time, the output current is supplied by the output capacitors.
Minimizing the response time can minimize the output capacitance required. If the
compensation network is well designed, during a load variation the device is able to set a
duty cycle value very different (0% or 80%) from steady state one. When this condition is
reached, the response time is limited by the time required to change the inductor current.
Figure 9. Inductor current ripple vs. output voltage
10
8
Vin=12V, L=1uH
6
Vin=12V, L=2uH
4
2
Inductor current ripple [A]
0
012345
Output voltage [V]
19/32
Vin=5V, L=500nH
Vin=5V, L=1.5uH
Page 20
Application information L6728
11.2 Output capacitor(s)
The output capacitors are basic components to define the ripple voltage across the output
and for the fast transient response of the power supply. They depend on the output voltage
ripple requirements, as well as any output voltage deviation requirement during a load
transient.
During steady-state conditions, the output voltage ripple is influenced by both the ESR and
capacitive value of the output capacitors as follow:
∆V
OUT_ESR
∆V
OUT_C
Where ∆I
∆ILESR⋅=
1
-------------------------------------- -
∆I
⋅=
L
8C
⋅⋅
OUTFSW
is the inductor current ripple. In particular, the expression that defines ∆V
L
OUT_C
takes in consideration the output capacitor charge and discharge as a consequence of the
inductor current ripple.
During a load variation, the output capacitors supplies the current to the load or absorb the
current stored into the inductor until the converter reacts. In fact, even if the controller
recognizes immediately the load transient and sets the duty cycle at 80% or 0%, the current
slope is limited by the inductor value. The output voltage has a drop that also in this case
depends on the ESR and capactive charge/discharge as follow:
∆V
OUT_ESR
∆V
OUT_C
Where ∆V
D
( for the load appliance or V
MAXVINVOUT
∆I
∆I
OUT
is the voltage applied to the inductor during the transient response
L
–⋅
ESR⋅=
OUT
L ∆I
⋅
------------------------------------- -
⋅=
2C
⋅⋅
OUT∆VL
OUT
for the load removal).
OUT
MLCC capacitors have typically low ESR to minimize the ripple but also have low
capacitance that do not minimize the voltage deviation during dynamic load variations. On
the contrary, electrolytic capacitors have big capacitance to minimize voltage deviation
during load transients while they does not show the same ESR values of the MLCC resulting
then in higher ripple voltages. For these reasons, a mix between electrolytic and MLCC
capacitor is suggeted to minimize ripple as well as reducing voltage deviation in dynamic
mode.
11.3 Input capacitors
The input capacitor bank is designed considering mainly the input rms current that depends
on the output deliverable current (I
I
rmsIOUT
D1D–()⋅⋅=
The equation reaches its maximum value, I
input capacitor ESR and, in worst case, are:
PESRI
20/32
⋅=
OUT
2
2⁄()
) and the duty-cycle (D) for the regulation as follow:
OUT
/2, with D = 0.5. The losses depends on the
OUT
Page 21
L6728 20A demo board
12 20A demo board
L6728 demo board realizes in a four-layer PCB a step-down DC/DC converter and shows
the operation of the device in a general purpose application. The input voltage can range
from 5V to 12V buses and the output voltage is fixed at 1.25V. The application can deliver an
output current up to 30A. The switching frequency is 300 KHz.
Figure 10. L6728 - 20A demo board (left) and components placement (right)
Figure 11. L6728 - top (left) and bottom (right) layers
21/32
Page 22
20A demo board L6728
Figure 12. 20A demo board schematic
22/32
Page 23
L6728 20A demo board
Table 6. 20A demo board - bill of material
Qty Reference Description Package
Capacitors
2 C1, C2 Electrolityc Capacitor 1800µF 16V Radial 10 x 25mm
7 C3 to C9 Not Mounted na
1 C10 MLCC, 100nF, 16V, X7R SMD0603
3 C11 to C13 MLCC, 4.7µF, 16V, X7R SMD1206
2C14, C38 MLCC, 1µF, 16V, X7R SMD0805
C16, C17, C21, C22, C25, C26,
13
C27, C28, C29, C30, C34
2 C15, C19 MLCC, 10µF, 16V, X5R SMD1206
2 C18, C20 Electrolityc Capacitor 2200µF 6.3V Radial 10 x 20mm
1 C23 MLCC, 6.8nF, X7R
1 C35 MLCC, 68pF, X7R
2 C36, C37 Not Mounted na
Not Mounted na
SMD06031 C24 MLCC, 33nF, X7R
Resistors
4 R1, R2, R20, R17 Resistor, 3R3, 1/16W, 1% SMD0603
4 R3, R5, R11, R16 Resistor, 0R, 1/8W, 1%
1 R4 Resistor, 1R8, 1/8W, 1%
5 R10, R12, R14, R15, R21 Not Mounted na
2 R6, R9 Resistor, 2K2, 1/16W, 1%
2 R8, R13 Resistor, 3K9, 1/16W, 1%
1 R7 Resistor, 18K, 1/16W, 1%
1 R19 Resistor, 22K, 1/16W, 1%
1 R18 Resistor, 20K, 1/16W, 1%
Inductor
1L1
Active Components
1 D1 Diode, 1N4148 SOT23
3 Q1 to Q4 Not Mounted na
1 Q5 STD70NH02L
1 Q6 STD80NH02L
1 U1 Controller, L6728 DFN10, 3x3mm
Inductor, 1.25µH, T60-18, 6Turns,
2xAWG18
SMD0805
SMD0603
na
DPACK
23/32
Page 24
20A demo board L6728
12.1 Board description
12.1.1 Power input (Vin)
This is the input voltage for the power conversion. The High-Side drain is connected to this
input. This voltage can range from 1.5V to 12Vbus.
If the voltage is between 4.5V and 12V it can supply also the device (through the Vcc pin)
and in this case the R16 (0Ohm) resistor must be present.
12.1.2 Output (Vout)
The output voltage is fixed at 1.25V but it can be changed by replacing the resistors R8
(sense partition lower resistor ) and R13 (feedback partition lower resistor). The overcurrent-protection limit is set at 15A but it can be changed by replacing the resistors R18.
12.1.3 Signal input (Vcc)
Using the input voltage Vin to supply the controller no power is required at this input.
However the controller can be supplied separately from the power stage through the Vcc
input (4.5-12V) and, in this case, the R16 (0Ohm) resistor must be unsoldered.
12.1.4 Test points
Several test points are provided to have easy access at all important signal characterizing
the device:
– COMP: the output of the error amplifier;
– FB: the inverting input of the error amplifier;
– PGOOD: signaling the regular functioning (active high);
– VGDHS: the Bootstrap Diode Anode;
– PHASE: Phase node;
– LGATE: Low-Side gate pin of the device;
– HGATE: High-Side gate pin of the device.
24/32
Page 25
L6728 20A demo board
12.1.5 Board characterization
Figure 13. 20A demo board efficiency
100
95
90
85
80
75
70
65
Efficiency [%]
60
55
50
0 2 4 6 8 10121416182022
Output Current [A]
Vin=12V, Vout=1.25V
Vin=5V, Vout=1.25V
Vin=12V, Vout=2.5V
Vin=5V, Vout=2.5V
25/32
Page 26
5A demo board L6728
13 5A demo board
L6728 demo board realizes in a two-layer PCB a step-down DC/DC converter and shows
the operation of the device in a general-purpose low-current application. The input voltage
can range from 5V to 12V buses and the output voltage is fixed at 1.25V. The application
can deliver an output current in excess of 5A. The switching frequency is 300 KHz.
Figure 14. L6728 - 5A demo board (left) and components placement (right)
Figure 15. L6728 - 5A demo board top (left) and bottom (right) layers
26/32
Page 27
L6728 5A demo board
Figure 16. 5A demo board schematic
27/32
Page 28
5A demo board L6728
Table 7. 5A demo board - bill of material
Qty Reference Description Package
Capacitors
2 C12, C51 MLCC, 10µF, 16V, X5R SMD1206
1 C10 MLCC, 100nF, 16V, X7R SMD0603
2 C14, C38 MLCC, 1µF, 16V, X7R SMD0805
1C39 MLCC, 22µF, 6.3V, X5R SMD1206
1 C30 330µF, 6.3V, 6TPF330M9L SMD7434
2 C23, C36 MLCC, 6.8nF, X7R
SMD06031 C24 MLCC, 68nF, X7R
1 C35 MLCC, 220pF, X7R
Resistors
3 R1, R2, R17 Resistor, 3R3, 1/16W, 1% SMD0603
3 R3, R5, R16 Resistor, 0R, 1/8W, 1%
SMD08051 R4 Resistor, 1R8, 1/8W, 1%
1 R14 Resistor, 15R, 1/8W, 1%
2 R6, R9 Resistor, 2K2, 1/16W, 1%
2 R8, R13 Resistor, 3K9, 1/16W, 1%
1 R7 Resistor, 18K, 1/16W, 1%
1 R19 Resistor, 22K, 1/16W, 1%
1 R18 Resistor, 20K, 1/16W, 1%
Inductor
1L1
Active Components
1 D1 Diode, BAT54 SOT23
1 Q5 STS9D8NH3LL SO8
1 U1 Controller, L6728 DFN10, 3x3mm
13.1 Board description
13.1.1 Power input (Vin)
Inductor, 2,20µH,
WURTH 744324220LF
SMD0603
na
This is the input voltage for the power conversion. The High-Side drain is connected to this
input. This voltage can range from 1.5V to 12Vbus.
If the voltage is between 4.5V and 12V it can supply also the device (through the Vcc pin)
and in this case the R16 (0Ohm) resistor must be present.
28/32
Page 29
L6728 5A demo board
13.1.2 Output (Vout)
The output voltage is fixed at 1.25V but it can be changed by replacing the resistors R8
(sense partition lower resistor ) and R13 (feedback partition lower resistor). The overcurrent-protection limit is set at 15A but it can be changed by replacing the resistors R18.
13.1.3 Signal input (Vcc)
Using the input voltage Vin to supply the controller no power is required at this input.
However the controller can be supplied separately from the power stage through the Vcc
input (4.5-12V) and, in this case, the R16 (0Ohm) resistor must be unsoldered.
13.1.4 Test points
Several test points are provided to have easy access at all important signal characterizing
the device:
– COMP: the output of the error amplifier;
– FB: the inverting input of the error amplifier;
– PGOOD: signaling the regular functioning (active high);
– VGDHS: the Bootstrap Diode Anode;
– PHASE: Phase node;
– LGATE: Low-Side gate pin of the device;
– HGATE: High-Side gate pin of the device.
13.1.5 Board characterization
Figure 17. 5A demo board efficiency
100
95
90
85
80
75
70
65
Efficiency [%]
60
55
50
0123456
Vin = 12V, Vout = 1.25V
Vin = 5V, Vout = 1.25V
Vin = 12V, Vout = 2.5V
Vin = 5V, Vout = 2.5V
Output Current [A]
29/32
Page 30
Mechanical data and package dimensions L6728
14 Mechanical data and package dimensions
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect . The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com
Figure 18. Mechanical data and package dimensions
DIMENSIONS
REF.
A 0.80 0.90 1.00 0.031 0.035 0.039
mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
PACKING INFORMATION
PACKAGE AND
A1 0.02 0.05 0.001 0.002
A2 0.70 0.028
A3 0.20 0.008
b 0.18 0.23 0.30 0.007 0.009 0.012
D 3.00 0.118
D2 2.21 2.26 2.31 0.087 0.089 0.091
E 3.00 0.118
E2 1.49 1.64 1.74 0.059 0.065 0.069
e0.50 0.20
L 0.3 0.4 0.5 0.012 0.016 0.020
M
m
0.75
0.25
0.295
0.098
DUAL FLAT NO-LEAD
Weight: not available
PACKAGE
DFN10 (3x3)
30/32
M
m
Page 31
L6728 Revision history
15 Revision history
Table 8. Document revision history
Date Revision Changes
29-Jun-2007 1 Initial release
17-Sep-2007 2 Updated TJ value in Table 3: Thermal data on page 6
31/32
Page 32
L6728
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