The L6566B is an extremely versatile current-mode primary controller ICs, specifically
designed for high-performance offline flyback converters. It is also suited for single-stage
single-switch input-current-shaping converters (single-stage PFC) for applications supposed
to comply with EN61000-3-2 or JEITA-MITI regulations.
Both fixed-frequency (FF) and quasi-resonant (QR) operation are supported. The user can
pick either of the two depending on application needs. The device features an externally
programmable oscillator: it defines converter’s switching frequency in FF mode and the
maximum allowed switching frequency in QR mode.
When FF operation is selected, the ICs work like a standard current-mode controller with a
maximum duty cycle limited at 70 % min. The oscillator frequency can be modulated to
mitigate EMI emissions.
QR operation, when selected, occurs at heavy load and is achieved through a transformer
demagnetization sensing input that triggers MOSFET’s turn-on. Under some conditions,
ZVS (zero-voltage switching) can be achieved. Converter’s power capability rise with the
mains voltage is compensated by line voltage feedforward. At medium and light load, as the
QR operating frequency equals the oscillator frequency, a function (valley skipping) is
activated to prevent further frequency rise and keep the operation as close to ZVS as
possible.
With either FF or QR operation, at very light load the ICs enter a controlled burst-mode
operation that, along with the built-in non-dissipative high-voltage start-up circuit and the low
quiescent current, helps keep low the consumption from the mains and meet energy saving
recommendations.
An innovative adaptive UVLO helps minimize the issues related to the fluctuations of the
self-supply voltage due to transformer’s parasites.
The protection functions included in this device are: not-latched input undervoltage
(brownout), output OVP (auto-restart or latch-mode selectable), a first-level OCP with
delayed shutdown to protect the system during overload or short circuit conditions (autorestart or latch-mode selectable) and a second-level OCP that is invoked when the
transformer saturates or the secondary diode fails short. A latched disable input allows easy
implementation of OTP with an external NTC, while an internal thermal shutdown prevents
IC overheating.
Programmable soft-start, leading-edge blanking on the current sense input for greater noise
immunity, slope compensation (in FF mode only), and a shutdown function for externally
controlled burst-mode operation or remote ON/OFF control complete the equipment of this
device.
6/51
Page 7
L6566BDescription
Figure 2.Typical system block diagram
Rectified
& F iltered
Mains
Voltage
FLYBA CK DC-DC CONVERT E R
L6566B
outdc
V
7/51
Page 8
Pin settingsL6566B
2 Pin settings
2.1 Connections
Figure 3.Pin connection (through top view)
HVSAC_OK
1
16
2.2 Pin description
Table 1.Pin functions
N°PinFunction
High-voltage start-up. The pin, able to withstand 700 V, is to be tied directly to the
rectified mains voltage. A 1 mA internal current source charges the capacitor
connected between Vcc pin (5) and GND pin (3) until the voltage on the Vcc pin
reaches the turn-on threshold, then it is shut down. Normally, the generator is re-
1HVS
2N.C.
3GND
4GD
enabled when the Vcc voltage falls below 5 V to ensure a low power throughput
during short circuit. Otherwise, when a latched protection is tripped the generator is
re-enabled 0.5 V below the turn-on threshold, to keep the latch supplied; or, when
the IC is turned off by pin COMP (9) pulled low the generator is active just below
the UVLO threshold to allow a faster restart.
Not internally connected. Provision for clearance on the PCB to meet safety
requirements.
Ground. Current return for both the signal part of the IC and the gate drive. All of
the ground connections of the bias components should be tied to a track going to
this pin and kept separate from any pulsed current return.
Gate driver output. The totem pole output stage is able to drive power MOSFET’s
and IGBT’s with a peak current capability of 800 mA source/sink.
N.C.
GND
GD
Vcc
FMOD
CSVREF
DIS
2
3
4
5
6
7
8
15
14
13
12
11
10
9
VFF
SS
OSC
MODE/SC
ZCD
CO M P
8/51
Page 9
L6566BPin settings
Table 1.Pin functions (continued)
N°PinFunction
Supply voltage of both the signal part of the IC and the gate driver. The internal
high voltage generator charges an electrolytic capacitor connected between this
pin and GND (pin 3) as long as the voltage on the pin is below the turn-on threshold
5Vcc
6FMOD
7CS
8DIS
of the IC, after that it is disabled and the chip is turned on. The IC is disabled as the
voltage on the pin falls below the UVLO threshold. This threshold is reduced at light
load to counteract the natural reduction of the self-supply voltage. Sometimes a
small bypass capacitor (0.1 µF typ.) to GND might be useful to get a clean bias
voltage for the signal part of the IC.
Frequency modulation input. When FF mode operation is selected, a capacitor
connected from this pin to GND (pin 3) is alternately charged and discharged by
internal current sources. As a result, the voltage on the pin is a symmetrical
triangular waveform with the frequency related to the capacitance value. By
connecting a resistor from this pin to pin 13 (OSC) it is possible to modulate the
current sourced by the OSC pin and then the oscillator frequency. This modulation
is to reduce the peak value of EMI emissions by means of a spread-spectrum
action. If the function is not used, the pin will be left open.
Input to the PWM comparator. The current flowing in the MOSFET is sensed
through a resistor, the resulting voltage is applied to this pin and compared with an
internal reference to determine MOSFET’s turn-off. The pin is equipped with 150 ns
min. blanking time after the gate-drive output goes high for improved noise
immunity. A second comparison level located at 1.5 V latches the device off and
reduces its consumption in case of transformer saturation or secondary diode short
circuit. The information is latched until the voltage on the Vcc pin (5) goes below
the UVLO threshold, hence resulting in intermittent operation. A logic circuit
improves sensitivity to temporary disturbances.
IC’s latched disable input. Internally the pin connects a comparator that, when the
voltage on the pin exceeds 4.5 V, latches off the IC and brings its consumption to a
lower value. The latch is cleared as the voltage on the Vcc pin (5) goes below the
UVLO threshold, but the HV generator keeps the Vcc voltage high (see pin 1
description). It is then necessary to recycle the input power to restart the IC. For a
quick restart pull pin 16 (AC_OK) below the disable threshold (see pin 16
description). Bypass the pin with a capacitor to GND (pin 3) to reduce noise pickup. Ground the pin if the function is not used.
9COMP
10VREF
Control input for loop regulation. The pin will be driven by the phototransistor
(emitter-grounded) of an optocoupler to modulate its voltage by modulating the
current sunk. A capacitor placed between the pin and GND (3), as close to the IC
as possible to reduce noise pick-up, sets a pole in the output-to-control transfer
function. The dynamics of the pin is in the 2.5 to 5 V range. A voltage below an
internally defined threshold activates burst-mode operation. The voltage at the pin
is bottom-clamped at about 2 V. If the clamp is externally overridden and the
voltage is pulled below 1.4 V the IC will shut down.
An internal generator furnishes an accurate voltage reference (5 V ± 2 %) that can
be used to supply few mA to an external circuit. A small film capacitor (0.1 µF typ.),
connected between this pin and GND (3), is recommended to ensure the stability of
the generator and to prevent noise from affecting the reference. This reference is
internally monitored by a separate auxiliary reference and any failure or drift will
cause the IC to latch off.
9/51
Page 10
Pin settingsL6566B
Table 1.Pin functions (continued)
N°PinFunction
Transformer demagnetization sensing input for quasi-resonant operation and OVP
input. The pin is externally connected to the transformer’s auxiliary winding through
a resistor divider. A negative-going edge triggers MOSFET’s turn-on if QR mode is
11ZCD
12 MODE/SC
13OSC
14SS
15VFF
16AC_OK
selected.
A voltage exceeding 5 V shuts the IC down and brings its consumption to a lower
value (OVP). Latch-off or auto-restart mode is selectable externally. This function is
strobed and digitally filtered to increase noise immunity.
Operating mode selection. If the pin is connected to the VREF pin (7)
quasi-resonant operation is selected, the oscillator (pin 13, OSC) determines the
maximum allowed operating frequency.
Fixed-frequency operation is selected if the pin is not tied to VREF, in which case
the oscillator determines the actual operating frequency, the maximum allowed
duty cycle is set at 70 % min. and the pin delivers a voltage ramp synchronized to
the oscillator when the gate-drive output is high; the voltage delivered is zero while
the gate-drive output is low. The pin is to be connected to pin CS (7) via a resistor
for slope compensation.
Oscillator pin. The pin is an accurate 1 V voltage source, and a resistor connected
from the pin to GND (pin 3) defines a current. This current is internally used to set
the oscillator frequency that defines the maximum allowed switching frequency of
the L6566B, if working in QR mode, or the operating switching frequency if working
in FF mode.
Soft-start current source. At start-up a capacitor Css between this pin and GND
(pin 3) is charged with an internal current generator. During the ramp, the internal
reference clamp on the current sense pin (7, CS) rises linearly starting from zero to
its final value, thus causing the duty cycle to increase progressively starting from
zero as well. During soft-start the adaptive UVLO function and all functions
monitoring pin COMP are disabled. The soft-start capacitor is discharged whenever
the supply voltage of the IC falls below the UVLO threshold. The same capacitor is
used to delay IC’s shutdown (latch-off or auto-restart mode selectable) after
detecting an overload condition (OLP).
Line voltage feedforward input. The information on the converter’s input voltage is
fed into the pin through a resistor divider and is used to change the setpoint of the
pulse-by-pulse current limitation (the higher the voltage, the lower the setpoint).
The linear dynamics of the pin ranges from 0 to 3 V. A voltage higher than 3 V
makes the IC stop switching. If feedforward is not desired, tie the pin to GND (pin 3)
directly if a latch-mode OVP is not required (see pin 11, ZCD) or through a 10 kΩ
min. resistor if a latch-mode OVP is required. Bypass the pin with a capacitor to
GND (pin 3) to reduce noise pick-up.
Brownout protection input. A voltage below 0.45 V shuts down (not latched) the IC,
lowers its consumption and clears the latch set by latched protections (DIS > 4.5 V ,
SS > 6.4 V , VFF > 6.4 V). IC’s operation is re-enabled as the voltage exceeds
0.45 V. The comparator is provided with current hysteresis: an internal 15 µA
current generator is ON as long as the voltage on the pin is below 0.45 V and is
OFF if this value is exceeded. Bypass the pin with a capacitor to GND (pin 3) to
reduce noise pick-up. Tie to Vcc with a 220 to 680 kΩ resistor if the fun ction is not
used.
10/51
Page 11
L6566BElectrical data
3 Electrical data
3.1 Maximum rating
Table 2.Absolute maximum ratings
SymbolPinParameterValueUnit
V
HVS
I
HVS
V
CC
V
FMOD
V
max
V
max
I
ZCD
V
MODE/SC
V
OSC
P
TOT
T
STG
T
J
1Voltage range (referred to ground)-0.3 to 700V
1Output currentSelf-limited
5IC supply voltage (Icc = 20 mA)Self-limited
6Voltage range -0.3 to 2V
7, 8, 10, 14 Analog inputs and outputs-0.3 to 7V
9, 15, 16Maximum pin voltage (Ipin ≤ 1 mA)Self-limited
11Zero current detector max. current±5mA
12Voltage range -0.3 to 5.3V
13Voltage range -0.3 to 3.3V
3.2 Thermal data
Table 3.Thermal data
SymbolParameterValueUnit
Power dissipation @TA = 50 °C0.75W
Storage temperature-55 to 150°C
Junction operating temperature range-40 to 150°C
R
thJA
Thermal resistance junction to ambient 120°C/W
11/51
Page 12
Electrical characteristicsL6566B
4 Electrical characteristics
(TJ = -25 to 125°C, VCC = 12, CO = 1 nF; MODE/SC = V
Level for lower UVLO off
threshold (voltage falling)
Level for higher UVLO off
threshold (voltage rising)
2.612.752.89
(3)
MODE/SC = open3.023.153.28
(3)
(3)
MODE/SC = open3.413.553.69
2.93.053.2
VV
V
V
V
14/51
Page 15
L6566BElectrical characteristics
Table 4.Electrical characteristics (continued)
SymbolParameterTest conditionMinTypMaxUnit
Zero current detector/ overvoltage protection
V
ZCDH
V
ZCDL
V
ZCDA
V
ZCDT
I
ZCD
I
ZCDsrc
I
ZCDsnk
T
BLANK1
V
ZCDth
T
BLANK2
Upper clamp voltageI
Lower clamp voltageI
Arming voltage
Triggering voltage
Internal pull-up
Source current capabilityV
Sink current capabilityV
= 3 mA5.45.76V
ZCD
= - 3 mA-0.4V
ZCD
(1)
positive-going edge85100115mV
(1)
negative-going edge305070mV
V
COMP
V
ZCD
ZCD
ZCD
< V
COMPSH
< 2 V, V
= V
ZCDL
= V
ZCDH
COMP
= V
COMPHI
-130-100-70
-3mA
3mA
-1
Turn-on inhibit time After gate-drive going low 2.5µs
OVP threshold4.8555.15V
OVP strobe delayAfter gate-drive going low2µs
Latched shutdown function
I
V
OTP
OTP
Input bias currentV
Disable threshold
DIS
(1)
= 0 to V
OTP
-1µA
4.324.54.68V
Thermal shutdown
VthShutdown threshold160°C
HysHysteresis50°C
µA
External oscillator (frequency modulation)
f
FMOD
Oscillation frequencyC
= 0.1 µF600750900Hz
MOD
---Usable frequency range0.0515kHz
V
V
I
FMOD
pk
vy
Peak voltage
Valley voltage0.5V
Charge/discharge current150µA
(3)
1.5V
Mode selection / slope compensation
MODE
SC
SC
Threshold for QR operation3V
th
Ramp peak
pk
(MODE/SC = open)
Ramp starting value
vy
(MODE/SC = open)
Ramp voltage
(MODE/SC = open)
Source capability
(MODE/SC = open)
R
pin high, V
R
GD pin high
GD pin low0V
V
= 3 kΩ to GND, GD
S-COMP
S-COMP
S-COMP = VS-COMPpk
= 5 V
COMP
= 3 kΩ to GND,
1.7V
0.3V
0.8mA
15/51
Page 16
Electrical characteristicsL6566B
(
−−=
Table 4.Electrical characteristics (continued)
SymbolParameterTest conditionMin.Typ.Max.Unit
Soft-start
T
= 25 °C, VSS < 2 V,
I
SS1
I
SS2
I
SSdis
V
SSclamp
V
SSDIS
V
SSLAT
Gate driver
Charge current
Discharge currentVSS > 2 V3.556.5µA
High saturation voltageV
Disable level
Latch-off levelV
J
= 4 V
V
COMP
TJ = 25 °C, VSS > 2 V,
V
=V
(1)
COMP
COMP
V
COMP
COMPHi
= 4 V2V
= V
COMP
= V
COMPHi
COMPHi
142026
3.556.5
4.8555.15V
6.4V
µA
V
GDH
V
GDL
I
sourcepk
I
sinkpk
t
t
V
GDclamp
Output high voltageI
Output low voltageI
Output source peak current-0.6A
Output sink peak current0.8A
Fall time40ns
f
Rise time50ns
r
Output clamp voltageI
UVLO saturationVcc = 0 to V
1. Parameters tracking one another.
2. See Table 6 on page 41 and Table 7 on page 42
3. The voltage feedforward block output is given by:
GDsource
GDsink
GDsource
= 5 mA, Vcc = 12 V9.811V
= 100 mA0.75V
= 5 mA; Vcc = 20 V1011.315V
ccon, Isink = 1 mA0.91.1V
)
VK5.2VKc V
VFFFFCOMPcs
16/51
Page 17
L6566BApplication information
5 Application information
The L6566B is a versatile peak-current-mode PWM controller specific for offline flyback
converters. The device allows either fixed-frequency (FF) or quasi-resonant (QR) operation,
selectable with the pin MODE/SC (12): forcing the voltage on the pin over 3 V (e.g. by tying
it to the 5 V reference externally available at pin VREF, 10) will activate QR operation,
otherwise the device will be FF-operated.
Irrespective of the operating option selected by pin 12, the device is able to work in different
modes, depending on the converter’s load conditions. If QR operation is selected (see
Figure 4):
1.QR mode at heavy load. Quasi-resonant operation lies in synchronizing MOSFET's
turn-on to the transformer’s demagnetization by detecting the resulting negative-going
edge of the voltage across any winding of the transformer. Then the system works
close to the boundary between discontinuous (DCM) and continuous conduction
(CCM) of the transformer. As a result, the switching frequency will be different for
different line/load conditions (see the hyperbolic-like portion of the curves in
Minimum turn-on losses, low EMI emission and safe behavior in short circuit are the
main benefits of this kind of operation.
2. Valley-skipping mode at medium/ light load. The externally programmable oscillator of
the L6566B, synchronized to MOSFET’s turn-on, enables the designer to define the
maximum operating frequency of the converter. As the load is reduced MOSFET’s turnon will not any more occur on the first valley but on the second one, the third one and
so on. In this way the switching frequency will no longer increase (piecewise linear
portion in
Figure 4).
3. Burst-mode with no or very light load. When the load is extremely light or disconnected,
the converter will enter a controlled on/off operation with constant peak current.
Decreasing the load will then result in frequency reduction, which can go down even to
few hundred hertz, thus minimizing all frequency-related losses and making it easier to
comply with energy saving regulations or recommendations. Being the peak current
very low, no issue of audible noise arises.
Figure 4).
Figure 4.Multi-mode operation with QR option active
f
osc
Valley-skipping
f
sw
0
0
mode
Burst-mode
Quasi-resonant mode
P
in
17/51
Input voltage
Pinmax
Page 18
Application informationL6566B
If FF operation is selected:
1.FF mode from heavy to light load. The system operates exactly like a standard current
mode control, at a frequency f
determined by the externally programmable oscillator:
sw
both DCM and CCM transformer operation are possible, depending on whether the
power that it processes is greater or less than:
Equation 1
2
sw
⎞
VVin
R
⎟
⎟
VVin
+
R
⎠
Lpf2
Pin
⎛
⎜
⎜
⎝
=
T
where Vin is the input voltage to the converter, VR the reflected voltage (i.e. the
regulated output voltage times the primary-to-secondary turn ratio) and Lp the
inductance of the primary winding. Pin
is the power level that marks the transition from
T
continuous to discontinuous operation mode of the transformer.
2. Burst-mode with no or very light load. This kind of operation is activated in the same
way and results in the same behavior as previously described for QR operation.
The L6566B is specifically designed for applications with no PFC front-end; pin 6 (FMOD)
features an auxiliary oscillator that can modulate the switching frequency (when FF
operation is selected) in order to mitigate EMI emissions by a spread-spectrum action.
5.1 High-voltage start-up generator
Figure 5 shows the internal schematic of the high-voltage start-up generator (HV generator).
It is made up of a high-voltage N-channel FET, whose gate is biased by a 15 MΩ resistor,
with a temperature-compensated current generator connected to its source.
With reference to the timing diagram of Figure 6, when power is first applied to the converter
the voltage on the bulk capacitor (Vin) builds up and, at about 80 V, the HV generator is
enabled to operate (HV_EN is pulled high) so that it draws about 1 mA. This current, minus
the device’s consumption, charges the bypass capacitor connected from pin Vcc (5) to
ground and makes its voltage rise almost linearly.
Figure 6.Timing diagram: normal power-up and power-down sequences
Vin
V
HVstart
Vcc
(pin 5)
Vcc
Vcc
Vcc
restart
ON
OFF
regulation is lost here
t
GD
(pin 4)
HV_EN
cc_OK
charge
I
0.85 mA
Power-on Power-off
Normal
operation
t
t
t
t
t
As the Vcc voltage reaches the turn-on threshold (14 V typ.) the device starts operating and
the HV generator is cut off by the Vcc_OK signal asserted high. The device is powered by
the energy stored in the Vcc capacitor until the self-supply circuit (typically an auxiliary
winding of the transformer and a steering diode) develops a voltage high enough to sustain
the operation. The residual consumption of this circuit is just the one on the 15 MΩ resistor
(≈10 mW at 400 Vdc), typically 50-70 times lower, under the same conditions, as compared
to a standard start-up circuit made with external dropping resistors.
At converter power-down the system will lose regulation as soon as the input voltage is so
low that either peak current or maximum duty cycle limitation is tripped. Vcc will then drop
and stop IC activity as it falls below the UVLO threshold (10 V typ.). The Vcc_OK signal is
de-asserted as the Vcc voltage goes below a threshold VCC
generator can now restart. However, if Vin < Vin
, as illustrated in Figure 6, HV_EN is de-
start
located at about 5V. The HV
rest
asserted too and the HV generator is disabled. This prevents converter’s restart attempts
and ensures monotonic output voltage decay at power-down in systems where brownout
protection (see the relevant section) is not used.
The low restart threshold VCC
the device will have a very low repetition rate, as shown in the timing diagram of
page 20
, and that the converter will work safely with extremely low power throughput.
ensures that, during short circuits, the restart attempts of
Figure 8.Zero current detection block, triggering block, oscillator block and
related logic
COMP
915
L6566B
line
FFWD
VFF
+Vin
11
ZCD
MONO
STABLE
BLANKING
TIME
Reset
4:1
Counter
R
Z1
R
Z2
100 mV
50 mV
5V
+
Strobe
+
-
5.7V
S/H
blanking
START
TURN-ON
LOGIC
OSCILLATOR
FAULT
R
Q
S
AUXILIARY
OSCILLATOR
6
FMOD
C
MOD
PWM
R
MOD
DRIVER
13
OSC
R
T
CS
7
4
GD
Q
Rs
20/51
Page 21
L6566BApplication information
5.2 Zero current detection and triggering block; oscillator block
The zero current detection (ZCD) and triggering blocks switch on the external MOSFET if a
negative-going edge falling below 50 mV is applied to the input (pin 11, ZCD). To do so the
triggering block must be previously armed by a positive-going edge exceeding 100 mV.
This feature is typically used to detect transformer demagnetization for QR operation, where
the signal for the ZCD input is obtained from the transformer’s auxiliary winding used also to
supply the L6566B. The triggering block is blanked for T
turn-off to prevent any negative-going edge that follows leakage inductance
demagnetization from triggering the ZCD circuit erroneously.
The voltage at the pin is both top and bottom limited by a double clamp, as illustrated in the
internal diagram of the ZCD block of
Figure 8 on page 20. The upper clamp is typically
located at 5.7 V, while the lower clamp is located at -0.4 V. The interface between the pin
and the auxiliary winding will be a resistor divider. Its resistance ratio will be properly chosen
Section 5.11: OVP block on page 35) and the individual resistance values (R
(see
will be such that the current sourced and sunk by the pin be within the rated capability of the
internal clamps (± 3 mA).
At converter power-up, when no signal is coming from the ZCD pin, the oscillator starts up
the system. The oscillator is programmed externally by means of a resistor (R
from pin OSC (13) to ground. With good approximation the oscillation frequency f
= 2.5 µs after MOSFET’s
BLANK
, RZ2)
Z1
) connected
T
will be:
osc
Equation 2
3
102f⋅
≈
(with f
osc
in kHz and RT in kΩ). As the device is turned on, the oscillator starts immediately;
osc
R
T
at the end of the first oscillator cycle, being zero the voltage on the ZCD pin, the MOSFET
will be turned on, thus starting the first switching cycle right at the beginning of the second
oscillator cycle. At any switching cycle, the MOSFET is turned off as the voltage on the
current sense pin (CS, 7) hits an internal reference set by the line feedforward block, and the
transformer starts demagnetization. If this completes (hence a negative-going edge appears
on the ZCD pin) after a time exceeding one oscillation period T
osc
= 1/f
from the previous
osc
turn-on, the MOSFET will be turned on again - with some delay to ensure minimum voltage
at turn-on – and the oscillator ramp will be reset. If, instead, the negative-going edge
appears before T
after T
will turn-on the MOSFET and synchronize the oscillator. In this way one or more
osc
drain ringing cycles will be skipped (“valley-skipping mode”,
frequency will be prevented from exceeding f
has elapsed, it will be ignored and only the first negative-going edge
osc
Figure 9) and the switching
.
osc
21/51
Page 22
Application informationL6566B
V
Figure 9.Drain ringing cycle skipping as the load is gradually reduced
DS
V
DS
V
DS
T
T
FW
osc
T
V
Pin = Pin'
(limit condition)
T
ON
t
T
osc
in''
< P
in'
Pin= P
t
T
osc
in'''
Pin= P
< P
in''
Note:When the system operates in valley skipping-mode, uneven switching cycles may be
observed under some line/load conditions, due to the fact that the OFF-time of the MOSFET
is allowed to change with discrete steps of one ringing cycle, while the OFF-time needed for
cycle-by-cycle energy balance may fall in between. Thus one or more longer switching
cycles will be compensated by one or more shorter cycles and vice versa. However, this
mechanism is absolutely normal and there is no appreciable effect on the performance of
the converter or on its output voltage.
If the MOSFET is enabled to turn on but the amplitude of the signal on the ZCD pin is
smaller than the arming threshold for some reason (e.g. a heavy damping of drain
oscillations, like in some single-stage PFC topologies, or when a turn-off snubber is used),
MOSFET’s turn-on cannot be triggered. This case is identical to what happens at start-up:
at the end of the next oscillator cycle the MOSFET will be turned on, and a new switching
cycle will take place after skipping no more than one oscillator cycle.
The operation described so far does not consider the blanking time T
turn off, and actually T
does not come into play as long as the following condition is
BLANK
after MOSFET’s
BLANK
met:
Equation 3
t
where D is the MOSFET duty cycle. If this condition is not met, things do not change
substantially: the time during which MOSFET’s turn-on is inhibited is extended beyond T
by a fraction of T
lower than the programmed value f
. As a consequence, the maximum switching frequency will be a little
BLANK
and valley-skipping mode may take place slightly
osc
earlier than expected. However this is quite unusual: setting f
phenomenon can be observed at duty cycles higher than 60 %. See
block on page 35
for further implications of T
If the voltage on the COMP pin (9) saturates high, which reveals an open control loop, an
internal pull-up keeps the ZCD pin close to 2 V during MOSFET's OFF-time to prevent noise
from false triggering the detection block. When this pull-up is active, the ZCD pin might not
be able to go below the triggering threshold, which would stop the converter. To allow autorestart operation, however ensuring minimum operating frequency in these conditions, the
oscillator frequency that retriggers MOSFET's turn-on is that of the external oscillator
divided by 128. Additionally, to prevent malfunction at converter's start-up, the pull-up is
disabled during the initial soft-start (see the relevant section). However, to ensure a correct
22/51
1D−≤
T
BLANK
T
osc
BLANK
osc
= 150 kHz, the
osc
Section 5.11: OVP
.
Page 23
L6566BApplication information
start-up, at the end of the soft-start phase the output voltage of the converter must meet the
condition:
Equation 4
Vout >
Ns
Naux
IR
ZCD1Z
where Ns is the turn number of the secondary winding, Naux the turn number of the
auxiliary winding and I
the maximum pull-up current (130 µA).
ZCD
The operation described so far under different operating conditions for the converter is
illustrated in the timing diagrams of
Figure 10.
If the FF option is selected the operation will be exactly equal to that of a standard currentmode PWM controller. It will work at a frequency fsw = fosc; both DCM and CCM
transformer's operation are possible, depending on the operating conditions (input voltage
and output load) and on the design of the power stage. The MOSFET is turned on at the
beginning of each oscillator cycle and is turned off as the voltage on the current sense pin
reaches an internal reference set by the line feedforward block. The maximum duty cycle is
limited at 70 % minimum. The signal on the ZCD pin in this case is used only for detecting
feedback loop failures (see
Figure 10. Operation of ZCD, triggering and oscillator blocks (QR option active)
ZCD
(pin 11)
100 mV
50 mV
Oscillator
ramp
Section 5.11: OVP block on page 35 ).
ZCD
(pin 11)
100 mV
50 mV
Oscillator
ramp
ZCD
(pin 11)
100 mV
50 mV
Oscillator
ramp
ZCD
blanking
time
Arm /Trigger
ON-enable
PWM latch
Set
PWM latch
Reset
GD
(pin 4)
armed trigger
a) full load
ZCD
blanking
time
Arm/Trigger
ON-enable
PWM latch
Set
PWM latch
Reset
GD
(pin 4)
ZCD
blanking
time
Arm /Trigger
ON-enable
PWM latch
Set
PWM latch
Reset
GD
(pin 4)
b) light load
c) start - up
23/51
Page 24
Application informationL6566B
5.3 Burst-mode operation at no load or very light load
When the voltage at the COMP pin (9) falls 20 mV below a threshold fixed internally at a
value, V
COMPBM
the MOSFET kept in OFF state and its consumption reduced at a lower value to minimize
Vcc capacitor discharge.
The control voltage now will increase as a result of the feedback reaction to the energy
delivery stop (the output voltage will be slowly decaying), the threshold will be exceeded and
the device will restart switching again. In this way the converter will work in burst-mode with
a nearly constant peak current defined by the internal disable level. A load decrease will
then cause a frequency reduction, which can go down even to few hundred hertz, thus
minimizing all frequency-related losses and making it easier to comply with energy saving
regulations. This kind of operation, shown in the timing diagrams of
others previously described, is noise-free since the peak current is low.
If it is necessary to decrease the intervention threshold of the burst-mode operation, this can
be done by adding a small DC offset on the current sense pin as shown in
page 25
.
Note:The offset reduces the available dynamics of the current signal; thereby, the value of the
sense resistor must be determined taking this offset into account.
, depending on the selected operating mode, the L6566B is disabled with
Figure 11 along with the
Figure 12 on
COMP
(pin 9)
V
COMPBM
f
osc
sw
f
GD
(pin 4)
MODE/SC=Open
MODE/SC=VREF
FF Mode Burst-mode FF Mode
QR Mode
Burst-mode
V alley-skipping Mode
20 mV
hyster.
t
MODE/SC=Open
MODE/SC=VREF
t
t
QR Mode
24/51
Page 25
L6566BApplication information
C
Figure 12. Addition of an offset to the current sense lowers the burst-mode
operation threshold
Vcs
o
= Vref
Vref
R
R + Rc
5.4 Adaptive UVLO
A major problem when optimizing a converter for minimum no-load consumption is that the
voltage generated by the auxiliary winding under these conditions falls considerably as
compared even to a few mA load. This very often causes the supply voltage Vcc of the
control IC to drop and go below the UVLO threshold so that the operation becomes
intermittent, which is undesired. Furthermore, this must be traded off against the need of
generating a voltage not exceeding the maximum allowed by the control IC at full load.
To help the designer overcome this problem, the device, besides reducing its own
consumption during burst-mode operation, also features a proprietary adaptive UVLO
function. It consists of shifting the UVLO threshold downwards at light load, namely when
the voltage at pin COMP falls below a threshold V
headroom. To prevent any malfunction during transients from minimum to maximum load
the normal (higher) UVLO threshold is re-established when the voltage at pin COMP
exceeds V
normal UVLO threshold ensures that at full load the MOSFET will be driven with a proper
gate-to-source voltage.
Figure 13. Adaptive UVLO block
OMP
9
-
+
V
COMPL
V
COMPO
and Vcc has exceeded the normal UVLO threshold (see Figure 13). The
COMPL
R
S Q
Vcc
OFF1
+
-
10
L6566B
Vcc
5
SW
Vcc
OFF2
(*)
3
UVLO
+
-
L6566B
4
Rc
R
7
Rs
internally fixed, so as to have more
COMPO
VCOMP
(pin 9)
V
COMPL
V
COMPO
Vcc
(pin 5)
Vcc
Vcc
OFF1
OFF2
Q
t
t
(*) V cc
< Vcc
OFF2
is selected when Q is high
OFF1
t
25/51
Page 26
Application informationL6566B
5.5 PWM control block
The device is specific for secondary feedback. Typically, there is a TL431 on the secondary
side and an optocoupler that transfers output voltage information to the PWM control on the
primary side, crossing the isolation barrier. The PWM control input (pin 9, COMP) is driven
directly by the phototransistor’s collector (the emitter is grounded to GND) to modulate the
duty cycle (
In applications where a tight output regulation is not required, it is possible to use a primarysensing feedback technique. In this approach the voltage generated by the self-supply
winding is sensed and regulated. This solution, shown in
is cheaper because no optocoupler or secondary reference is needed, but output voltage
regulation, especially as a result of load changes, is quite poor.
Figure 14. Possible feedback configurations that can be used with the L6566B
Figure 14, left-hand side circuit).
Figure 14, right-hand side circuit,
L6566B
9
COMP
TL431
Secondary feedbackPrimary feedback
Vout
L6566B
COMP
5 Vcc
9
Cs
N
aux
Ideally, the voltage generated by the self-supply winding and the output voltage should be
related by the Naux/Ns turn ratio only. Actually, numerous non-idealities, mainly
transformer's parasites, cause the actual ratio to deviate from the ideal one. Line regulation
is quite good, in the range of ± 2 %, whereas load regulation is about ± 5 % and output
voltage tolerance is in the range of ± 10 %.
The dynamics of the pin is in the 2.5 to 5 V range. The voltage at the pin is clamped
downwards at about 2 V. If the clamp is externally overridden and the voltage on the pin is
pulled below 1.4 V the L6566B will shut down. This condition is latched as long as the
device is supplied. While the device is disabled, however, no energy is coming from the selfsupply circuit, thus the voltage on the Vcc capacitor will decay and cross the UVLO
threshold after some time, which clears the latch and lets the HV generator restart. This
function is intended for an externally controlled burst-mode operation at light load with a
reduced output voltage, a technique typically used in multi-output SMPS, such as those for
TVs or monitors (see the timing diagram
5.6 PWM comparator, PWM latch and voltage feedforward blocks
The PWM comparator senses the voltage across the current sense resistor Rs and, by
comparing it to the programming signal delivered by the feedforward block, determines the
exact time when the external MOSFET is to be switched off. Its output resets the PWM
latch, previously set by the oscillator or the ZCD triggering block, which will assert the gate
driver output low. The use of PWM latch avoids spurious switching of the MOSFET that
might result from the noise generated (“double-pulse suppression”).
Cycle-by-cycle current limitation is realized with a second comparator (OCP comparator)
that senses the voltage across the current sense resistor Rs as well and compares this
voltage to a reference value V
the circuit schematic in
delivered by the feedforward block and sent to the PWM comparator exceeds V
the OCP comparator to reset first the PWM latch instead of the PWM comparator. The value
of V
csx, thereby, determines the overcurrent setpoint along with the sense resistor Rs.
The power that QR flyback converters with a fixed overcurrent setpoint (like fixed-frequency
systems) are able to deliver changes with the input voltage considerably. With wide-range
mains, at maximum line it can be more than twice the value at minimum line, as shown by
the upper curve in the diagram of
function available to solve this issue.
It acts on the overcurrent setpoint V
Vin sensed through a dedicated pin (15, VFF): the higher the input voltage, the lower the
csx. Its output is or-ed with that of the PWM comparator (see
Figure 17 on page 29). In this way, if the programming signal
csx, it will be
Figure 16 on page 28. The device has the line feedforward
csx, so that it is a function of the converter’s input voltage
27/51
Page 28
Application informationL6566B
@
setpoint. This is illustrated in the diagram on the left-hand side of Figure 17 on page 29: it
shows the relationship between the voltage on the pin VFF and V
csx (with the error amplifier
saturated high in the attempt of keeping output voltage regulation):
Equation 5
csx
V
VFF
1V
3
k
1
Vin
−=−=
3
Figure 16. Typical power capability change vs input voltage in QR flyback
converters
2.5
2
inmin
1.5
V
inlim
P
1
0.5
11.522.533.54
system not
compensated
system optimally
compensated
in
V
inmin
V
k = 0
k = k
k
opt
Note:If the voltage on the pin exceeds 3 V switching ceases but the soft-start capacitor is not
discharged. The schematic in Figure 17 on page 29 shows also how the function is included
in the control loop.
With a proper selection of the external divider R1-R2, i.e. of the ratio k = R2 / (R1+R2), it is
possible to achieve the optimum compensation described by the lower curve in the diagram
of
Figure 16.
The optimum value of k, k
, which minimizes the power capability variation over the input
opt
voltage range, is the one that provides equal power capability at the extremes of the range.
The exact calculation is complex, and non-idealities shift the real-world optimum value from
the theoretical one. It is therefore more practical to provide a first cut value, simple to be
calculated, and then to fine tune experimentally.
Assuming that the system operates exactly at the boundary between DCM and CCM, and
neglecting propagation delays, the following expression for k
Equation 6
3k
⋅=
opt
28/51
can be found:
opt
V
R
()
⋅++⋅
VVVVV
Rmaxinmininmaxinminin
Page 29
L6566BApplication information
V
Experience shows that this value is typically lower than the real one. Once the maximum
peak primary current, I
PKpmax
, occurring at minimum input voltage Vinmin has been found,
the value of Rs can be determined from (5):
Equation 7
k
opt
1Rs−
=
Figure 17. Left: overcurrent setpoint vs VFF voltage; right: line feedforward function block
V
minin
3
I
maxPKp
[V]
csx
1.2
V
= Upper clamp
1
0.8
0.6
0.4
0.2
0
00.511.522.533.5
COMP
V
[V]
VFF
The converter is then tested on the bench to find the output power level Pout
regulation is lost (because overcurrent is being tripped) both at Vin = Vin
@ Vin
lim
max
.
max
> Pout
@ Vin
lim
@ Vin
lim
max
Vin = Vin
If Pout
increasing; if Pout
needs decreasing. This will go on until the difference between the two values is acceptably
low. Once found the true k
in this way, it is possible that Pout
opt
from the target; to correct this, the sense resistor Rs needs adjusting and the above tuning
process will be repeated with the new Rs value. Typically a satisfactory setting is achieved in
no more than a couple of iterations.
min
< Pout
Rectif ie d Line Voltage
VFFCS
15
VOLTAGE
FORWARD
Optional for
OVP settings
7
FEED
Vcsx
1.5 V
+
PWM
+
OCP
+
Hiccup
-
Rs
DRIVER
4
Clock/ZCD
min
R
S
Q
DISABLE
lim
and
where
R1
R2
COMP
9
L6566B
the system is still undercompensated and k needs
@ Vin
lim
the system is overcompensated and k
min
turns out slightly different
lim
GD
In applications where this function is not wanted, e.g. because of a narrow input voltage
range, the VFF pin can be simply grounded, directly or through a resistor (see “
OVP block on page 35
”). The overcurrent setpoint will be then fixed at the maximum value of
Section 5.11:
1V. If a lower setpoint is desired to reduce the power dissipation on Rs, the pin can be also
biased at a fixed voltage using a divider from VREF (pin 10).
If the FF option is selected the line feedforward function can be still used to compensate for
the total propagation delay Td of the current sense chain (internal propagation delay td
(H-L)
plus the turn-off delay of the external MOSFET), which in standard current mode PWM
controllers is done by adding an offset on the current sense pin proportional to the input
voltage. In that case the divider ratio k, which will be much smaller as compared to that used
with the QR option selected, can be calculated with the following equation:
29/51
Page 30
Application informationL6566B
Equation 8
opt
LpRs
Td
3k
=
where Lp is the inductance of the primary winding. In case a constant maximum power
capability vs. the input voltage is not required, the VFF pin can be grounded, directly or
through a resistor (see
Section 5.11: OVP block on page 35), hence fixing the overcurrent
setpoint at 1 V, or biased at a fixed voltage through a divider from VREF to get a lower
setpoint.
It is possible to bypass the pin to ground with a small film capacitor (e.g. 1-10 nF) to ensure
a clean operation of the IC even in a noisy environment.
The pin is internally forced to ground during UVLO, after activating any latched protection
and when pin COMP is pulled below its low clamp voltage (see
block on page 26
).
Section 5.5: PWM control
5.7 Hiccup-mode OCP
A third comparator senses the voltage on the current sense input and shuts down the device
if the voltage on the pin exceeds 1.5 V, a level well above that of the maximum overcurrent
setpoint (1 V). Such an anomalous condition is typically generated by either a short circuit of
the secondary rectifier or a shorted secondary winding or a hard-saturated flyback
transformer.
Figure 18. Hiccup-mode OCP: timing diagram
Vcc
(pin 5)
Vcc
Vcc
restart
Vcc
CS
V
(pin 7)
GD
(pin 4)
OCP latch
Vcc_OK
ON
OFF
1.5 V
Secondary diode is shorted her e
t
t
t
t
t
To distinguish an actual malfunction from a disturbance (e.g. induced during ESD tests), the
first time the comparator is tripped the protection circuit enters a “warning state”. If in the
next switching cycle the comparator is not tripped, a temporary disturbance is assumed and
the protection logic will be reset in its idle state; if the comparator will be tripped again a real
malfunction is assumed and the L6566B will be stopped. Depending on the time relationship
30/51
Page 31
L6566BApplication information
between the detected event and the oscillator, occasionally the device could stop after the
third detection.
This condition is latched as long as the device is supplied. While it is disabled, however, no
energy is coming from the self-supply circuit; hence the voltage on the Vcc capacitor will
decay and cross the UVLO threshold after some time, which clears the latch. The internal
start-up generator is still off, then the Vcc voltage still needs to go below its restart voltage
before the Vcc capacitor is charged again and the device restarted. Ultimately, this will result
in a low-frequency intermittent operation (Hiccup-mode operation), with very low stress on
the power circuit. This special condition is illustrated in the timing diagram of
page 30
.
Figure 18 on
5.8 Frequency modulation
To alleviate converter’s EMI emissions and reduce cost and size of the line filter, it is
advantageous to modulate its switching frequency, so that the resulting spread-spectrum
action distributes the energy of each harmonic of the switching frequency over a number of
side-band harmonics. Their overall energy will be unchanged but the individual amplitudes
will be smaller. This is what naturally occurs with QR operation, due to the twice-mainsfrequency ripple appearing on the input bulk capacitor, which translates into different DCMCCM boundary frequencies.
The L6566B is provided with a dedicated pin, FMOD (6), to perform this function if FF mode
is selected.
Figure 19. Frequency modulation circuit
L6566B
1 V
0 V
13
OSC
RMOD
RT
With reference to Figure 19, the capacitor C
alternately charged and discharged between 0.5 and 1.5 V by internal current generators
sourcing and sinking the same current (three times the current defined by the resistor R
pin OSC). Hence, the voltage across C
is determined by C
. By connecting a resistor R
MOD
will be a symmetric triangle, whose frequency fm
MOD
sourced by pin OSC will be modulated according a triangular profile at a frequency f
is considerably higher than RT, as normally is, both fm and the symmetry of the
R
MOD
triangle will be little affected.
6
FMOD
CMOD
is connected from FMOD to ground and is
MOD
from FMOD to OSC, the current
MOD
1.5 V
0.5 V
m
. If
T
on
With this arrangement it is possible to set, nearly independently, the frequency deviation
and the modulating frequency fm, which define the modulation index:
∆f
sw
31/51
Page 32
Application informationL6566B
Equation 9
f∆
sw
=β
f
m
which is the parameter that the amplitude of the generated side-band harmonics depends
on.
The minimum frequency f
frequency f
(occurring on the valley of the triangle) will be symmetrically placed
sw_max
around the centre value f
(occurring on the peak of the triangle) and the maximum
sw_min
, so that:
sw
Equation 10
swmin_sw
Then, RT will be found from (5) (see Section 5.2: Zero current detection and triggering block;
oscillator block on page 21
), while R
Equation 11
R
=
MOD
where ∆fsw and fm (in kHz, with C
MOD
to achieve the best compromise between attenuation of peak EMI emissions and clean
converter operation.
5.9 Latched disable function
1
2
and C
MOD
3
102
⋅
f
∆
sw
in nF and R
1
fff;fff∆+=∆−=
swmax_swsw
can be calculated as follows:
MOD
C=
MOD
MOD
75
f
m
in kΩ) will be selected by the user so
sw
2
The device is equipped with a comparator having the non-inverting input externally available
at the pin DIS (8) and with the inverting input internally referenced to 4.5 V. As the voltage
on the pin exceeds the internal threshold, the device is immediately shut down and its
consumption reduced to a low value.
The information is latched and it is necessary to let the voltage on the Vcc pin go below the
UVLO threshold to reset the latch and restart the device. To keep the latch supplied as long
as the converter is connected to the input source, the HV generator is activated periodically
so that Vcc oscillates between the start-up threshold V
HV generator in this way cuts its power dissipation approximately by three (as compared to
the case of continuous conduction) and keeps peak silicon temperature close to the average
value.
To let the L6566B restart it is then necessary to disconnect the converter from the input
source. Pulling pin 16 (AC_OK) below the disable threshold (see
protection on page 37
) will stop the HV generator until Vcc falls below Vcc
latch can be cleared and a quicker restart is allowed as the input source is removed. This
operation is shown in the timing diagram of
32/51
and V
ccON
Figure 20 on page 33.
- 0.5 V. Activating the
ccON
Section 5.12: Brownout
, so that the
restart
Page 33
L6566BApplication information
t
This function is useful to implement a latched overtemperature protection very easily by
biasing the pin with a divider from VREF, where the upper resistor is an NTC physically
located close to a heating element like the MOSFET, or the transformer. The DIS pin is a
high impedance input, thus it is prone to pick up noise, which might give origin to undesired
latch-off of the device. It is possible to bypass the pin to ground with a small film capacitor
(e.g. 1-10 nF) to prevent any malfunctioning of this kind.
Figure 20. Operation after latched disable activation: timing diagram
DIS
(pin 8)
4.5V
Vcc
Vcc
(pin 5)
Vcc
ON
Vcc
Vcc
HV generato r is turned on
ON
-0.5
OFF
restart
GD
Restart i s quic ker
Disable latch i s reset here
HV generator turn-on is disabled here
(pin 4)
Input source is removed here
V
Vin
HVstart
AC_OK
(pin 16)
Vth
5.10 Soft-start and delayed latched shutdown upon overcurrent
At device start-up, a capacitor (CSS) connected between the SS pin (14) and ground is
charged by an internal current generator, I
clamped. During this ramp, the overcurrent setpoint progressively rises from zero to the
value imposed by the voltage on the VFF pin (15, see
latch and voltage feedforward blocks on page 27
gradually, hence controlling the start-up inrush current. The time needed for the overcurrent
setpoint to reach its steady state value, referred to as soft-start time, is approximately:
, from zero up to about 2 V where it is
SS1
Section 5.6: PWM comparator, PWM
); MOSFET’s conduction time increases
t
t
t
t
Equation 12
V
VFF
3
⎞
⎟
⎟
⎠
During the ramp (i.e. until V
T
Css
SS
I
1SS
= 2 V) all the functions that monitor the voltage on pin COMP
SS
)V(V
VFFcsx
Css
I
⎛
⎜
−==
1
⎜
⎝
1SS
are disabled.
33/51
Page 34
Application informationL6566B
(
The soft-start pin is also invoked whenever the control voltage (COMP) saturates high,
which reveals an open-loop condition for the feedback system. This condition very often
occurs at start-up, but may be also caused by either a control loop failure or a converter
overload/short circuit. A control loop failure results in an output overvoltage that is handled
by the OVP function of the L6566B (see next section). In case of QR operation, a short
circuit causes the converter to run at a very low frequency, then with very low power
capability. This makes the self-supply system that powers the device unable to keep it
operating, so that the converter will work intermittently, which is very safe. In case of
overload the system has a power capability lower than that at nominal load but the output
current may be quite high and overstress the output rectifier. In case of FF operation the
capability is almost unchanged and both short circuit and overload conditions are more
critical to handle.
The L6566B, regardless of the operating option selected, makes it easier to handle such
conditions: the 2 V clamp on the SS pin is removed and a second internal current generator
= I
I
SS2
is allowed to reach 2 V
resulting behavior will be identical to that under short circuit illustrated in
page 20
/4 keeps on charging CSS. As the voltage reaches 5 V the device is disabled, if it
SS1
over 5 V, the device will be latched off. In the former case the
BE
Figure 7 on
; in the latter case the result will be identical to that of Figure 20 on page 33. See
Section 5.9: Latched disable function on page 32 for additional details.
Figure 21. Soft-start pin operation under different operating conditions and settings
Vcc
(pin 5)
SS
pin 14)
COMP
(pin 9)
GD
(pin 4)
2V
Vcc falls below UVLO
5V+2Vbe
5V
START-UP
NORMAL
OPERATION
TEMPORARY
OVERLOAD
NORMAL
OPERATION
before latching off
here the IC
shuts down
OVERLOAD
here the IC
latches off
SHUTDOWN
LATCHE D
AUTORESTART
A diode, with the anode to the SS pin and the cathode connected to the VREF pin (10) is the
simplest way to select either auto-restart mode or latch-mode behavior upon overcurrent. If
the overload disappears before the Css voltage reaches 5 V the I
generator will be
SS2
turned off and the voltage gradually brought back down to 2 V. Refer to the “Application
examples and Ideas” section (
Table 7 on page 45) for additional hints.
If latch-mode behavior is desired also for converter’s short circuit, make sure that the supply
voltage of the device does not fall below the UVLO threshold before activating the latch.
Figure 21 shows soft-start pin behavior under different operating conditions and with
different settings (latch-mode or autorestart).
UVLO
RESTART
t
t
t
t
Note:Unlike other PWM controllers provided with a soft-start pin, in the L6566B grounding the SS
pin does not guarantee that the gate driver is disabled.
34/51
Page 35
L6566BApplication information
5.11 OVP block
The OVP function of the L6566B monitors the voltage on the ZCD pin (11) in MOSFET’s
OFF-time, during which the voltage generated by the auxiliary winding tracks converter’s
output voltage. If the voltage on the pin exceeds an internal 5 V reference, a comparator is
triggered, an overvoltage condition is assumed and the device is shut down. An internal
current generator is activated that sources 1 mA out of the VFF pin (15). If the VFF voltage
is allowed to reach 2 Vbe over 5 V, the L6566B will be latched off. See
disable function on page 32
for more details on IC’s behavior under these conditions. If the
impedance externally connected to pin 15 is so low that the 5+2 V
reached or if some means is provided to prevent that, the device will be able to restart after
the Vcc has dropped below 5 V. Refer to the “Application examples and Ideas” section
Table 7 on page 45) for additional hints.
(
Figure 22. OVP function: internal block diagram
ZCD
11
5 V
40k
Ω
5pF
2 µs
-
+
Monostable
M2
STROBE
0.5 µs
COUT
OVP
PWM latch
R
to triggering
block
Q
QS
Monostable
M1
Section 5.9: Latched
threshold cannot be
BE
L6566B
2-bit
counter
FF
R Q1
S
Count er
Fault
reset
The ZCD pin will be connected to the auxiliary winding through a resistor divider RZ1, RZ2
Figure 8 on page 20). The divider ratio k
(see
OVP
= R
Z2
/ (R
+ RZ2) will be chosen equal
Z1
to:
Equation 13
OVP
Ns
Naux
where Vout
=
5
Vout
k
OVP
is the output voltage value that is to activate the protection, Ns the turn
OVP
number of the secondary winding and Naux the turn number of the auxiliary winding.
35/51
Page 36
Application informationL6566B
Figure 23. OVP function: timing diagram
GD
(pin 4)
Vau x
0
ZCD
(pin 11)
5V
COUT
STROBE
OVP
COUNTER
RESET
COUNTER
STAT US
FAULT
2 µs0.5 µs
00 00 →11 →22 →00
NORMA L OPERA T IO NTEMPO RA RY DISTURBA NCEF EEDBA CK LOOP FAILURE
11 →22 →33 →40
→
The value of RZ1 will be such that the current sourced by the ZCD pin be within the rated
capability of the internal clamp:
Equation 14
t
t
t
t
t
t
t
t
t
Naux
1
≥
3
−
103
⋅
Np
Vin
max
where Vin
max
winding. See
page 21
for additional details.
R
1Z
is the maximum dc input voltage and Ns the turn number of the primary
Section 5.2: Zero current detection and triggering block; oscillator block on
To reduce sensitivity to noise and prevent the latch from being erroneously activated, first
the OVP comparator is active only for a small time window (typically, 0.5 µs) starting 2 µs
after MOSFET’s turn-off, to reject the voltage spike associated to the positive-going edges
of the voltage across the auxiliary winding Vaux; second, to stop the L6566B the OVP
comparator must be triggered for four consecutive switching cycles. A counter, which is
reset every time the OVP comparator is not triggered in one switching cycle, is provided to
this purpose.
Figure 22 on page 35 shows the internal block diagram, while the timing diagrams in
Figure 23 illustrate the operation.
Note:To use the OVP function effectively, i.e. to ensure that the OVP comparator will be always
interrogated during MOSFET’s OFF-time, the duty cycle D under open-loop conditions must
fulfill the following inequality:
36/51
Page 37
L6566BApplication information
≤
+
Equation 15
1fTD
sw2BLANK
where T
BLANK2
= 2 µs; this is also illustrated in the diagram of Figure 24.
Figure 24. Maximum allowed duty cycle vs switching frequency for correct OVP
detection
0.8
0.7
0.6
0.5
Dmax
0.4
0.3
0.2
5.1041.1051.5.1052.1052.5.1053.1053.5.1054.10
5.12 Brownout protection
Brownout protection is basically a not-latched device shutdown function activated when a
condition of mains undervoltage is detected. There are several reasons why it may be
desirable to shut down a converter during a brownout condition, which occurs when the
mains voltage falls below the minimum specification of normal operation.
0.725
5
fsw [Hz]
Firstly, a brownout condition may cause overheating of the primary power section due to an
excess of RMS current. Secondly, spurious restarts may occur during converter power
down, hence causing the output voltage not to decay to zero monotonically.
L6566B shutdown upon brownout is accomplished by means of an internal comparator, as
shown in the block diagram of
Figure 25 on page 38, which shows the basic usage. The
inverting input of the comparator, available on the AC_OK pin (16), is supposed to sense a
voltage proportional to the RMS (peak) mains voltage; the non-inverting input is internally
referenced to 0.485 V with 35 mV hysteresis. If the voltage applied on the AC_OK pin before
the device starts operating does not exceed 0.485 V or if it falls below 0.45 V while the
device is running, the AC_FAIL signal goes high and the device shuts down, with the softstart capacitor discharged and the gate-drive output low. Additionally, if the device has been
latched off by some protection function (testified by Vcc oscillating between V
V
- 0.5 V) the AC_OK voltage falling below 0.45 V clears the latch. This may allow a
ccON
ccON
and
quicker restart as the input source is removed.
While the brownout protection is active the start-up generator keeps on working but, being
there no PWM activity, the Vcc voltage continuously oscillates between the start-up and the
HV generator restart thresholds, as shown in the timing diagram of
37/51
Figure 25.
Page 38
Application informationL6566B
−
Figure 25. Brownout protection: internal block diagram and timing diagram
Sensed
voltage
R
H
RL
AC_OK
L6566B
16
15 µA
0.485V
0.45V
Vcc
5
-
+
AC_ FAIL
Sensed voltage
Vsen
OFF
Vsen
VAC_OK
(pin 16)
AC_ FAIL
HYS
I
15 µA
Vcc
(pin 5)
GD
(pin 4)
Vout
ON
0.485V
t
0.45V
t
t
t
t
t
t
The brownout comparator is provided with current hysteresis in addition to voltage
hysteresis: an internal 15 µA current sink is ON as long as the voltage applied on the
AC_OK pin is such that the AC_FAIL signal is high. This approach provides an additional
degree of freedom: it is possible to set the ON threshold and the OFF threshold separately
by properly choosing the resistors of the external divider (see below). With just voltage
hysteresis, instead, fixing one threshold automatically fixes the other one depending on the
built-in hysteresis of the comparator.
With reference to
(Vsen
) and OFF (Vsen
ON
Figure 25, the following relationships can be established for the ON
) thresholds of the sensed voltage:
OFF
Equation 16
ON
−
R
H
6
−
1015
485.0Vsen
which, solved for RH and RL, yield:
Equation 17
Vsen078.1Vsen
R
=
H
38/51
⋅−
−
6
1015
⋅
485.0
+⋅=
R
L
OFFON
OFF
R
RR;
=
HL
45.0Vsen
45.0
OFF
45.0
=
R
LH
45.0Vsen
−
Page 39
L6566BApplication information
(
−=+
=
Figure 26. Voltage sensing techniques to implement brownout protection with the
L6566B
HV Input bus
R
H
R
L
R
R
AC_OK
L1
L2
VFF
16
L6566B
15
Optionalfor
OVPsettings
AC mains (N/L)
AC mains (L/N)
R
R
H
R
L
H
AC_OK
16
L1
R
VFF
R
L2
F
C
L6566B
15
Optionalfor
OVP settings
a)b)
It is typically convenient to use a single divider to bias both the AC_OK and the VFF pins, as
shown in
is lower than that on the AC_OK pin. Once R
and k
Figure 26: this is possible because in all practical cases the voltage on the VFF pin
and RL have been found as suggested above,
, either calculated from (6) or (8) or experimentally found, RL will be split as:
opt
H
Equation 18
)
RRR;RRkR
2LL1LHLopt2L
Circuit a) senses the input voltage bus (across the bulk capacitor, downstream the bridge
rectifier); in this case, for a proper operation of the brownout function, Vsen
than the peak voltage at minimum mains and Vsen
lower than the minimum voltage on
OFF
must be lower
ON
the input bulk capacitor at minimum mains and maximum load considering, in case, holdup
requirements during mains missing cycles as well. Brownout level will be load-dependent. In
case of latched shutdown, when the input source is removed it is necessary to wait until the
bulk capacitor voltage falls below the start voltage of the HV generator V
HVstart
in order for
the unit to restart, which may take even several seconds.
Circuit b) senses the mains voltage directly, upstream the bridge rectifier. It can be
configured either for half-wave sensing (only the line/neutral wire is sensed) or full-wave
sensing (both neutral and line are sensed); in the first case, assuming C
the sensed voltage will be equal to 1/
will be equal to 2/
π the peak mains voltage. C
π the peak mains voltage, while in the second case it
needs to be quite a big capacitor (in the uF)
F
is large enough,
F
to have small residual ripple superimposed on the dc level; as a rule-of-thumb, use a time
constant R
at least 4-5 times the maximum line cycle period in case of half-wave
L ·CF
sensing, 2-3 times in case of full-wave sensing. Then fine tune if needed, considering also
transient conditions such as mains missing cycles. Brownout level will not depend on the
load. When the input source is removed C
will be discharged after some ten ms then this
F
circuit is suitable to have a quick restart after a latched shutdown.
The AC_OK pin is a high impedance input connected to high value resistors, thus it is prone
to pick up noise, which might alter the OFF threshold when the converter is running or give
origin to undesired switch-off of the device during ESD tests. It is possible to bypass the pin
to ground with a small film capacitor (e.g. 1-10 nF) to prevent any malfunctioning of this kind.
The voltage on the pin is clamped upwards at about 3.15 V; then, if the function is not used
the pin has to be connected to Vcc through a resistor (220 to 680 kΩ).
39/51
Page 40
Application informationL6566B
5.13 Slope compensation
The pin MODE/SC (12), when not connected to VREF, provides a voltage ramp during
MOSFET’s ON-time synchronous to that of the internal oscillator sawtooth, with 0.8 mA
minimum current capability. This ramp is intended for implementing additive slope
compensation on current sense. This is needed to avoid the sub-harmonic oscillation that
arises in all peak-current-mode-controlled converters working at fixed frequency in
continuous conduction mode with a duty cycle close to or exceeding 50 %.
Figure 27. Slope compensation waveforms
Internal
oscillator
GD
(pin 4)
MODE/SC
(pin 12)
t
t
t
The compensation will be realized by connecting a programming resistor between this pin
and the current sense input (pin 7, CS). The CS pin has to be connected to the sense
resistor with another resistor to make a summing node on the pin. Since no ramp is
delivered during MOSFET OFF-time (see
Figure 27), no external component other than the
programming resistor is needed to ensure a clean operation at light loads.
Note:The addition of the slope compensation ramp will reduce the available dynamics of the
current signal; thereby, the value of the sense resistor must be determined taking this into
account. Note also that the burst-mode threshold (in terms of power) will be slightly
changed.
If slope compensation is not required with FF operation, the pin shall be left floating.
40/51
Page 41
L6566BApplication information
5.14 Summary of L6566B power management functions
It has been seen that the device is provided with a number of power management functions:
multiple operating mode upon loading conditions and protection functions. To help the
designer familiarize with these functions, in the following tables all of theme are summarized
with their respective activation mechanism and the resulting status of the most important
pins. This can be useful not only for a correct use of the IC but also for diagnostic purposes:
especially at prototyping/debugging stage, it is quite common to bump into unwanted
activation of some function, and these tables can be used as a sort of quick troubleshooting
guide.
Table 5.L6566B light load management features
IC
Feature Description
Controlled
ON-OFF
Burst
mode
operation for
low power
consumptio
n at light
load
Caused
by
V
COMP
V
COMPBM
- Hys
<
behavior
Pulse
skipping
operation
Vcc_restart
(V)
N.A.1.34 mA5unchanged
Consump.
(Iqdis,mA)
VREF
(V)
SS
VCOMP
(V)
V
COMPBM
-HYS
V
COMPBM
to
OSC
FMOD
(V)
0/10
41/51
Page 42
Application informationL6566B
Table 6.L6566B protections
Vcc
IC Iq
Protection Description Caused by
V
ZCD>VZCDt
for 4
h
consecutive
switching
cycles
OVP
Output
overvoltage
protection
VFF >
VFFlatch
V
COMP
=V
COMPHi
VSS >
OLP
Output
overload
protection
V
SSDIS
V
COMP
=V
COMPHi
VSS >
V
SSLAT
V
COMP
=V
COMPHi
VSS >
Short circuit
protection
2nd OCP
Output short
circuit
protection
Transformer
saturation or
shorted
secondary
diode
protection
(4)
V
SSDIS
V
COMP
=V
COMPHi
VSS >
(6)
V
SSLAT
VCS >
V
CSDIS
for 2-3
consecutive
switching
cycles
Externally
settable
OTP
overtempera
ture
protection
V
DIS>VOTP
Internal
thermal
Tj > 160oC
shutdown
Brownout
Reference
drift
Shutdown1
Mains
undervoltag
e protection
V
drift
REF
protection
Gate driver
disable
V
AC_OK
V
th
V
> VovLatched13.50.33000000
REF
VFF > V
(mA)
VREF
(V)
(6)
SS
unchanged
(6)
IC
behavior
Auto
(1)
restart
restart
(V)
52.25
Latched13.50.33000000
Auto
restart
(2)
51.465
(6)
<V
VSS
SSLAT
Latched13.50.33000000
Auto
restart
51.460
<V
VSS
SSLAT
Latched13.50.33000000
Latched50.33000000
Latched13.50.33000000
<
off
Auto
restart
Auto
restart
Auto
restart
50.33000000
(5)
50.3300000unchanged
52.55unchanged
VCOMP
(V)
OSC
(V)
FMODVFF
000unchanged
V
(3)
(6)
COMPHi
(6)
V
COMPHi
(5)
unchang
ed
00unchanged
uncha
1
nged
0unchanged
unchanged
42/51
Page 43
L6566BApplication information
Table 6.L6566B protections (continued)
Vcc
IC Iq
Protection Description Caused by
IC
behavior
restart
(V)
(mA)
VREF
(V)
SS
VCOMP
(V)
OSC
(V)
FMODVFF
Shutdown
Shutdown2
by V
COMP
low
Shutdown
by V
going
cc
ADAPTIVE
UVLO
below V
(lowering of
V
ccoff
threshold at
light load)
1. Use One external diode from V
2. Use one external diode from SS (#14) to V
ccoff
V
<
COMP
V
COMPOFF
V
< 9.4V
cc
(
VCOMP
V
COMPL
V
< 7.2V
cc
(
VCOMP
V
COMPO
FF
Latched100.33000000
>
)
Auto
restart
5 V
>
)
(#15) to AC_OK (#16), cathode to AC_OK
(#10), cathode to V
REF
0.18
mA
00 000 0
REF
3. If Css and the Vcc capacitor are such that Vcc falls below UVLO before latch tripping (Figure 21 on page 34)
4. If C
5. When T
and the Vcc capacitor are such that the latch is tripped before V
ss
< 110 oC
J
6. Discharged to zero by V
going below UVLO
cc
falls below UVLO (Figure 21 on page 34)
cc
It is worth reminding that “Auto-restart” means that the device will work intermittently as long
as the condition that is activating the function is not removed; “Latched” means that the
device is stopped as long as the unit is connected to the input power source and the unit
must be disconnected for some time from the source in order for the device (and the unit) to
restart. Optionally, a restart can be forced by pulling the voltage of pin 16 (AC_OK) below
Table 7.External circuits that determine IC behavior upon OVP and OCP
F1
fuse
CX1CX2
Lx
AC_OK
16
VFF
15
DIS
8
10
NTC2
R12
C4R6
VREF
NTC1
CY2
R16
121
IC1
OSC
C5
B1
C1
Vcc
HVS
91413
COMP
SS
ZCD
11
5
GD
4
CS
7
3
GND
C6
R18
C3
R3
R4
D3 1N4148
R1
D1
R2
R17
D2
1N4148
C2
T1
D4
C8A,B
C7 2.2 nF Y 1
Q1
R5
CY1
MODE/SC
L6566B
6
FMOD
R11
C10
OVP latchedOVP auto-restart
OCP latched
OCP auto-restart
VFF
RFF ≈10 R
VFF
16
15
16
15
SSVREF
1410
L6566B
L2
1N4148
SSVREF
1410
L6566B
H
R
R
L1
L2
R
AC_OK
FF
R
R
RL1
R
H
L2
AC_OK
RFF
RH
R
L1
RL2
AC_OK
VFF
Diode needed if
R
H
R
L1
R
L2
SSVREF
AC_OK
1410
16
15
VFF
Diode needed if
IC3 PC817A
1
4
3
2
TL431
SSVREF
1410
16
L6566B
15
⋅+
R
+
1
R
1N4148
L6566B
⋅+
R
1L
1
+
R
2L
Vout
R7
R9
C9
R8
R10
−
3
R103133
1L
46
...≥
1L
2L
3
−
R103133
1L
46
...≥
45/51
Page 46
Application examples and ideasL6566B
Figure 31. Frequency foldback at light load (FF operation)
R1
MODE/SC
12
L6566B
OSC
T
R
Vre f
10
COMP
9
13
R2
BC857C
Figure 32. Latched shutdown upon mains overvoltage
Vcc
L6566B
BC847
5
DIS
8
15
VFF
Vin
>10 Rq
DIS
8
BC857
Vref
10
L6566B
15
VFF
Vin
Rq
46/51
Page 47
L6566BPackage mechanical data
7 Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
47/51
Page 48
Package mechanical dataL6566B
Table 8.SO16N mechanical data
mm. inch
Dim.
Min TypMaxMin TypMax
A 1.75 0.069
a1 0.1 0.25 0.004 0.009
a2 1.6 0.063
b 0.35 0.46 0.014 0.018
b1 0.19 0.25 0.007 0.010
C 0.5 0.020
c1 45° (typ.)
D
E 5.8 6.2 0.228 0.244
e 1.27 0.050
e3 8.89 0.350
F
G 4.60 5.30 0.181 0.208
L 0.4 1.27 0.150 0.050
9.8 10 0.386 0.394
3.8 4.0 0.150 0.157
M 0.62 0.024
S 8°(max.)
Figure 33. Package dimensions
48/51
Page 49
L6566BOrder codes
8 Order codes
Table 9.Order codes
Order codesPackagePackaging
L6566BSO16NTube
L6566BTRSO16NTape and reel
49/51
Page 50
Revision historyL6566B
9 Revision history
Table 10.Document revision history
DateRevisionChanges
20-Aug-20071First release
29-May-20082Updated Figure 29 on page 44, Table 2 on page 11
50/51
Page 51
L6566B
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