Datasheet L6228Q Datasheet (ST)

DMOS driver for bipolar stepper motor

Features

■ Operating supply voltage from 8 to 52 V

■ 2.8 A output peak current (1.4 A RMS)

■ R

■ Operating frequency up to 100 kHz

■ Non dissipative overcurrent protection

■ Dual independent constant t

current controllers

■ Fast/slow decay mode selection

■ Fast decay quasi-synchronous rectification

■ Decoding logic for stepper motor full and half

step drive

■ Cross conduction protection

■ Thermal shutdown

■ Undervoltage lockout

■ Integrated fast free wheeling diodes

Applications

■ Bipolar stepper motor

Figure 1. Block diagram

0.73 Ω typ. value @ TJ = 25 °C

DS(on)

OFF

PWM

L6228Q

VFQFPN32 5 mm x 5 mm

Description

The L6228Q is a DMOS fully integrated stepper
motor driver with non-dissipative overcurrent
protection, realized in BCDmultipower technology,
which combines isolated DMOS power transistors
with CMOS and bipolar circuits on the same chip.
The device includes all the circuitry needed to
drive a two-phase bipolar stepper motor including:
a dual DMOS full bridge, the constant off time
PWM current controller that performs the
chopping regulation and the phase sequence
generator, that generates the stepping sequence.
Available in VFQFPN32 5 mm x 5 mm package,
the L6228Q features a non-dissipative
overcurrent protection on the high side power
MOSFETs and thermal shutdown.

VCP

V

BOOT

CHARGE

PUMP

THERMAL

EN

PROTECTION

STEPPING

SEQUENCE

GENERATION

VOLTAGE

REGULATOR

5V10V

OCD

OCD

A

B

OVER

CURRENT

DETECTION

GATE

LOGIC

OVER

CURRENT

DETECTION

GATE

LOGIC

V

BOOT

10V 10V

ONE SHOT

MONOSTABLE

MASKING

PWM

TIME

V

BOOT

SENSE

COMPARATOR

BRIDGE A

BRIDGE B

+

-

D01IN1225

VS

A

OUT1

OUT2

SENSE

VREF

RC

A

VS

B

OUT1

OUT2

SENSE

VREF

RC

B

A

A

A

A

B

B

B

B

VBOOT

CONTROL

HALF/FULL

CLOCK

RESET

CW/CCW

August 2010 Doc ID 14321 Rev 4 1/32

www.st.com

32

Contents L6228Q

Contents

1 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.2 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

4 Circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4.1 Power stages and charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4.2 Logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.3 PWM current control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.4 Decay modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.5 Stepping sequence generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.6 Half step mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.7 Normal drive mode (full-step two-phase-on) . . . . . . . . . . . . . . . . . . . . . . 18

4.8 Wave drive mode (full-step one-phase-on) . . . . . . . . . . . . . . . . . . . . . . . 18

4.9 Non-dissipative overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.10 Thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

6 Output current capability and IC power dissipation . . . . . . . . . . . . . . 25

7 Thermal management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

9 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

2/32 Doc ID 14321 Rev 4

L6228Q Electrical data

1 Electrical data

1.1 Absolute maximum ratings

Table 1. Absolute maximum ratings

Symbol Parameter Parameter Value Unit

V

V

V

BOOT

V

IN,VEN

V

REFA

V

RCA, VRCB

V

SENSEA,

V

SENSEB

I

S(peak)

T

stg

OD

, V

I

, T

S

S

Supply voltage

Differential voltage between
VSA, OUT1A, OUT2A, SENSEA and

, OUT1B, OUT2B, SENSE

VS

B

B

Bootstrap peak voltage

Input and enable voltage range -0.3 to +7 V

Voltage range at pins V

REFB

V

REFB

REFA

and

Voltage range at pins RCA and RC

Voltage range at pins SENSEA and
SENSE

B

Pulsed supply current (for each VS
pin), internally limited by the
overcurrent protection

RMS supply current (for each VS pin)

Storage and operating temperature

OP

range

B

VSA =

VSB = V

VSA =

VSB = VS = 60 V;

V

SENSEA

= V

GND

VSA =

VSB = V

VSA =

VSB = VS;

< 1 ms

t

PULSE

VSA =

VSB = V

S

SENSEB

S

S

1.2 Recommended operating conditions

60 V

=

60 V

VS + 10 V

-0.3 to +7 V

-0.3 to +7 V

-1 to +4 V

3.55 A

1.4 A

-40 to 150 °C

Table 2. Recommended operating conditions

Symbol Parameter Parameter Min Max Unit

V

REFA

V

V

V

S

V

OD

, V

SENSEA,

SENSEB

I

OUT

T

j

f

sw

Supply voltage

Differential voltage between

, OUT1A, OUT2A, SENSEA and

VS

A

VSB, OUT1B, OUT2B, SENSE

Voltage range at pins V

REFB

V

REFB

Voltage range at pins SENSEA and
SENSE

B

REFA

B

and

VSA =

VSB = V

VSA =

VSB = VS;

V

SENSEA

= V

SENSEB

(pulsed tW < trr)
(DC)

S

852V

-0.1 5 V

-6

-1

RMS output current 1.4 A

Operating junction temperature -25 +125 °C

Switching frequency 100 kHz

Doc ID 14321 Rev 4 3/32

52 V

6
1

V
V

Electrical data L6228Q

1.3 Thermal data

Table 3. Thermal data

Symbol Parameter Value Unit

R

th(JA)

1. Mounted on a double-layer FR4 PCB with a dissipating copper surface of 0.5 cm2 on the top side plus 6
cm2 ground layer connected through 18 via holes (9 below the IC).

Thermal resistance junction-ambient max

(1)

.

42 °C/W

4/32 Doc ID 14321 Rev 4

L6228Q Pin connection

2 Pin connection

Figure 2. Pin connection (top view)

Note: 1 The pins 2 to 8 are connected to die PAD.

2 The die PAD must be connected to GND pin.

Doc ID 14321 Rev 4 5/32

Pin connection L6228Q

Table 4. Pin description

N° Pin Type Function

1, 21 GND GND Ground terminals.

9OUT1BPower output Bridge B output 1.

RC network pin. A parallel RC network connected between this pin and
ground sets the current controller OFF-time of the bridge B.

Bridge B source pin. This pin must be connected to power ground through a
sensing power resistor.

Bridge B current controller reference voltage.
Do not leave this pin open or connected to GND.

Step mode selector. HIGH logic level sets HALF STEP mode, LOW logic level
sets FULL STEP mode.
If not used, it has to be connected to GND or +5 V.

Decay mode selector. HIGH logic level sets SLOW DECAY mode. LOW logic
level sets FAST DECAY mode.
If not used, it has to be connected to GND or +5 V.

Chip enable. LOW logic level switches OFF all power MOSFETs of both
bridge A and bridge B. This pin is also connected to the collector of the

(1)

overcurrent and thermal protection to implement over current protection.
If not used, it has to be connected to +5 V through a resistor.

Bootstrap voltage needed for driving the upper power MOSFETs of both
bridge A and bridge B.

Bridge B power supply voltage. It must be connected to the supply voltage
together with pin VS

A

Bridge A power supply voltage. It must be connected to the supply voltage
together with pin VS

B

Reset pin. LOW logic level restores the home state (state 1) on the phase
sequence generator state machine.
If not used, it has to be connected to +5 V.

Bridge A current controller reference voltage.
Do not leave this pin open or connected to GND.

Selects the direction of the rotation. HIGH logic level sets clockwise direction,
whereas LOW logic level sets counterclockwise direction.
If not used, it has to be connected to GND or +5 V.

Bridge A source pin. This pin must be connected to power ground through a
sensing power resistor.

RC network pin. A parallel RC network connected between this pin and
ground sets the current controller OFF-time of the bridge A.

Power supply

B

Analog input

Logic input

RC pin

11 RC

B

12 SENSE

13 VREF

HALF/FULL

14

B

15 CONTROL Logic input

16 EN Logic input

17 VBOOT

19 OUT2

20 VS

22 VS

B

A

B

Supply
voltage

Power output Bridge B output 2.

Power supply

Power supply

23 OUT2APower output Bridge A output 2.

24 VCP Output Charge pump oscillator output.

25 RESET Logic input

26 VREF

Analog Input

A

27 CLOCK Logic input Step clock input. The state machine makes one step on each rising edge.

28 CW/CCW Logic input

29 SENSE

30 RC

31 OUT1

1. Also connected at the output drain of the over current and thermal protection MOSFET. Therefore, it has to be driven

putting in series a resistor with a value in the range of 2.2 kΩ - 180 kΩ, recommended 100 kΩ

Power supply

A

A

A

RC pin

Power output Bridge A output 1.

6/32 Doc ID 14321 Rev 4

L6228Q Electrical characteristics

3 Electrical characteristics

Table 5. Electrical characteristics (TA = 25 °C, Vs = 48 V, unless otherwise specified)

Symbol Parameter Test condition Min Typ Max Unit

V

Sth(ON)

V

Sth(OFF)

I

T

j(OFF)

S

Turn-on threshold 5.8 6.3 6.8 V

Turn-off threshold 5 5.5 6 V

Quiescent supply current

All bridges OFF;
TJ = -25 °C to 125 °C

Thermal shutdown temperature 165 °C

Output DMOS transistors

= 25 °C 1.47 1.69 Ω

T

R

DS(on)

High-side + low-side switch ON
resistance

J

=125 °C

T

J

(1)

EN = Low; OUT = V

I

DSS

Leakage current

EN = Low; OUT = GND -0.3 mA

Source drain diodes

V

SD

t

rr

t

fr

Forward ON voltage ISD = 1.4 A, EN = LOW 1.15 1.3 V

Reverse recovery time If = 1.4 A 300 ns

Forward recovery time 200 ns

Logic inputs (EN, CONTROL, HALF/FULL, CLOCK, RESET, CW/CCW)

V

V

I

I

V

th(ON)

V

th(OFF)

V

th(HYS)

IH

IL

IH

Low level logic input voltage -0.3 0.8 V

IL

High level logic input voltage 2 7 V

Low level logic input current GND logic input voltage -10 µA

High level logic input current 7 V logic input voltage 10 µA

Turn-on input threshold 1.8 2.0 V

Turn-off input threshold 0.8 1.3 V

Input threshold hysteresis 0.25 0.5 V

Switching characteristics

(1)

510mA

2.35 2.70 Ω

S

2mA

t

D(ON)EN

t

D(OFF)EN

t

RISE

t

FAL L

t

DCLK

t

CLK(min)L

t

CLK(min)H

Enable to output turn-on delay

(2)

time

Enable to output turn-off delay time

Output rise time

Output fall time

Clock to output delay time

Minimum clock time

Minimum clock time

(2)

(2)

(3)

(4)

(4)

Doc ID 14321 Rev 4 7/32

(2)

I

=1.4 A, resistive load

LOAD

500 650 800 ns

500 800 1000 ns

40 250 ns

40 250 ns

2µs

1µs

1µs

Electrical characteristics L6228Q

Table 5. Electrical characteristics (continued) (TA = 25 °C, Vs = 48 V, unless otherwise specified)

Symbol Parameter Test condition Min Typ Max Unit

f

CLK

t

S(MIN)

t

H(MIN)

t

R(MIN)

t

RCLK(MIN)

t

DT

f

CP

Clock frequency 100 kHz

Minimum set-up time

Minimum hold time

Minimum reset time

(5)

(5)

(5)

Minimum reset to clock delay time

Dead time protection 0.5 1 µs

Charge pump frequency

PWM comparator and monostable

I

RCA, IRCB

V

offset

t

PROP

t

BLANK

t

ON(MIN)

t

OFF

I

BIAS

Source current at pins RCA and RC

Offset voltage on sense comparator V

Turn OFF propagation delay

Internal blanking time on SENSE pins 1 µs

Minimum on time 2.5 3 µs

PWM recirculation time

Input bias current at pins VREFA and
VREF

B

Over current protection

1µs

1µs

1µs

(5)

(6)

TJ = -25 °C to 125 °C

V

B

= V

RCA

REFA, VREFB

R

= 20 kΩ; C

OFF

= 100 kΩ; C

R

OFF

= 2.5 V 3.5 5.5 mA

RCB

= 0.5 V ±5 mV

(1)

0.6 1 MHz

500 ns

= 1 nF 13 µs

OFF

= 1 nF 61 µs

OFF

1µs

10 µA

I

SOVER

R

OPDR

t

OCD(ON)

t

OCD(OFF)

1. Tested at 25 °C in a restricted range and guaranteed by characterization

2. See Figure 3.

3. See Figure 4.

4. See Figure 5.

5. See Figure 6.

6. Measured applying a voltage of 1 V to pin SENSE and a voltage drop from 2 V to 0 V to pin VREF.

7. See Figure 7.

Input supply overcurrent protection
threshold

Open drain ON resistance I = 4 mA 40 60 W

OCD turn-on delay time

OCD turn-off delay time

(7)

(7)

T

= -25 °C to 125 °C

j

I = 4 mA; CEN < 100 pF 200 ns

I = 4 mA; CEN < 100 pF 100 ns

(1)

2.8 A

8/32 Doc ID 14321 Rev 4

L6228Q Electrical characteristics

Figure 3. Switching characteristic definition

EN

V

th(ON)

V

th(OFF)

t

I

OUT

90%

10%

D01IN1316

t

D(OFF)EN

t

FALL

t

D(ON)EN

t

t

RISE

Figure 4. Clock to output delay time

CLOCK

V

th(ON)

I

OUT

D01IN1317

Figure 5. Minimum timing definition; clock input

CLOCK

t

DCLK

t

t

V

th(OFF)

V

th(ON)

t

CLK(MIN)L

V

th(OFF)

t

CLK(MIN)H

D01IN1318

Doc ID 14321 Rev 4 9/32

Electrical characteristics L6228Q

Figure 6. Minimum timing definition; logic inputs

CLOCK

V

th(ON)

LOGIC INPUTS

t

S(MIN)

RESET

V

th(OFF)

V

th(ON)

t

R(MIN)

t

RCLK(MIN)

Figure 7. Overcurrent detection timing definition

I

OUT

I

SOVER

t

H(MIN)

D01IN1319

ON

BRIDGE

OFF

V

EN

90%

10%

t

OCD(ON)

t

OCD(OFF)

D02IN1399

10/32 Doc ID 14321 Rev 4

L6228Q Circuit description

8

4 Circuit description

4.1 Power stages and charge pump

The L6228Q integrates two independent power MOS full bridges. Each power MOS has an
R
patterns are generated by the PWM Current Controller and the Phase Sequence Generator
(see below). Cross conduction protection is achieved using a dead time (t
value) between the switch off and switch on of two power MOSFETs in one leg of a bridge.

= 0.73 Ω (typical value @ 25 °C), with intrinsic fast freewheeling diode. Switching

DS(on)

= 1 μs typical

DT

Pins VS

and VSB must be connected together to the supply voltage VS. The device

A

operates with a supply voltage in the range from 8 V to 52 V. It has to be noticed that the
R

increases of some percents when the supply voltage is in the range from 8 V to

DS(on)

12 V.

Using N-channel power MOS for the upper transistors in the bridge requires a gate drive
voltage above the power supply voltage. The bootstrapped supply voltage V

is obtained

BOOT

through an internal Oscillator and few external components to realize a charge pump circuit
as shown in Figure 8. The oscillator output (VCP) is a square wave at 600 kHz (typical) with
10V amplitude. Recommended values/part numbers for the charge pump circuit are shown
in Ta bl e 6 .

Table 6. Charge pump external components values

Component Value

C

BOOT

C

P

D1 1N4148

D2 1N4148

220 nF

10 nF

Figure 8. Charge pump circuit

V

S

D1

D2

C

P

VCP VBOOT VS

Doc ID 14321 Rev 4 11/32

C

BOOT

VS

B

D01IN132

A

Circuit description L6228Q

0

4.2 Logic inputs

Pins CONTROL, HALF/FULL, CLOCK, RESET and CW/CCW are TTL/CMOS and
microcontroller compatible logic inputs. The internal structure is shown in Figure 9. Typical
value for turn-on and turn-off thresholds are respectively V

Pin EN (Enable) has identical input structure with the exception that the drain of the
Overcurrent and thermal protection MOSFET is also connected to this pin. Due to this
connection some care needs to be taken in driving this pin. The EN input may be driven in
one of two configurations as shown in Figure 10 or Figure 11. If driven by an open drain
(collector) structure, a pull-up resistor R

and a capacitor CEN are connected as shown in

EN

Figure 10. If the driver is a standard Push-Pull structure the resistor R

C

are connected as shown in Figure 11. The resistor REN should be chosen in the range

EN

from 2.2 kΩ to 180 kΩ. Recommended values for R

and CEN are respectively 100 kΩ and

EN

5.6nF. More information on selecting the values is found in the overcurrent protection

section.

Figure 9. Logic inputs internal structure

5V

= 1.8 V and V

th(ON)

= 1.3 V.

th(OFF)

and the capacitor

EN

ESD

PROTECTION

Figure 10. EN pin open collector driving

5V

R

EN

OPEN

COLLECTOR

OUTPUT

C

EN

EN

PROTECTION

Figure 11. EN pin push-pull driving

R

PUSH-PULL

OUTPUT

EN

C

EN

EN

D01IN1329

5V

ESD

D01IN133

5V

ESD

PROTECTION

D01IN1331

12/32 Doc ID 14321 Rev 4

L6228Q Circuit description

4.3 PWM current control

The L6228Q includes a constant off time PWM current controller for each of the two bridges.
The current control circuit senses the bridge current by sensing the voltage drop across an
external sense resistor connected between the source of the two lower power MOS
transistors and ground, as shown in Figure 12. As the current in the motor builds up the
voltage across the sense resistor increases proportionally. When the voltage drop across
the sense resistor becomes greater than the voltage at the reference input (VREF
VREF

) the sense comparator triggers the monostable switching the bridge off. The power

B

MOS remain off for the time set by the monostable and the motor current recirculates as
defined by the selected decay mode, described in the next section. When the monostable
times out the bridge will again turn on. Since the internal dead time, used to prevent cross
conduction in the bridge, delays the turn on of the power MOS, the effective off time is the
sum of the monostable time plus the dead time.

Figure 12. PWM current controller simplified schematic

VS

(or B)

A

S

R

BLANKING TIME

MONOSTABLE

MONOSTABLE

SET

1μs

BLANKER

SENSE

COMPARATOR

COMPARATOR

OUTPUT

GATE DRIVERS

DRIVERS

+

DEAD TIME

+

-

VREF

FROM THE

LOW-SIDE

A(or B)

2H 1H

DRIVERS

+

DEAD TIME

2L 1L

SENSE

R

SENSE

A(or B)

OUT2

OUT1

I

OUT

A(or B)

A(or B)

D01IN1332

TO GATE LOGIC

5mA

RC

R

Q

-

+

2.5V

A(or B)

OFF

(0) (1)

5V

C

OFF

or

A

2 PHASE

STEPPER MOTOR

Figure 13 shows the typical operating waveforms of the output current, the voltage drop

across the sensing resistor, the RC pin voltage and the status of the bridge. More details
regarding the Synchronous Rectification and the output stage configuration are included in
the next section.

Immediately after the power MOS turns on, a high peak current flows through the sensing
resistor due to the reverse recovery of the freewheeling diodes. The L6228Q provides a 1 μs
blanking time t

that inhibits the comparator output so that this current spike cannot

BLANK

prematurely re-trigger the monostable.

Doc ID 14321 Rev 4 13/32

Circuit description L6228Q

Figure 13. Output current regulation waveforms

I

OUT

V

REF

R

SENSE

t

OFF

V

SENSE

V

REF

0

V

RC

5V

2.5V

ON

SYNCHRONOUS OR QUASI
SYNCHRONOUS RECTIFICATION

OFF

D01IN1334

1μs t

Slow Decay Slow Decay

Fast Decay

t

RCRISE

t

RCFALL

1μs t

BC

Figure 14 shows the magnitude of the Off Time t

BLANK

DT

OFF

t

ON

DDA

versus C

OFF

t

OFF

1μs t

BLANK

Fast Decay

t

RCRISE

t

RCFALL

1μs t

DT

BC

and R

values. It can be

OFF

approximately calculated from the equations:

t

RCFALL

t

OFF

where R

= t

OFF

and C

= 0.6 · R

RCFALL

+ tDT = 0.6 · R

OFF

OFF

· C

OFF

OFF

· C

OFF

+ t

DT

are the external component values and tDT is the internally generated

Dead Time with:

20 kΩ ≤ R

0.47 nF ≤ C

t

= 1 µs (typical value)

DT

≤ 100 kΩ

OFF

OFF

≤ 100 nF

Therefore:

t

OFF(MIN)

t

OFF(MAX)

These values allow a sufficient range of t

The capacitor value chosen for C
pin RCOFF. The Rise Time t

= 6.6 µs

= 6 ms

OFF

RCRISE

to implement the drive circuit for most motors.

OFF

also affects the Rise Time t

RCRISE

of the voltage at the

will only be an issue if the capacitor is not completely
charged before the next time the monostable is triggered. Therefore, the on time t
depends by motors and supply parameters, has to be bigger than t
good current regulation by the PWM stage. Furthermore, the on time t
than the minimum on time t

ON(MIN)

.

for allowing a

RCRISE

can not be smaller

ON

, which

ON

14/32 Doc ID 14321 Rev 4

L6228Q Circuit description

t

> 2.5μs=

⎧⎫

ONtON MIN()

⎨⎬

t

⎩⎭

ONtRCRISEtDT

–>

(typ. value)

t

RCRISE

= 600 · C

OFF

Figure 15 shows the lower limit for the on time tON for having a good PWM current regulation

capacity. It has to be said that t
this condition, but it can be smaller than t
to work but the off time t

So, small C

value gives more flexibility for the applications (allows smaller on time and,

OFF

OFF

therefore, higher switching frequency), but, the smaller is the value for C

is always bigger than t

ON

RCRISE

is not more constant.

ON(MIN)

because the device imposes

- tDT. In this last case the device continues

, the more

OFF

influential will be the noises on the circuit performance.

Figure 14. t

versus C

OFF

s]

μ

toff [

1.10

1.10

100

and R

OFF

4

3

10

OFF

= 100k

R

off

= 47k

R

= 20k

R

Ω

off

Ω

off

Ω

1

0.1 1 10 100
Coff [nF]

Doc ID 14321 Rev 4 15/32

Circuit description L6228Q

Figure 15. Area where tON can vary maintaining the PWM regulation

100

10

ton(min) [us]

1

0.1 1 10 100

2.5μs (typ. valu e)

Coff [nF]

4.4 Decay modes

The CONTROL input is used to select the behavior of the bridge during the off time. When
the CONTROL pin is low, the fast decay mode is selected and both transistors in the bridge
are switched off during the off time. When the CONTROL pin is high, the slow decay mode
is selected and only the low side transistor of the bridge is switched off during the off time.

Figure 16 shows the operation of the bridge in the fast decay mode. At the start of the off

time, both of the power MOS are switched off and the current recirculates through the two
opposite free wheeling diodes. The current decays with a high dI/dt since the voltage across
the coil is essentially the power supply voltage. After the dead time, the lower power MOS in
parallel with the conducting diode is turned on in synchronous rectification mode. In
applications where the motor current is low it is possible that the current can decay
completely to zero during the off time. At this point if both of the power MOS were operating
in the synchronous rectification mode it would then be possible for the current to build in the
opposite direction. To prevent this only the lower power MOS is operated in synchronous
rectification mode. This operation is called quasi-synchronous rectification mode. When the
monostable times out, the power MOS are turned on again after some delay set by the dead
time to prevent cross conduction.

Figure 17 shows the operation of the bridge in the slow decay mode. At the start of the off

time, the lower power MOS is switched off and the current recirculates around the upper half
of the bridge. Since the voltage across the coil is low, the current decays slowly. After the
dead time the upper power MOS is operated in the synchronous rectification mode. When
the monostable times out, the lower power MOS is turned on again after some delay set by
the dead time to prevent cross conduction.

16/32 Doc ID 14321 Rev 4

L6228Q Circuit description

Figure 16. Fast decay mode output stage configurations

A) ON TIME B) 1μs DEAD TIME C) QUASI-SYNCHRONOUS

D01IN1335

Figure 17. Slow decay mode output stage configurations

A) ON TIME B) 1μs DEAD TIME C) SYNCHRONOUS

D01IN1336

4.5 Stepping sequence generation

The phase sequence generator is a state machine that provides the phase and enable
inputs for the two bridges to drive a stepper motor in either full step or half step. Two full step
modes are possible, the normal drive mode where both phases are energized each step
and the wave drive mode where only one phase is energized at a time. The drive mode is
selected by the HALF/FULL input and the current state of the sequence generator as
described below. A rising edge of the CLOCK input advances the state machine to the next
state. The direction of rotation is set by the CW/CCW input. The RESET input resets the
state machine to state 1.

RECTIFICATION

RECTIFICATION

D) 1μs SLOW DECAY

D) 1μs DEAD TIME

4.6 Half step mode

A HIGH logic level on the HALF/FULL input selects half step mode. Figure 18 shows the
motor current waveforms and the state diagram for the phase sequencer generator.
At start-up or after a RESET the phase sequencer is at state 1. After each clock pulse the
state changes following the sequence 1,2,3,4,5,6,7,8,… if CW/CCW is high (clockwise
movement) or 1,8,7,6,5,4,3,2,… if CW/CCW is low (counterclockwise movement).

Doc ID 14321 Rev 4 17/32

Circuit description L6228Q

4.7 Normal drive mode (full-step two-phase-on)

A LOW level on the HALF/FULL input selects the full step mode. When the low level is
applied when the state machine is at an ODD numbered state the normal drive mode is
selected. Figure 19 shows the motor current waveform state diagram for the state machine
of the phase sequencer generator. The normal drive mode can easily be selected by holding
the HALF/FULL input low and applying a RESET. At start -up or after a RESET the state
machine is in state 1. While the HALF/FULL input is kept low, state changes following the
sequence 1,3,5,7,… if CW/CCW is high (Clockwise movement) or 1,7,5,3,… if CW/CCW is
low (Counterclockwise movement).

4.8 Wave drive mode (full-step one-phase-on)

A LOW level on the pin HALF/FULL input selects the full step mode. When the low level is
applied when the state machine is at an EVEN numbered state the wave drive mode is
selected. Figure 20 shows the motor current waveform and the state diagram for the state
machine of the phase sequence generator. To enter the wave drive mode the state machine
must be in an EVEN numbered state. The most direct method to select the Wave Drive
Mode is to first apply a RESET, then while keeping the HALF/FULL input high apply one
pulse to the clock input then take the HALF/FULL input low. This sequence first forces the
state machine to state 1. The clock pulse, with the HALF/FULL input high advances the
state machine from state 1 to either state 2 or 8 depending on the CW/CCW input. Starting
from this point, after each clock pulse (rising edge) will advance the state machine following
the sequence 2,4,6,8,… if CW/CCW is high (clockwise movement) or 8,6,4,2,… if CW/CCW
is low (counterclockwise movement).

Figure 18. Half step mode

324 5

6

1 8 7

Start Up or Reset

Figure 19. Normal drive mode

4

35

2

17

Start Up or Reset

6

8

D01IN1320

D01IN1322

I

OUTA

I

OUTB

CLOCK

I

OUTA

I

OUTB

CLOCK

2345678

1

1

3571357

18/32 Doc ID 14321 Rev 4

L6228Q Circuit description

Figure 20. Wave drive mode

I

OUTA

5

4

3

I

2

1

Start Up or Reset

6

8

7

D01IN1321

OUTB

CLOCK

4682468

2

4.9 Non-dissipative overcurrent protection

The L6228Q integrates an overcurrent detection circuit (OCD) for full protection. This circuit
provides protection against a short circuit to ground or between two phases of the bridge.
With this internal over current detection, the external current sense resistor normally used
and its associated power dissipation are eliminated. Figure 21 shows a simplified schematic
of the overcurrent detection circuit.

To implement the over current detection, a sensing element that delivers a small but precise
fraction of the output current is implemented with each high side power MOS. Since this
current is a small fraction of the output current there is very little additional power
dissipation. This current is compared with an internal reference current I
output current reaches the detection threshold (typically 2.8 A) the OCD comparator signals
a fault condition. When a fault condition is detected, the EN pin is pulled below the turn off
threshold (1.3 V typical) by an internal open drain MOS with a pull down capability of 4 mA.
By using an external R-C on the EN pin, the off time before recovering normal operation can
be easily programmed by means of the accurate thresholds of the logic inputs.

. When the

REF

Doc ID 14321 Rev 4 19/32

Circuit description L6228Q

Figure 21. Overcurrent protection simplified schematic

OUT1

POWER SENSE

1 cell

I

POWER DMOS

n cells

OVER TEMPERATURE

OCD

I

/ n

1A

(I1A+I2A) / n

I

FROM THE

BRIDGE B

μC or LOGIC

V

DD

.EN

R

EN

.

C

EN

TO GATE

R

DS(ON)

40Ω TYP.

LOGIC

OCD

COMPARATOR

INTERNAL

OPEN-DRAIN

COMPARATOR

Figure 22 shows the overcurrent detection operation. The disable time t

VS

A

1A I2A

+

REF

OUT2

A

A

POWER DMOS

n cells

I

/ n

2A

HIGH SIDE DMOSs OF

THE BRIDGE A

POWER SENSE

D01IN1337

DISABLE

before
recovering normal operation can be easily programmed by means of the accurate
thresholds of the logic inputs. It is affected whether by C
magnitude is reported in Figure 23. The delay time t

DELAY

an overcurrent has been detected depends only by C

and REN values and its

EN

before turning off the bridge when

value. Its magnitude is reported in

EN

Figure 24.

1 cell

C

is also used for providing immunity to pin EN against fast transient noises. Therefore

EN

the value of C
delay time and the R

The resistor R
values for R

should be chosen as big as possible according to the maximum tolerable

EN

EN

and CEN are respectively 100 kΩ and 5.6 nF that allow obtaining 200 μs

EN

value should be chosen according to the desired disable time.

EN

should be chosen in the range from 2.2 kΩ to 180 kΩ. Recommended

disable time.

20/32 Doc ID 14321 Rev 4

L6228Q Circuit description

Figure 22. Overcurrent protection waveforms

I

OUT

I

SOVER

V

EN

V

DD

V

th(ON)

V

th(OFF)

V

EN(LOW)

ON

OCD

OFF

ON

BRIDGE

OFF

t

OCD(ON)

t

DELAY

t

EN(FALL)

t

D(OFF)EN

t

OCD(OFF)

t

DISABLE

t

EN(RISE)

t

D(ON)EN

D02IN1400

Doc ID 14321 Rev 4 21/32

Circuit description L6228Q

Figure 23. t

1.10

1.10

[µs]

[µs]

DISABLE

DISABLE

t

t

Figure 24. t

DISABLE

100

100

DELAY

versus CEN and REN (VDD = 5 V)

Ω

REN= 220 k

3

3

10

10

1

1

1 10 100

1 10 100

versus C

10

REN= 220 k

EN (VDD

Ω

CEN[nF ]

CEN[nF ]

= 5 V)

REN= 100 k

REN= 100 k

Ω

Ω

R

R

EN

EN

R

R

EN

EN

R

R

EN

EN

= 47 k

= 47 k

= 33 k

= 33 k

= 10 k

= 10 k

Ω

Ω
Ω

Ω

Ω

Ω

s]

μ

1

tdelay [

0.1
110100

4.10 Thermal protection

In addition to the overcurrent protection, the L6228Q integrates a thermal protection for
preventing the device destruction in case of junction over temperature. It works sensing the
die temperature by means of a sensible element integrated in the die. The device switch-off
when the junction temperature reaches 165 °C (typ. value) with 15 °C hysteresis
(typ. value).

Cen [nF]

22/32 Doc ID 14321 Rev 4

L6228Q Application information

5 Application information

A typical bipolar stepper motor driver application using L6228Q is shown in Figure 25.
Typical component values for the application are shown in Tab le 7 . A high quality ceramic
capacitor in the range of 100 to 200 nF should be placed between the power pins (VS
VS

) and ground near the L6228Q to improve the high frequency filtering on the power

B

supply and reduce high frequency transients generated by the switching. The capacitor
connected from the EN input to ground sets the shut down time when an over current is
detected (see overcurrent protection). The two current sensing inputs (SENSE
SENSE

) should be connected to the sensing resistors with a trace length as short as

B

and

A

possible in the layout. The sense resistors should be non-inductive resistors to minimize the
dI/dt transients across the resistor. To increase noise immunity, unused logic pins (except
EN) are best connected to 5 V (high logic level) or GND (low logic level) (see pin
description). It is recommended to keep power ground and signal ground separated on PCB.

Table 7. Component values for typical application

Component Value

and

A

C

C

C

C

C

BOOT

C

C

C

REF

D

D

R

R

R

R

SENSEA

R

SENSEB

EN

EN

1

2

A

B

100 µF

100 nF

1 nF

1 nF

220 nF

P

10 nF

5.6 nF

68 nF

1

2

A

B

1N4148

1N4148

39 kΩ

39 kΩ

100 kΩ

0.6 Ω

0.6 Ω

Doc ID 14321 Rev 4 23/32

Application information L6228Q

Figure 25. Typical application

Note: To reduce the IC thermal resistance, therefore improve the dissipation path, the NC pins can

be connected to GND.

24/32 Doc ID 14321 Rev 4

L6228Q Output current capability and IC power dissipation

6 Output current capability and IC power dissipation

In Figure 26, Figure 27, Figure 28 and Figure 29 are shown the approximate relation
between the output current and the IC power dissipation using PWM current control driving
a two-phase stepper motor, for different driving sequences:

● HALF STEP mode (Figure 26) in which alternately one phase / two phases are

energized.

● NORMAL DRIVE (FULL-STEP TWO PHASE ON) mode (Figure 27) in which two

phases are energized during each step.

● WAVE DRIVE (FULL-STEP ONE PHASE ON) mode (Figure 27) in which only one

phase is energized at each step.

● MICROSTEPPING mode (Figure 29), in which the current follows a sine-wave profile,

provided through the V

For a given output current and driving sequence the power dissipated by the IC can be
easily evaluated, in order to establish which package should be used and how large must be
the on-board copper dissipating area to guarantee a safe operating junction temperature
(125 °C maximum).

ref

pins.

Figure 26. IC power dissipation versus output current in HALF STEP mode

HALF STEP

I

[A]

OUT

I

A

I

B

I

OUT

I

OUT

Test Conditions:
Supply Voltage = 24V

No PWM
f

= 30 kHz (slow decay)

SW

PD [W]

10

8

6

4

2

0

0 0.25 0.5 0.75 1 1.25 1.5

Doc ID 14321 Rev 4 25/32

Output current capability and IC power dissipation L6228Q

Figure 27. IC power dissipation versus output current in NORMAL mode

(full step two phase on)

PD [W]

10

NORM AL DRIVE

8

6

4

2

0

0 0.25 0.5 0.75 1 1.25 1.5

I

OUT

[A]

I

A

I

B

I

OUT

I

OUT

Test Conditions:
Supply Voltage = 24 V

No PWM

= 30 kHz (slow decay)

f

SW

Figure 28. IC power dissipation versus output current in WAVE mode

(full step one phase on)

WAVE DRIVE

10

8

6

[W]

P

D

4

2

0

0 0.25 0.5 0.75 1 1.25 1.5

I

[A]

OUT

I

A

I

B

I

OUT

I

OUT

Test Conditions:
Supply Voltage = 24V

No PWM

f

= 30 kHz (slow decay)

SW

Figure 29. IC power dissipation versus output current in MICROSTEPPING mode

10

[W]

P

D

26/32 Doc ID 14321 Rev 4

MICROSTEPPING

8

6

4

2

0

0 0.25 0.5 0.75 1 1.25 1.5

[A]

I

OUT

I

A

I

B

Test Conditions:
Supply Voltage = 24V

fSW = 30 k
fSW = 50 k

I

OUT

Hz (slow decay)
Hz (slow decay)

I

OUT

L6228Q Thermal management

7 Thermal management

In most applications the power dissipation in the IC is the main factor that sets the maximum
current that can be delivered by the device in a safe operating condition. Therefore, it has to
be taken into account very carefully. Besides the available space on the PCB, the right
package should be chosen considering the power dissipation. Heat sinking can be achieved
using copper on the PCB with proper area and thickness.

For instance, using a VFQFPN32L 5x5 package the typical Rth(JA) is about 42 °C/W when
mounted on a double-layer FR4 PCB with a dissipating copper surface of 0.5 cm
side plus 6 cm

2

ground layer connected through 18 via holes (9 below the IC).

2

on the top

Doc ID 14321 Rev 4 27/32

Package mechanical data L6228Q

8 Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.

Table 8. VFQFPN32 5x5x1.0 pitch 0.50

Databook (mm)

Dim.

Min Typ Max

A 0.80 0.85 0.95

b 0.18 0.25 0.30

b1 0.165 0.175 0.185

D 4.85 5.00 5.15

D2 3.00 3.10 3.20

D3 1.10 1.20 1.30

E 4.85 5.00 5.15

E2 4.20 4.30 4.40

E3 0.60 0.70 0.80

e0.50

L 0.30 0.40 0.50

ddd 0.08

Note: VFQFPN stands for thermally enhanced very thin profile fine pitch quad flat package no

lead. Very thin profile: 0.80 < A < 1.00 mm.

Details of terminal 1 are optional but must be located on the top surface of the package by
using either a mold or marked features.

28/32 Doc ID 14321 Rev 4

L6228Q Package mechanical data

Figure 30. Package dimensions

Doc ID 14321 Rev 4 29/32

Order codes L6228Q

9 Order codes

Table 9. Ordering information

Order code Package Packaging

L6228Q

VFQFPN32 5x5x1.0 mm

L6228QTR Tape and reel

Tu be

30/32 Doc ID 14321 Rev 4

L6228Q Revision history

10 Revision history

Table 10. Document revision history

Date Revision Changes

14-Jan-2008 1 First release

10-Jun-2008 2

28-Jan-2009 3 Updated value in Table 3: Thermal data on page 4

31-Aug-2010 4 Updated Ta bl e 9

Updated: Figure 25 on page 24
Added: Note 1 on page 4

Doc ID 14321 Rev 4 31/32

L6228Q

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32/32 Doc ID 14321 Rev 4