Datasheet L6227Q Datasheet (ST)

Features

■ Operating supply voltage from 8 to 52 V

■ 2.8 A output peak current (1.4 A DC)

■ R

0.73 Ω typ. value @ TJ = 25 °C

DS(on)

■ Operating frequency up to 100 kHz

■ Non dissipative overcurrent protection

■ Dual independent constant t

PWM current

OFF

controllers

■ Slow decay synchronous rectification

■ Cross conduction protection

■ Thermal shutdown

■ Under voltage lockout

■ Integrated fast free wheeling diodes

Applications

■ Bipolar stepper motor

■ Dual or quad DC motor

L6227Q

DMOS dual full bridge driver

with PWM current controller

VFQFPN32 5 mm x 5 mm

Description

The L6227Q is a DMOS dual full bridge designed
for motor control applications, realized in
BCDmultipower technology, which combines
isolated DMOS power transistors with CMOS and
bipolar circuits on the same chip. The device also
includes two independent constant off time PWM
current controllers that performs the chopping
regulation. Available in VQFPN32 5 mm x 5 mm
package, the L6227Q features a non-dissipative
overcurrent protection on the high side power
MOSFETs and thermal shutdown.

Figure 1. Block diagram

VBOOT

VCP

EN

IN1

IN2

EN

IN1

IN2

V

BOOT

CHARGE

PUMP

OCD

A

THERMAL

PROTECTION

A

A

A

VOLTAGE

REGULATOR

5V10V

OCD

B

B

B

B

OVER

CURRENT

DETECTION

GATE

LOGIC

OVER

CURRENT

DETECTION

GATE

LOGIC

V

BOOT

10V 10V

ONE SHOT

MONOSTABLE

MASKING

PWM

TIME

V

BOOT

SENSE

COMPARATOR

BRIDGE A

BRIDGE B

+

-

D99IN1085A

VS

A

OUT1

OUT2

SENSE

VREF

RC

A

V

S

B

OUT1

OUT2

SENSE

VREF

RC

B

A

A

A

A

B

B

B

B

January 2009 Rev 3 1/27

www.st.com

27

Contents L6227Q

Contents

1 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.2 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

4 Circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4.1 Power stages and charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4.2 Logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4.3 Truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.4 PWM current control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.5 Slow decay mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.6 Non-dissipative overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.7 Thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6 Output current capability and IC power dissipation . . . . . . . . . . . . . . 21

7 Thermal management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

9 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

2/27

L6227Q Electrical data

1 Electrical data

1.1 Absolute maximum ratings

Table 1. Absolute maximum ratings

Symbol Parameter Parameter Value Unit

V

V

V

BOOT

V

IN,VEN

V

REFA

V

RCA, VRCB

V

SENSEA,

V

SENSEB

I

S(peak)

T

stg

OD

, V

I

, T

S

S

Supply voltage

Differential voltage between
VSA, OUT1A, OUT2A, SENSEA and

, OUT1B, OUT2B, SENSE

VS

B

B

Bootstrap peak voltage

Input and enable voltage range -0.3 to +7 V

Voltage range at pins V

REFB

V

REFB

REFA

and

Voltage range at pins RCA and RC

Voltage range at pins SENSEA and
SENSE

B

Pulsed supply current (for each VS
pin), internally limited by the
overcurrent protection

RMS supply current (for each VS pin)

Storage and operating temperature

OP

range

B

VSA =

VSB = V

VSA =

VSB = VS = 60 V;

V

VSA =

VSA =
t

PULSE

VSA =

SENSEA

VSB = V

VSB = VS;

< 1 ms

VSB = V

= V

S

SENSEB

S

S

1.2 Recommended operating conditions

= GND

60 V

60 V

VS + 10 V

-0.3 to +7 V

-0.3 to +7 V

-1 to +4 V

3.55 A

1.4 A

-40 to 150 ° C

Table 2. Recommended operating conditions

Symbol Parameter Parameter Min Max Unit

V

REFA

V

V

V

S

V

OD

, V

SENSEA,

SENSEB

I

OUT

T

J

f

sw

Supply voltage

Differential voltage between

, OUT1A, OUT2A, SENSEA and

VS

A

VSB, OUT1B, OUT2B, SENSE

Voltage range at pins V

REFB

V

REFB

Voltage range at pins SENSEA and
SENSE

B

REFA

B

and

VSA =

VSB = V

VSA =

VSB = VS;

V

SENSEA

= V

SENSEB

(pulsed tW < trr)
(DC)

S

852V

-0.1 5 V

-6

-1

RMS output current 1.4 A

Operating junction temperature -25 +125 °C

Switching frequency 100 kHz

3/27

52 V

6
1

V
V

Electrical data L6227Q

1.3 Thermal data

Table 3. Thermal data

Symbol Parameter Value Unit

R

th(JA)

1. Mounted on a double-layer FR4 PCB with a dissipating copper surface of 0.5 cm2 on the top side plus 6
cm2 ground layer connected through 18 via holes (9 below the IC).

Thermal resistance junction-ambient max

(1)

.

42 ° C/W

4/27

L6227Q Pin connection

2 Pin connection

Figure 2. Pin connection (top view)

Note: 1 The pins 2 to 8 are connected to die PAD

2 The die PAD must be connected to GND pin

5/27

Pin connection L6227Q

Table 4. Pin description

N° Pin Type Function

1, 21 GND GND Signal ground terminals.

9OUT1BPower output Bridge B output 1.

11 RC

B

RC pin

RC network pin. A parallel RC network connected between this pin and
ground sets the current controller OFF-time of the bridge B.

12 SENSE

13 IN1

14 IN2

B

B

15 VREF

Power supply

B

Logic input Bridge B input 1

Logic input Bridge B input 2

Analog input

B

Bridge B source pin. This pin must be connected to power ground through a
sensing power resistor.

Bridge B current controller reference voltage.
Do not leave this pin open or connect to GND.

Bridge B enable. LOW logic level switches OFF all power MOSFETs of bridge
B. This pin is also connected to the collector of the overcurrent and thermal

16 EN

B

Logic input

(1)

protection transistor to implement over current protection.
If not used, it has to be connected to +5 V through a resistor.

17 VBOOT

19 OUT2

20 VS

22 VS

B

A

23 OUT2

Supply
voltage

Power output Bridge B output 2.

B

Power supply

Power supply

Power output Bridge A output 2.

A

Bootstrap voltage needed for driving the upper power MOSFETs of both
bridge A and Bridge B.

Bridge B power supply voltage. It must be connected to the supply voltage
together with pin VS

.

A

Bridge A power supply voltage. It must be connected to the supply voltage
together with pin VS

.

B

24 VCP Output Charge pump oscillator output.

Bridge A enable. LOW logic level switches OFF all power MOSFETs of bridge
A. This pin is also connected to the collector of the overcurrent and thermal

25 EN

A

Logic input

(1)

protection transistor to implement over current protection.
If not used, it has to be connected to +5 V through a resistor.

26 VREF

27 IN1

28 IN2

29 SENSE

30 RC

31 OUT1

1. Also connected at the output drain of the over current and thermal protection MOSFET. Therefore, it has to be driven

putting in series a resistor with a value in the range of 2.2 kΩ - 180 kΩ, recommended 100 kΩ.

Analog input

A

Logic input Bridge A logic input 1.

A

Logic input Bridge A logic input 2.

A

Power supply

A

A

A

RC pin

Power output Bridge A output 1.

Bridge A current controller reference voltage.
Do not leave this pin open or connect to GND.

Bridge A source pin. This pin must be connected to power ground through a
sensing power resistor.

RC network pin. A parallel RC network connected between this pin and
ground sets the current controller OFF-time of the bridge A.

6/27

L6227Q Electrical characteristics

3 Electrical characteristics

Table 5. Electrical characteristics (TA = 25 °C, Vs = 48 V, unless otherwise specified)

Symbol Parameter Test condition Min Typ Max Unit

V

Sth(ON)

V

Sth(OFF)

I

T

J(OFF)

S

Turn-on threshold 5.8 6.3 6.8 V

Turn-off threshold 5 5.5 6 V

Quiescent supply current

All Bridges OFF;

= -25 °C to 125 °C

T

J

(1)

510mA

Thermal shutdown temperature 165 ° C

Output DMOS transistors

= 25 °C 1.47 1.69 Ω

T

R

DS(on)

I

DSS

High-side + low-side switch ON
resistance

Leakage current

J

T

=125 ° C

J

EN = Low; OUT = V

(1)

2.35 2.7 Ω

S

2mA

EN = Low; OUT = GND -0.3 mA

Source drain diodes

V

SD

t

rr

t

fr

Forward ON voltage ISD = 1.4 A, EN = LOW 1.15 1.3 V

Reverse recovery time If = 1.4 A 300 ns

Forward recovery time 200 ns

Logic input

V

V

I

I

V

th(ON)

V

th(OFF)

V

th(HYS)

IL

IH

IL

IH

Low level logic input voltage -0.3 0.8 V

High level logic input voltage 2 7 V

Low level logic input current GND logic input voltage -10 µA

High level logic input current 7 V logic input voltage 10 µA

Turn-on input threshold 1.8 2.0 V

Turn-off input threshold 0.8 1.3 V

Input threshold hysteresis 0.25 0.5 V

Switching characteristics

t

D(on)EN

t

D(on)IN

t

RISE

t

D(off)EN

t

D(off)IN

t

FAL L

t

dt

f

CP

Enable to out turn ON delay time

Input to out turn ON delay time

Output rise time

Enable to out turn OFF delay time

Input to out turn OFF delay time I

Output fall time

Dead time protection 0.5 1 µs

Charge pump frequency

(2)

(2)

(2)

I

=1.4 A, resistive load 500 800 ns

LOAD

I

=1.4 A, resistive load

LOAD

(dead time included)

I

LOAD

(2)

I

LOAD

LOAD

I

LOAD

=1.4 A, resistive load 40 250 ns

=1.4 A, resistive load 500 800 1000 ns

=1.4 A, resistive load 500 800 1000 ns

=1.4 A, resistive load 40 250 ns

1.9 µs

-25 °C < TJ < 125 °C 0.6 1 MHz

7/27

Electrical characteristics L6227Q

Table 5. Electrical characteristics (continued) (TA = 25 °C, Vs = 48 V, unless otherwise specified)

Symbol Parameter Test condition Min Typ Max Unit

PWM comparator and monostable

I

RCA, IRCB

V

offset

t

PROP

t

BLANK

t

ON(MIN)

t

OFF

I

BIAS

Source current at pins RCA and RC

Offset voltage on sense comparator V

Turn OFF propagation delay

(3)

Internal blanking time on SENSE pins 1 µs

Minimum on time 2.5 3 µs

PWM recirculation time

Input bias current at pins VREFA and
VREFB

V

B

= V

RCA

REFA, VREFB

R

= 20 kΩ; C

OFF

= 100 kΩ; C

R

OFF

= 2.5 V 3.5 5.5 mA

RCB

= 0.5 V ±5 mV

= 1 nF 13 µs

OFF

= 1 nF 61 µs

OFF

Over current protection

I

SOVER

R

OPDR

t

OCD(ON)

t

OCD(OFF)

1. Tested at 25 °C in a restricted range and guaranteed by characterization.

2. See Figure 3 on page 9

3. Measured applying a voltage of 1 V to pin SENSE and a voltage drop from 2 V to 0 V to pin VREF.

4. See Figure 4 on page 9

Input supply overcurrent protection
threshold

Open drain ON resistance I = 4 mA 40 60 Ω

OCD turn-on delay time

OCD turn-off delay time

(4)

(4)

= -25 °C to 125 °C

T

J

I = 4 mA; CEN < 100 pF 200 ns

I = 4 mA; CEN < 100 pF 100 ns

(1)

500 ns

10 µA

2.8 A

8/27

L6227Q Electrical characteristics

Figure 3. Switching characteristic definition

EN

V

th(ON)

V

th(OFF)

t

I

OUT

90%

10%

D01IN1316

t

D(OFF)EN

t

FALL

t

D(ON)EN

t

t

RISE

Figure 4. Overcurrent detection timing definition

I

OUT

I

SOVER

ON

BRIDGE

OFF

V

EN

90%

10%

t

OCD(ON)

t

OCD(OFF)

D02IN1399

9/27

Circuit description L6227Q

8

4 Circuit description

4.1 Power stages and charge pump

The L6227Q integrates two independent power MOS Full Bridges. Each power MOS has an
R
conduction protection is achieved using a dead time (td = 1 µs typical) between the switch
off and switch on of two power MOS in one leg of a bridge.

Using N-channel power MOS for the upper transistors in the bridge requires a gate drive
voltage above the power supply voltage. The bootstrapped (VBOOT) supply is obtained
through an internal oscillator and few external components to realize a charge pump circuit
as shown in Figure 5. The oscillator output (VCP) is a square wave at 600 kHz (typical) with
10 V amplitude. Recommended values/part numbers for the charge pump circuit are shown
in Table 6.

Table 6. Charge pump external components values

= 0.73 Ω (typical value @ 25 °C), with intrinsic fast freewheeling diode. Cross

DS(on)

Component Value

C

BOOT

C

P

D1 1N4148

D2 1N4148

220 nF

10 nF

Figure 5. Charge pump circuit

D1

D2

C

P

VCP VBOOT VS

C

BOOT

VS

A

B

V

S

D01IN132

10/27

L6227Q Circuit description

0

4.2 Logic inputs

Pins IN1A, IN2B, IN1B and IN2B are TTL/CMOS and microcontroller compatible logic inputs.
The internal structure is shown in Figure 6. Typical value for turn-on and turn-off thresholds
are respectively Vthon = 1.8 V and Vthoff = 1.3 V.

Pins EN

and ENB have identical input structure with the exception that the drains of the

A

Overcurrent and thermal protection MOSFETs (one for the bridge A and one for the
bridge B) are also connected to these pins. Due to these connections some care needs to
be taken in driving these pins. The EN

and ENB inputs may be driven in one of two

A

configurations as shown in Figure 7 or Figure 8. If driven by an open drain (collector)
structure, a pull-up resistor R
the driver is a standard push-pull structure the resistor R
connected as shown in Figure 8. The resistor R

2.2 kΩ to 180 kΩ. Recommended values for R

and a capacitor CEN are connected as shown in Figure 7. If

EN

should be chosen in the range from

EN

and CEN are respectively 100 kΩ and 5.6 nF.

EN

and the capacitor CEN are

EN

More information on selecting the values is found in the overcurrent protection section.

Figure 6. Logic inputs internal structure

5V

ESD

PROTECTION

D01IN1329

Figure 7. EN

and ENB pins open collector driving

A

COLLECTOR

Figure 8. EN

5V

R

EN

OPEN

OUTPUT

and ENB pins push-pull driving

A

PUSH-PULL

OUTPUT

EN

C

EN

R

EN

EN

C

EN

ESD

PROTECTION

PROTECTION

11/27

5V

D01IN133

5V

ESD

D01IN1331

Circuit description L6227Q

4.3 Truth table

Table 7. Truth table

Inputs Outputs

EN IN1 IN2 OUT1 OUT2

LX

H L L GND GND Brake mode (lower path)

H H L Vs GND (Vs) Forward

H L H GND (Vs)

H H H Vs Vs Brake mode (upper path)

1. Valid only in case of load connected between OUT1 and OUT2

2. X = don't care

3. High Z = high impedance output

4. GND (Vs) = GND during Ton, Vs during Toff

(2)

X High Z

4.4 PWM current control

The L6227Q includes a constant off time PWM current controller for each of the two bridges.
The current control circuit senses the bridge current by sensing the voltage drop across an
external sense resistor connected between the source of the two lower power MOS
transistors and ground, as shown in Figure 9. As the current in the load builds up the voltage
across the sense resistor increases proportionally. When the voltage drop across the sense
resistor becomes greater than the voltage at the reference input (VREF
sense comparator triggers the monostable switching the low-side MOS off. The low-side
MOS remain off for the time set by the monostable and the motor current recirculates in the
upper path. When the monostable times out the bridge will again turn on. Since the internal
dead time, used to prevent cross conduction in the bridge, delays the turn on of the power
MOS, the effective off time is the sum of the monostable time plus the dead time.

(3)

(4)

High Z Disable

Vs Reverse

Description

or VREFB) the

A

(1)

Figure 9. PWM current controller simplified schematic

12/27

L6227Q Circuit description

Figure 10 shows the typical operating waveforms of the output current, the voltage drop

across the sensing resistor, the RC pin voltage and the status of the bridge. Immediately
after the low-side power MOS turns on, a high peak current flows through the sensing
resistor due to the reverse recovery of the freewheeling diodes. The L6227Q provides a 1 µs
blanking time t

that inhibits the comparator output so that this current spike cannot

BLANK

prematurely re-trigger the monostable.

Figure 10. Output current regulation waveforms

I

OUT

V

REF

R

SENSE

t

OFF

V

SENSE

V

REF

0

V

RC

5V

2.5V

ON

SYNCHRONOUS OR QUASI
SYNCHRONOUS RECTIFICATION

OFF

D01IN1334

1µs t

Slow Decay Slow Decay

Fast Decay

t

RCRISE

t

RCFALL

1µs t

BC

Figure 11 shows the magnitude of the off time t

approximately calculated from the equations:

t

RCFALL

t

OFF

= 0.6 · R

= t

RCFALL

OFF

· C

OFF

+ tDT = 0.6 · R

OFF

· C

OFF

+ t

BLANK

DT

OFF

DT

t

ON

DDA

versus C

t

OFF

1µs t

BLANK

Fast Decay

t

RCRISE

t

RCFALL

1µs t

BC

and R

OFF

OFF

DT

values. It can be

where R

OFF

and C

Dead Time with:

20 kΩ ≤ R

OFF

0.47 nF ≤ C

t

= 1 µs (typical value)

DT

Therefore:

t

OFF(MIN)

t

OFF(MAX)

= 6.6 µs

= 6 ms

are the external component values and tDT is the internally generated

OFF

≤ 100 kΩ

≤ 100 nF

OFF

13/27

Circuit description L6227Q

These values allow a sufficient range of t

The capacitor value chosen for C
pin R

. The rise time t

COFF

RCRISE

also affects the rise time t

OFF

will only be an issue if the capacitor is not completely
charged before the next time the monostable is triggered. Therefore, the on time t
depends by motors and supply parameters, has to be bigger than t
good current regulation by the PWM stage. Furthermore, the on time t
than the minimum on time t

tONt

> 2.5µs=

⎧
⎨
⎩

tONt

t

RCRISE

ON MIN()

TCRISEtDT

– W+>

= 600 · C

OFF

ON(MIN)

.

to implement the drive circuit for most motors.

OFF

RCRISE

of the voltage at the

for allowing a

RCRISE

can not be smaller

ON

ON

, which

Figure 12 on page 15 shows the lower limit for the on time tON for having a good PWM

current regulation capacity. It has to be said that t
the device imposes this condition, but it can be smaller than t
the device continues to work but the off time t

So, small C

value gives more flexibility for the applications (allows smaller on time and,

OFF

therefore, higher switching frequency), but, the smaller is the value for C

is always bigger than t

ON

is not more constant.

OFF

RCRISE

ON(MIN)

because

- tDT. In this last case

, the more

OFF

influential will be the noises on the circuit performance.

Figure 11. t

versus C

OFF

OFF

and R

OFF

4

1.10

= 100k

R

off

3

1.10

= 20k

R

off

s]

µ

100

toff [

10

1

0.1 1 10 100

R

Ω

= 47k

off

Coff [nF]

Ω

Ω

14/27

L6227Q Circuit description

Figure 12. Area where tON can vary maintaining the PWM regulation

100

s]

µ

10

ton(min) [

1.5µs (typ. value)

1

0.1 1 10 100
Coff [nF]

4.5 Slow decay mode

Figure 13 shows the operation of the bridge in the slow decay mode. At the start of the off

time, the lower power MOS is switched off and the current recirculates around the upper half
of the bridge. Since the voltage across the coil is low, the current decays slowly. After the
dead time the upper power MOS is operated in the synchronous rectification mode. When
the monostable times out, the lower power MOS is turned on again after some delay set by
the dead time to prevent cross conduction.

Figure 13. Slow decay mode output stage configurations

15/27

Circuit description L6227Q

4.6 Non-dissipative overcurrent protection

The L6227Q integrates an overcurrent detection circuit (OCD). This circuit provides
protection against a short circuit to ground or between two phases of the bridge. With this
internal over current detection, the external current sense resistor normally used and its
associated power dissipation are eliminated. Figure 14 shows a simplified schematic of the
overcurrent detection circuit.

To implement the over current detection, a sensing element that delivers a small but precise
fraction of the output current is implemented with each high side power MOS. Since this
current is a small fraction of the output current there is very little additional power
dissipation. This current is compared with an internal reference current I
output current in one bridge reaches the detection threshold (typically 2.8 A) the relative
OCD comparator signals a fault condition. When a fault condition is detected, the EN pin is
pulled below the turn off threshold (1.3 V typical) by an internal open drain MOS with a pull
down capability of 4 mA. By using an external R-C on the EN pin, the off time before
recovering normal operation can be easily programmed by means of the accurate
thresholds of the logic inputs.

Figure 14. Overcurrent protection simplified schematic

OUT2

VS

OUT1

POWER SENSE

1 cell

A

A

A

. When the

REF

HIGH SIDE DMOSs OF

THE BRIDGE A

I

1A I2A

POWER SENSE

D01IN1337

DISABLE

1 cell

before

+

POWER DMOS

n cells

I

/ n

2A

µC or LOGIC

V

DD

.EN

R

EN

.

C

EN

TO GATE

R

DS(ON)

40Ω TYP.

LOGIC

INTERNAL

OPEN-DRAIN

POWER DMOS

OCD

COMPARATOR

OCD

COMPARATOR

n cells

I

/ n

1A

(I1A+I2A) / n

I

REF

OVER TEMPERATURE

FROM THE

BRIDGE B

Figure 15 shows the overcurrent detection operation. The disable time t

recovering normal operation can be easily programmed by means of the accurate
thresholds of the logic inputs. It is affected whether by C
magnitude is reported in Figure 16. The delay time t

DELAY

an overcurrent has been detected depends only by C

and REN values and its

EN

before turning off the bridge when

value. Its magnitude is reported in

EN

Figure 17.

C

is also used for providing immunity to pin EN against fast transient noises. Therefore

EN

the value of C
delay time and the R

The resistor R
values for R

should be chosen as big as possible according to the maximum tolerable

EN

EN

and CEN are respectively 100 kΩ and 5.6 nF that allow obtaining 200 µs

EN

value should be chosen according to the desired disable time.

EN

should be chosen in the range from 2.2 kΩ to 180 kΩ. Recommended

disable time.

16/27

L6227Q Circuit description

Figure 15. Overcurrent protection waveforms

I

OUT

I

SOVER

V

EN

V

DD

V

th(ON)

V

th(OFF)

ON

OCD

OFF

V

EN(LOW)

BRIDGE

Figure 16. t

[µs]

[µs]

t

t

ON

OFF

DISABLE

3

3

1.10

1.10

100

100

DISABLE

DISABLE

10

10

t

DELAY

t

OCD(ON)

t

EN(FALL)

versus CEN and R

REN= 220 k

REN= 220 k

t

D(OFF)EN

t

OCD(OFF)

EN (VDD

Ω

Ω

t

DISABLE

t

EN(RISE)

= 5 V)

REN= 100 k

REN= 100 k

Ω

Ω

t

D(ON)EN

R

R

EN

EN

R

R

EN

EN

R

R

EN

EN

D02IN1400

= 47 k

= 47 k
= 33 k

= 33 k

= 10 k

= 10 k

Ω

Ω
Ω

Ω

Ω

Ω

1

1

1 10 100

1 10 100

CEN[nF ]

CEN[nF ]

17/27

Circuit description L6227Q

Figure 17. t

DELAY

tdelay [µs]

versus C

10

1

0.1
110100

4.7 Thermal protection

EN (VDD

= 5 V)

Cen [nF]

In addition to the ovecurrent protection, the L6227Q integrates a thermal protection for
preventing the device destruction in case of junction over temperature. It works sensing the
die temperature by means of a sensible element integrated in the die. The device switch-off
when the junction temperature reaches 165 °C (typ. value) with 15 °C hysteresis (typ.
value).

18/27

L6227Q Application information

5 Application information

A typical application using L6227Q is shown in Figure 18. Typical component values for the
application are shown in Table 8. A high quality ceramic capacitor in the range of 100 to
200 nF should be placed between the power pins (VS
L6227Q to improve the high frequency filtering on the power supply and reduce high
frequency transients generated by the switching. The capacitors connected from the EN
and EN

inputs to ground set the shut down time for the bridge A and bridge B respectively

B

when an over current is detected (see overcurrent protection). The two current sensing
inputs (SENSE

and SENSEB) should be connected to the sensing resistors with a trace

A

length as short as possible in the layout. The sense resistors should be non-inductive
resistors to minimize the dI/dt transients across the resistor. To increase noise immunity,
unused logic pins (except EN

and ENB) are best connected to 5 V (high logic level) or GND

A

(low logic level) (see pin description). It is recommended to keep power ground and signal
ground separated on PCB.

Table 8. Component values for typical application

Component Value

and VSB) and ground near the

A

A

C

C

C

C

C

BOOT

C

C

ENA

C

ENB

C

REFA

C

REFB

D

D

R

R

R

ENA

R

ENB

R

SENSEA

R

SENSEB

1

2

A

B

100 µF

100 nF

1 nF

1 nF

220 nF

P

10 nF

5.6 nF

5.6 nF

68 nF

68 nF

1

2

A

B

1N4148

1N4148

39 kΩ

39 kΩ

100 kΩ

100 kΩ

0.6 Ω

0.6 Ω

19/27

Application information L6227Q

Figure 18. Typical application

Note: To reduce the IC thermal resistance, therefore improve the dissipation path, the NC pins can

be connected to GND.

20/27

L6227Q Output current capability and IC power dissipation

6 Output current capability and IC power dissipation

In Figure 19 and Figure 20 are shown the approximate relation between the output current
and the IC power dissipation using PWM current control driving two loads, for two different
driving types:

– One full bridge ON at a time (Figure 19) in which only one load at a time is

energized.

– Two full bridges ON at the same time (Figure 20) in which two loads at the same

time are energized.

For a given output current and driving type the power dissipated by the IC can be easily
evaluated, in order to establish which package should be used and how large must be the
on-board copper dissipating area to guarantee a safe operating junction temperature
(125 °C maximum).

Figure 19. IC power dissipation vs output current with one full bridge ON at a time

ONE FULL BRIDGE ON AT A TIME

PD [W]

10

8

6

4

2

0

0 0.25 0.5 0.75 1 1.25 1.5

[A]

I

OUT

I

A

I

B

I

OUT

I

OUT

Test Conditions:
Supply Voltage = 24V

No PWM

f

= 30 kHz (slow decay)

SW

Figure 20. IC power dissipation versus output current with two full bridges ON at the

same time

TWO FULL BRIDGES ON AT THE SAME TIME

10

8

6

PD [W]

4

2

0

0 0.25 0.5 0.75 1 1.25 1.5

[A]

I

OUT

I

A

I

B

I

OUT

I

OUT

Test Conditions:
Supply Voltage = 24 V

No PWM

= 30 kHz (slow decay)

f

SW

21/27

Thermal management L6227Q

7 Thermal management

In most applications the power dissipation in the IC is the main factor that sets the maximum
current that can be delivered by the device in a safe operating condition. Therefore, it has to
be taken into account very carefully. Besides the available space on the PCB, the right
package should be chosen considering the power dissipation. Heat sinking can be achieved
using copper on the PCB with proper area and thickness. For instance, using a VFQFPN32L
5x5 package the typical Rth(JA) is about 42 °C/W when mounted on a double-layer FR4
PCB with a dissipating copper surface of 0.5 cm
connected through 18 via holes (9 below the IC).

2

on the top side plus 6 cm2 ground layer

22/27

L6227Q Package mechanical data

8 Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.

Table 9. VFQFPN32 5x5x1.0 pitch 0.50

Databook (mm)

Dim.

Min Typ Max

A 0.80 0.85 0.95

b 0.18 0.25 0.30

b1 0.165 0.175 0.185

D 4.85 5.00 5.15

D2 3.00 3.10 3.20

D3 1.10 1.20 1.30

E 4.85 5.00 5.15

E2 4.20 4.30 4.40

E3 0.60 0.70 0.80

e0.50

L 0.30 0.40 0.50

ddd 0.08

Note: 1 VFQFPN stands for thermally enhanced very thin profile fine pitch quad flat package no

lead. Very thin profile: 0.80 < A = 1.00 mm.

2 Details of terminal 1 are optional but must be located on the top surface of the package by

using either a mold or marked features.

23/27

Package mechanical data L6227Q

Figure 21. Package dimensions

24/27

L6227Q Order codes

9 Order codes

Table 10. Order code

Order code Package Packaging

L6227Q VFQFPN32 5 x 5 x 1.0 mm Tube

25/27

Revision history L6227Q

10 Revision history

Table 11. Document revision history

Date Revision Changes

07-Dec-2007 1 First release

10-Jun-2008 2

28-Jan-2009 3 Updated value in Table 3: Thermal data on page 4

Updated: Figure 18 on page 20
Added: Note 1 on page 4

26/27

L6227Q

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