Datasheet L6206Q Datasheet (ST)

Features

■ Operating supply voltage from 8 to 52 V

■ 5.6 A output peak current

■ R

0.3 Ω typ. value @ TJ = 25 °C

DS(on)

■ Operating frequency up to 100 kHz

■ Programmable high side overcurrent detection

and protection

■ Diagnostic output

■ Paralleled operation

■ Cross conduction protection

■ Thermal shutdown

■ Undervoltage lockout

■ Integrated fast free wheeling diodes

Application

■ Bipolar stepper motor

■ Dual or quad DC motor

Figure 1. Block diagram

L6206Q

DMOS dual full bridge driver

QFN-48

(7 x 7 mm)

Description

The L6206Q is a DMOS dual full bridge designed for motor control applications, developed using BCDmultipower technology, which combines isolated DMOS power transistors with CMOS and bipolar circuits on the same chip. Available in QFN48 7x7 package, the L6206Q features thermal shutdown and a non-dissipative overcurrent detection on the high side power MOSFETs plus a diagnostic output that can be easily used to implement the overcurrent protection.

VBOOT

VCP

PROGCL

OCD

EN

IN1

IN2

OCD

PROGCL

EN

IN1

IN2

A

B

V

BOOT

CHARGE

PUMP

VOLTAGE

REGULATOR

OCD

THERMAL

PROTECTION

OCD

10V

5V

VS

V

BOOT

OVER

A

B

CURRENT

DETECTION

GATE

LOGIC

OVER

CURRENT

DETECTION

GATE

LOGIC

V

BOOT

V01V01

BRIDGE A

BRIDGE B

A

OUT1

OUT2

SENSE

V

S

B

OUT1

OUT2

SENSE

A

B

AM02555v1

November 2011 Doc ID 022028 Rev 1 1/30

www.st.com

30

Contents L6206Q

Contents

1 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.2 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

4 Circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4.1 Power stages and charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4.2 Logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4.3 Non-dissipative overcurrent detection and protection . . . . . . . . . . . . . . . 11

4.4 Thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6 Paralleled operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

7 Output current capability and IC power dissipation . . . . . . . . . . . . . . 22

8 Thermal management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

9 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

10 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

11 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

2/30 Doc ID 022028 Rev 1

L6206Q Electrical data

1 Electrical data

1.1 Absolute maximum ratings

Table 1. Absolute maximum ratings

Symbol Parameter Parameter Value Unit

V

Supply voltage VSA = VSB = VS 60 V

S

V

OD

OCD

OCDB

Differential voltage between VSA, OUT1A, OUT2A, SENSEA and VSB,

, OUT2B, SENSE

OUT1

B

,

A

OCD pins voltage range -0.3 to +10 V

B

VSA = VSB = VS = 60V; VSENSEA = VSENSEB = GND

60 V

PROGCL

PROGCLB

V

SENSEA

V

SENSEB

I

S(peak)

,

A

PROGCL pins voltage range -0.3 to +7 V

BOOT

IN,VEN

Bootstrap peak voltage VSA = VSB = VS V

Input and enable voltage range -0.3 to +7 V

,

Voltage range at pins SENSEA and SENSE

Pulsed supply current (for each VS pin), internally limited by the overcurrent protection

B

= VSB = VS;

V

SA

t

PULSE

IS RMS supply current (for each VS pin) VSA = VSB = VS 2.5 A

T

, TOP

stg

Storage and operating temperature range

1.2 Recommended operating conditions

Table 2. Recommended operating conditions

Symbol Parameter Parameter Min. Max. Unit

Supply voltage VSA = VSB = VS 8 52 V

V

S

Differential voltage between VSA,

V

OUT1A, OUT2A, SENSEA and VSB,

OD

OUT1B, OUT2B, SENSEB

= VSB = VS;

VS

A

V

SENSEA

< 1ms

= V

SENSEB

+ 10 V

S

-1 to +4 V

7.1 A

-40 to 150 °C

52 V

,

V

SENSEA

V

SENSEB

I

OUT

T

f

sw

Voltage range at pins SENSEA and SENSEB

RMS output current 2.5 A

Operating junction temperature -25 +125 °C

j

Switching frequency 100 kHz

Pulsed t

DC -1 1 V

< t

W

rr

-6 6 V

Doc ID 022028 Rev 1 3/30

Pin connection L6206Q

2 Pin connection

Figure 2. Pin connection (top view)

OUT1A

GND

OUT1B

NC

SENSEA

OCDA

48 47 46 45 44 43 42 41 40 39 38 37

1

NC

EPAD

2

3

4

NC

5

NC

6

7

NC

8

NC

9

NC

10

11

12

NC

13 14 15 16 17 18 19 20 21 22 23 24

NC

OCDB

SENSEB

SENSEA

SENSEB

IN2A

IN1B

IN1A

IN2B

Note: The exposed PAD must be connected to GND pin.

Table 3. Pin description

ENA

PROGCLA

ENB

PROGCLB

VCPNCOUT2A

OUT2A

OUT2B

VBOOT

36

NC

35

VSA

34

VSA

33

NC

32

NC

31

GND

30

NC

29

NC

28

NC

27

VSB

26

VSB

25

NC

AM02556v1

Pin Name Type Function

43 IN1A Logic input Bridge A logic input 1.

44 IN2A Logic input Bridge A logic input 2.

45, 46 SENSEA Power supply

Bridge A source pin. This pin must be connected to power ground directly or through a sensing power resistor.

Bridge A overcurrent detection and thermal protection pin. An internal

48 OCDA Open-drain output

open-drain transistor pulls to GND when overcurrent on bridge A is detected or in case of thermal protection.

2, 3 OUT1A Power output Bridge A output 1.

6, 31 GND GND

Signal ground terminals. These pins are also used for heat dissipation toward the PCB.

10, 11 OUT1B Power output Bridge B output 1.

Bridge B overcurrent detection and thermal protection pin. An internal

13 OCDB Open-drain output

open-drain transistor pulls to GND when overcurrent on bridge B is detected or in case of thermal protection.

15, 16 SENSEB Power supply

Bridge B source pin. This pin must be connected to power ground directly or through a sensing power resistor.

4/30 Doc ID 022028 Rev 1

L6206Q Pin connection

Table 3. Pin description (continued)

Pin Name Type Function

17 IN1B Logic input Bridge B input 1

18 IN2B Logic input Bridge B input 2

Bridge B overcurrent level programming. A resistor connected between

19 PROGCLB R pin

20 ENB Logic input

21 VBOOT Supply voltage

22, 23 OUT2B Power output Bridge B output 2.

26, 27 VSB Power supply

this pin and ground sets the programmable current limiting value for bridge B. By connecting this pin to ground the maximum current is set. This pin cannot be left unconnected.

Bridge B enable. LOW logic level switches OFF all power MOSFETs of bridge B. If not used, it must be connected to +5 V.

Bootstrap voltage needed for driving the upper power MOSFETs of both bridge A and bridge B.

Bridge B power supply voltage. It must be connected to the supply voltage together with pin VSA.

34, 35 VSA Power supply

38, 39 OUT2A Power output Bridge A output 2.

40 VCP Output Charge pump oscillator output.

41 ENA Logic input

42 PROGCLA R pin

Bridge A power supply voltage. It must be connected to the supply voltage together with pin VSB.

Bridge A enable. LOW logic level switches OFF all power MOSFETs of bridge A. If not used, it must be connected to +5 V.

Bridge A overcurrent level programming. A resistor connected between this pin and ground sets the programmable current limiting value for bridge A. By connecting this pin to ground, the maximum current is set. This pin cannot be left unconnected.

Doc ID 022028 Rev 1 5/30

Electrical characteristics L6206Q

3 Electrical characteristics

VS = 48 V, TA = 25 °C, unless otherwise specified.

Table 4. Electrical characteristics

Symbol Parameter Test condition Min. Typ. Max. Unit

V

Sth(ON)

V

Sth(OFF)

IS Quiescent supply current

T

j(OFF)

Turn-on threshold 6.6 7 7.4 V

Turn-off threshold 5.6 6 6.4 V

All bridges OFF; Tj = -25 °C to 125 °C

(1)

510mA

Thermal shutdown temperature 165 °C

Output DMOS transistors

Tj = 25 °C 0.34 0.4

R

DS(ON)

I

DSS

High-side switch ON resistance

Tj =125 °C

Tj = 25 °C 0.28 0.34

Low-side switch ON resistance

Tj =125 °C

EN = Low; OUT = V

Leakage current

EN = Low; OUT = GND -0.15 mA

(1)

0.53 0.59

0.47 0.53

2mA

S

Source drain diodes

V

Forward ON voltage ISD = 2.5 A, EN = LOW 1.15 1.3 V

SD

t

rr

t

fr

Reverse recovery time If = 2.5 A 300 ns

Forward recovery time 200 ns

Logic input

Ω

V

I

V

th(ON)

V

th(OFF)

V

th(HYS)

IH

IL

IH

Low level logic input voltage -0.3 0.8 V

IL

High level logic input voltage 2 7 V

Low level logic input current GND logic input voltage -10 µA

High level logic input current 7 V logic input voltage 10 µA

Turn-on input threshold 1.8 2 V

Turn-off input threshold 0.8 1.3 V

Input threshold hysteresis 0.25 0.5 V

Switching characteristics

t

D(on)EN

t

D(on)IN

t

RISE

Enable pin to out, turn ON delay time

(2)

Input pin to out, turn ON delay time

Output rise time

(2)

=2.5 A, resistive load 100 250 400 ns

I

LOAD

=2.5 A, resistive load (dead

I

LOAD

time included)

I

=2.5 A, resistive load 40 250 ns

LOAD

6/30 Doc ID 022028 Rev 1

1.6 µs

L6206Q Electrical characteristics

Table 4. Electrical characteristics (continued)

Symbol Parameter Test condition Min. Typ. Max. Unit

t

D(off)EN

t

D(off)IN

t

FAL L

t

dt

f

CP

Enable pin to out, turn OFF delay

(2)

time

Input pin to out, turn OFF delay time I

Output fall time

(2)

I

=2.5 A, resistive load 300 550 800 ns

LOAD

=2.5 A, resistive load 600 ns

LOAD

=2.5 A, resistive load 40 250 ns

LOAD

Dead time protection 0.5 1 µs

Charge pump frequency -25 °C<Tj <125 °C 0.6 1 MHz

Overcurrent detection

I

s over

Input supply overcurrent detection threshold

-25 °C<Tj <125 °C; RCL= 39 kΩ

-25 °C<Tj <125 °C; RCL= 5 kΩ

-25 °C<Tj <125 °C; RCL= GND

0.57

4.42

5.6

ROPDR Open-drain ON resistance I = 4 mA 40 60 Ω

t

OCD(ON)

t

OCD(OFF)

1. Tested at 25 °C in a restricted range and guaranteed by characterization.

2. See Figure 3.

3. See Figure 4.

OCD turn-on delay time

OCD turn-off delay time

(3)

I = 4 mA; CEN < 100 pF 200 ns

(3)

I = 4 mA; CEN < 100 pF 100 ns

Figure 3. Switching characteristic definition

EN

A A A

V

th(OFF)

I

th(ON)

OUT

90%

10%

D01IN1316

t

D(OFF)EN

t

FAL L

t

D(ON)EN

t

RISE

t

AM02557v1

Doc ID 022028 Rev 1 7/30

Electrical characteristics L6206Q

Figure 4. Overcurrent detection timing definition

I

OUT

OCD

Threshold

t

V

OCD

90%

10%

t

OCD(ON)

t

OCD(OFF)

AM02558v1

8/30 Doc ID 022028 Rev 1

L6206Q Circuit description

4 Circuit description

4.1 Power stages and charge pump

The L6206Q integrates two independent Power MOS full bridges. Each power MOS has an R conduction protection is implemented by using a dead time (t an internal timing circuit between the turn-off and turn-on of two power MOSFETs in one leg of a bridge.

= 0.3 Ω (typical value @ 25 °C) with intrinsic fast freewheeling diode. Cross

DS(ON)

= 1 µs typical value) set by

DT

Pins VS

and VSB must be connected together to the supply voltage (VS).

A

Using an N-channel power MOSFET for the upper transistors in the bridge requires a gate drive voltage above the power supply voltage. The bootstrapped supply (V

) is obtained

BOOT

through an internal oscillator and few external components to realize a charge pump circuit, as shown in Figure 5. The oscillator output (pin VCP) is a square wave at 600 kHz (typically) with 10 V amplitude. Recommended values/part numbers for the charge pump circuit are shown in Ta bl e 5 .

Table 5. Charge pump external component values

Component Value

C

BOOT

C

P

R

P

220 nF

10 nF

100 Ω

D1 1N4148

D2 1N4148

Figure 5. Charge pump circuit

V

S

D1

R

C

VCP VBOOT VS

C

D2

P

BOOT

VS

A

B

AM02559v1

4.2 Logic inputs

Pins IN1A, IN2A, IN1B, IN2B, ENA, and ENB are TTL/CMOS and µC compatible logic inputs. The internal structure is shown in Figure 6. The typical values for turn-on and turn-off thresholds are respectively V

Pins EN connecting them respectively to the outputs OCD outputs. If this type of connection is chosen, particular care needs to be taken in driving these pins. Two configurations are shown in Figure 7 and Figure 8. If driven by an open- drain (collector) structure, a pull-up resistor R

and ENB are commonly used to implement overcurrent and thermal protection by

A

=1.8 V and V

thon

= 1.3 V.

thoff

and OCDB, which are open-drain

A

and a capacitor CEN are connected as

EN

Doc ID 022028 Rev 1 9/30

Circuit description L6206Q

shown in Figure 7. If the driver is a standard push-pull structure the resistor REN and the capacitor C the range from 2.2 kΩ to 180 kΩ. Recommended values for R

are connected as shown in Figure 8. The resistor REN should be chosen in

EN

and CEN are respectively

EN

100 kΩ and 5.6 nF. More information on selecting the values can be found in 4.3: Non-

dissipative overcurrent detection and protection.

Figure 6. Logic inputs internal structure

5V

ESD

PROTECTION

AM02560v1

Figure 7. EN

Figure 8. EN

and ENB pins open collector driving

A

OCDA or OCD

5V

R

EN

OPEN

COLLECTOR

OUTPUT

and ENB pins push-pull driving

A

R

PUSH-PULL

OUTPUT

EN

C

EN

C

EN

OCDA or OCD

ENA or EN

B

5V

AM02561v1

5V

AM02562v1

10/30 Doc ID 022028 Rev 1

L6206Q Circuit description

Table 6. Truth table

Inputs Outputs

EN IN1 IN2 OUT1 OUT2

L X X High Z High Z

H L L GND GND

H H L Vs GND

H L H GND Vs

H H H Vs Vs

X = Do not care

High Z = High impedance output

4.3 Non-dissipative overcurrent detection and protection

The L6206Q integrates an overcurrent detection circuit (OCD). With this internal overcurrent detection, the external current sense resistor normally used and its associated power dissipation are eliminated. Figure 9 shows a simplified schematic of the overcurrent detection circuit for bridge A. Bridge B is provided with an analogous circuit.

To implement the overcurrent detection, a sensing element that delivers a small but precise fraction of the output current is implemented with each high side power MOSFET. Since this current is a small fraction of the output current there is very little additional power dissipation. This current is compared with an internal reference current I output current reaches the detection threshold I

, the OCD comparator signals a fault

sover

REF. When the

condition. When a fault condition is detected, an internal open-drain MOSFET with a pulldown capability of 4 mA connected to the OCD pin is turned on. Figure 10 shows the OCD operation.

This signal can be used to regulate the output current simply by connecting the OCD pin to the EN pin and adding an external R-C, as shown in Figure 9. The off-time before recovering normal operation can be easily programmed by means of the accurate thresholds of the logic inputs.

I

REF and, therefore, the output current detection threshold, are selectable by the RCL value,

following the equations:

● I

Figure 11 shows the output current protection threshold versus R

= 5.6 A ±30% at -25 °C < Tj < 125 °C if RCL = 0 Ω (PROGCL connected to GND)

sover

22100

----------------

= ±10% at -25 °C < Tj < 125 °C if 5 kΩ < RCL < 40 kΩ

R

CL

value in the range 5 kΩ

CL

to 40 kΩ.

The disable time (t

DISABLE

by means of the accurate thresholds of the logic inputs. It is affected either by C values and its magnitude is reported in Figure 12. The delay time (t the bridge when an overcurrent has been detected, depends only on the C

), before recovering normal operation, can be easily programmed

or REN

), before turning off

DELAY

EN

value. Its

EN

magnitude is reported in Figure 13.

Doc ID 022028 Rev 1 11/30

Circuit description L6206Q

CEN is also used for providing immunity to pin EN against fast transient noises. Therefore the value of C delay time and the R

The resistor R values for R

should be chosen as big as possible according to the maximum tolerable

EN

and CEN are respectively 100 kΩ and 5.6 nF which allow a 200 µs disable

EN

value should be chosen according to the desired disable time.

EN

should be chosen in the range from 2.2 kΩ to 180 kΩ. Recommended

time to be obtained.

Figure 9. Overcurrent protection simplified schematic

μC or LOGIC

+5V

OUT1

POWER SENSE

1 cell

POWER DMOS

OCD

OVER

n cells

PROGCL

I1A/ n

A,

TO GATE

LOGIC

R

ENA

C

ENA

EN

OCD

A

R

DS(ON)

40Ω TYP.

OPEN-DRAIN

COMPARATOR

INTERNAL

TEMPERATURE

VS

A

I1AI

+

(I1A+I2A) / n

I

REF

I

REF

R

CLA

A

2A

.

OUT2

A

POWER DMOS

I2A/ n

-

+

HIGH SIDE DMOSs OF

THE BRIDGE A

POWER SENSE

n cells

1.2V

1 cell

AM02563v1

12/30 Doc ID 022028 Rev 1

L6206Q Circuit description

Figure 10. Overcurrent protection waveforms

I

OUT

I

SOVER

V

EN

V

DD

V

th(ON)

V

th(OFF)

ON

OCD

OFF

ON

BRIDGE

t

DELAY

V

EN(LOW)

t

DISABLE

OFF

t

OCD(ON)

t

EN(FALL)

t

D(OFF)EN

t

OCD(OFF)

t

EN(RISE)

Figure 11. Output current protection threshold versus RCL value

5

4.5

4

3.5

3

[A]

2.5

2

1.5

1

0.5

0

5k 10k 15k 20k 25k 30k 35k 40k

RCL [ Ω]

I

SOVER

t

D(ON)EN

AM02564v1

AM02565v1

Doc ID 022028 Rev 1 13/30

Circuit description L6206Q

Figure 12. t

3

1.10

100

[µs]

DISABLE

t

10

1

Figure 13. t

DISABLE

1 10 100

DELAY

versus CEN and REN (VDD = 5 V)

Ω

REN= 220 k

CEN[n F]

Ω

versus CEN (VDD = 5 V)

REN= 100 k

Ω

R

EN

= 47 k

= 33 k

= 10 k

Ω

10

s]

μ

1

tdelay [

0.1 110100

Cen [nF]

14/30 Doc ID 022028 Rev 1

L6206Q Circuit description

4.4 Thermal protection

In addition to overcurrent detection, the L6206Q integrates a thermal protection for preventing device destruction in the case of junction overtemperature. It works by sensing the die temperature by means of a sensitive element integrated in the die. The device switches off when the junction temperature reaches 165 °C (typ. value) with 15 °C hysteresis (typ. value).

Doc ID 022028 Rev 1 15/30

Application information L6206Q

5 Application information

A typical application using L6206Q is shown in Figure 14. Typical component values for the application are shown in Ta bl e 7. A high quality ceramic capacitor in the range of 100 to 200 nF should be placed between the power pins (VS to improve the high frequency filtering on the power supply and reduce high frequency transients generated by the switching. The capacitors connected from the EN EN

/OCDB nodes to ground set the shutdown time for bridge A and bridge B respectively

B

when an overcurrent is detected (see 4.3: Non-dissipative overcurrent detection and

protection). The two current sources (SENSE

ground with a trace length as short as possible in the layout. To increase noise immunity, unused logic pins are best connected to 5 V (high logic level) or GND (low logic level) (see

Table 3.).

It is recommended to keep power ground and signal ground separated on the PCB.

Table 7. Component values for typical application

Component Value

100 uF

C

1

C

100 nF

2

C

BOOT

10 nF

C

P

C

ENA

C

ENB

C

REF

D

1N4148

1

1N4148

D

2

5 kΩ

R

CLA

R

5 kΩ

CLB

100 kΩ

R

ENA

100 kΩ

R

ENB

R

100 Ω

P

and VSB) and ground near the L6206Q

A

/OCDA and

A

and SENSEB) should be connected to power

A

220 nF

5.6 nF

68 nF

16/30 Doc ID 022028 Rev 1

L6206Q Application information

Figure 14. Typical application

VS

8-52V

+

DC

POWER

GROUND

-

SIGNAL

GROUND

A

34, 35

VCP

C

P

VBOOT

SENSE

OUT1

OUT2

OUT1

OUT2

GND

B

26, 27

40

21

A

45, 46

B

15, 16

A

2, 3

A

38, 39

B

10, 11

B

22, 23

6, 31

C

1

C

2

D

1

R

P

BOOT

LOAD

D

2

A

B

C

48VS

41

13

20

17

18

43

44

42

19

OCD

A

EN

A

OCD

B

EN

B

IN1

B

IN2

B

IN1

A

IN2

A

PROGCL

R

ENA

C

ENA

R

ENB

C

ENB

A

R

CLA

B

R

CLB

IN1

IN2

IN1

IN2

EN

A

EN

B

A

AM02566v1

Note: To reduce the IC thermal resistance, and therefore improve the dissipation path, the NC pins

can be connected to GND.

Doc ID 022028 Rev 1 17/30

Paralleled operation L6206Q

6 Paralleled operation

The outputs of the L6206Q can be paralleled to increase the output current capability or reduce the power dissipation in the device at a given current level. It must be noted, however, that the internal wire bond connections from the die to the power or sense pins of the package must carry current in both of the associated half bridges.

When the two halves of one full bridge (for example OUT1

and OUT2A) are connected in

A

parallel, the peak current rating is not increased as the total current must still flow through one bond wire on the power supply or sense pin. In addition, the overcurrent detection senses the sum of the current in the upper devices of each bridge (A or B) so connecting the two halves of one bridge in parallel does not increase the overcurrent detection threshold.

For most applications the recommended configuration is half bridge 1 of bridge A paralleled with the half bridge 1 of bridge B, and the same for the half bridges 2, as shown in

Figure 15. The current in the two devices connected in parallel share well as the R

DS(ON)

of the devices on the same die is well matched. When connected in this configuration the overcurrent detection circuit, which senses the current in each bridge (A and B), senses the current in the upper devices connected in parallel independently and the sense circuit with the lowest threshold trips first. With the enable pins connected in parallel, the first detection of an overcurrent in either upper DMOS device turns off both bridges. Assuming that the two DMOS devices share the current equally, the resulting overcurrent detection threshold is twice the minimum threshold set by the resistors R recommended to use R

CLA

= R

CLB

.

CLA

or R

in Figure 15. It is

CLB

In this configuration the resulting bridge has the following characteristics.

● Equivalent device: full bridge

● R

● 5 A max. RMS load current

● 11.2 A max. OCD threshold

0.15 Ω typ. value @ TJ = 25 °C

DS(ON)

18/30 Doc ID 022028 Rev 1

L6206Q Paralleled operation

Figure 15. Parallel connection for higher current

VS

C

P

VBOOT

SENSE

OUT1

OUT2

OUT1

OUT2

GND

VS

VCP

A

34, 35

B

26, 27

40

21

A

45, 46

B

15, 16

A

2, 3

A

38, 39

B

10, 11

B

24, 25

6, 31

48 41

13

20

17

18

43

44

42

19

OCD

B

EN

B

OCD

A

EN

A

IN1

A

IN2

A

IN1

B

IN2

B

PROGCL

R

EN

C

EN

A

R

CLA

B

R

CLB

EN

IN1

IN2

AM02567v1

VS

8-52V

+

DC

POWER

GROUND

-

SIGNAL

GROUND

LOAD

C

1

C

2

D

1

R

P

BOOT

D

2

C

To operate the device in parallel and maintain a lower overcurrent threshold, half bridge 1 and the half bridge 2 of bridge A can be connected in parallel and the same is done for bridge B, as shown in Figure 16. In this configuration, the peak current for each half bridge is still limited by the bond wires for the supply and sense pins so the dissipation in the device is reduced, but the peak current rating is not increased.

When connected in this configuration the overcurrent detection circuit, senses the sum of the current in upper devices connected in parallel. With the enable pins connected in parallel, an overcurrent turns off both bridges.

Since the circuit senses the total current in the upper devices, the overcurrent threshold is equal to the threshold set by the resistor RCL threshold when outputs OUT1A and OUT2A are high and resistor RCL when outputs OUT1

It is recommended to use RCL

and OUT2B are high.

B

= RCLB.

A

or RCLB in Figure 16. RCLA sets the

A

sets the threshold

B

In this configuration, the resulting bridge has the following characteristics.

- Equivalent device: full bridge

- R

0.15 Ω typ. value @ TJ = 25 °C

DS(ON)

- 2.5 A max. RMS load current

- 5.6 A max. OCD threshold

Doc ID 022028 Rev 1 19/30

Paralleled operation L6206Q

Figure 16. Parallel connection with lower overcurrent threshold

VS

8-52V

+

DC

POWER

GROUND

-

SIGNAL

GROUND

LOAD

C

1

C

2

D

1

R

P

BOOT

D

2

C

VS

VCP

C

P

VBOOT

SENSE

OUT1

OUT2

OUT1

OUT2

GND

A

34, 35

B

26, 27

40

21

A

45, 46

B

15, 16

A

2, 3

A

38, 39

B

10, 11

B

24, 25

6, 31

OCD

48

41

13

20

17

18

43

44

42

19

A

EN

A

OCD

B

EN

B

IN1

A

IN2

A

IN1

B

IN2

B

PROGCL

R

EN

C

EN

A

R

CLA

B

R

CLB

EN

IN

A

IN

B

AM02568v1

It is also possible to parallel the four half bridges to obtain a simple half bridge as shown in

Figure 17. In this configuration the overcurrent threshold is equal to twice the minimum

threshold set by the resistors R R

.

CLB

CLA

or R

in Figure 17. It is recommended to use R

CLB

CLA

=

The resulting half bridge has the following characteristics.

● Equivalent device: half bridge

● R

● 5 A max. RMS load current

● 11.2 A max. OCD threshold

0.075 Ω typ. value @ TJ = 25 °C

DS(ON)

20/30 Doc ID 022028 Rev 1

L6206Q Paralleled operation

Figure 17. Paralleling the four half bridges

VS

8-52V

+

DC

POWER

GROUND

-

SIGNAL

GROUND

A

34, 35

VS

VCP

C

P

VBOOT

SENSE

OUT1

OUT2

OUT1

OUT2

GND

B

26, 27

40

21

A

45, 46

B

15, 16

A

2, 3

A

38, 39

B

10, 11

B

24, 25

6, 31

C

1

C

2

D

1

R

P

BOOT

D

2

C

LOAD

OCD

48

41

13

20

17

18

43

44

42

19

A

EN

A

OCD

B

EN

B

IN1

A

IN2

A

IN1

B

IN2

B

PROGCL

R

EN

C

EN

IN

A

R

CLA

B

R

CLB

AM02569v1

Doc ID 022028 Rev 1 21/30

Output current capability and IC power dissipation L6206Q

7 Output current capability and IC power dissipation

Figure 18 and Figure 19 show the approximate relation between the output current and the

IC power dissipation using PWM current control driving two loads, for two different driving types:

● One full bridge ON at a time (Figure 18) in which only one load at a time is energized.

● Two full bridges ON at the same time (Figure 19) in which two loads at the same time

are energized.

For a given output current and driving type the power dissipated by the IC can be easily evaluated, in order to establish which package should be used and how large the onboard copper dissipating area must be in order to guarantee a safe operating junction temperature (125 °C maximum).

Figure 18. IC power dissipation vs. output current with one full bridge on at a time

ONE FULL BRIDGE ON AT A TIME

10

I

A

I

OUT

8

6

PD [W]

4

I

B

I

OUT

Test Conditions:

2

Supply Voltage = 24V

No PWM

0

00.511.522.5 3

I

[A]

OUT

f

= 30kHz (slow decay)

SW

AM02570v1

Figure 19. IC power dissipation vs. output current with two full bridges ON at the

same time

TWO FULL BRIDGES ON AT THE SAME TIME

10

8

6

PD [W]

4

I

A

I

B

I

OUT

I

OUT

2

0

00.511.522.53

[A]

I

OUT

22/30 Doc ID 022028 Rev 1

Test Conditions: Supply Voltage = 24V

No PWM

= 30kHz (slow decay)

f

SW

AM02571v1

L6206Q Thermal management

8 Thermal management

In most applications the power dissipation in the IC is the main factor that sets the maximum current that can be delivered by the device in a safe operating condition. Therefore, it must be taken into account very carefully. Besides the available space on the PCB, the right package should be chosen considering the power dissipation. Heat sinking can be achieved using copper on the PCB with proper area and thickness.

Doc ID 022028 Rev 1 23/30

Electrical characteristics curves L6206Q

9 Electrical characteristics curves

Figure 20. Typical quiescent current vs.

Iq [m A ]

5.6

5.4

5.2

5.0

4.8

4.6 0 102030405060

supply voltage

fsw = 1kHz Tj = 25°C

[V]

V

S

Tj = 85°C

Tj = 125°C

AM02572v1

Figure 22. Normalized typical quiescent

Iq / (Iq @ 1 k Hz)

1.7

1.6

1.5

1.4

1.3

1.2

1.1

1.0

0.9

current vs. switching frequency

020406080100

f

SW

[kHz]

AM02574v1

Figure 21. Typical high-side R

DS(on)

voltage

R

[Ω]

DS(ON)

0.380

0.376

0.372

0.368

Tj = 25°C

0.364

0.360

0.356

0.352

0.348

0.344

0.340

0.336

0 5 10 15 20 25 30

[V]

V

S

Figure 23. Normalized R

vs. junction

DS(on)

temperature (typical value)

R

/ (R

DS(ON)

@ 25 °C)

Tj [°C]

DS(ON)

1.8

1.6

1.4

1.2

1.0

0.8 0 20406080100120140

vs. supply

AM02573v1

AM02575v1

24/30 Doc ID 022028 Rev 1

L6206Q Electrical characteristics curves

Figure 24. Typical low-side R

R

DS(ON)

voltage

[Ω]

DS(on)

vs. supply

0.300

0.296

0.292

Tj = 25°C

0.288

0.284

0.280

0.276 0 5 10 15 20 25 30

V

[V]

S

AM02576v1

Figure 25. Typical drain-source diode forward

ON characteristic

ISD[A]

3.0

2.5

2.0

1.5

1.0

0.5

0.0

700 800 900 1000 1100 1200 1300

Tj = 25°C

V

[mV]

SD

AM02577v1

Doc ID 022028 Rev 1 25/30

Package mechanical data L6206Q

10 Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK

Table 8. VFQFPN48 (7 x 7 x 1.0 mm) package mechanical data

®

packages, depending on their level of environmental compliance. ECOPACK®

®

is an ST trademark.

(mm)

Dim.

Min. Typ. Max.

A 0.80 0.90 1.00

A1 0.02 0.05

A2 0.65 1.00

A3 0.25

b 0.18 0.23 0.30

D 6.85 7.00 7.15

D2 4.95 5.10 5.25

E 6.85 7.00 7.15

E2 4.95 5.10 5.25

e 0.45 0.50 0.55

L 0.30 0.40 0.50

ddd 0.08

26/30 Doc ID 022028 Rev 1

L6206Q Package mechanical data

Figure 26. VFQFPN48 (7 x 7 x 1.0 mm) package outline

Doc ID 022028 Rev 1 27/30

Order codes L6206Q

11 Order codes

Table 9. Ordering information

Order codes Package Packaging

L6206Q

QFN48 7 x 7 x 1.0 mm

L6206QTR Tape and reel

Tr ay

28/30 Doc ID 022028 Rev 1

L6206Q Revision history

12 Revision history

Table 10. Document revision history

Date Revision Changes

15-Nov-2011 1 First release

Doc ID 022028 Rev 1 29/30

L6206Q

Please Read Carefully:

Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice.

All ST products are sold pursuant to ST’s terms and conditions of sale.

Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein.

No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein.

UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.

UNLESS EXPRESSLY APPROVED IN WRITING BY TWO AUTHORIZED ST REPRESENTATIVES, ST PRODUCTS ARE NOT RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK.

Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST.

ST and the ST logo are trademarks or registered trademarks of ST in various countries.

Information in this document supersedes and replaces all information previously supplied.

The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.

STMicroelectronics group of companies

Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -

Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America

www.st.com

30/30 Doc ID 022028 Rev 1