3 HIGH SIDE DRIVER S:
2A (HSD1), 0.45A (HSD2 & HSD3)
NO EXTERNAL CHARGE PUMP CAPACITORS ARE REQUIRED
STAND BY MODE CONTROLLED BY 3 INPUT PIN S:
ENABLE FOR REG2 AND REG 3,
2
I
C BUS FOR REG1, REG4, REG5, HSD1,
HSD2, HSD3
INDIVIDUAL THERM AL SHUT DOW N
INDEPENDENT CURRENT LIMITING
SHORT CIRCUIT PROTECTION
LOAD DUMP PROTECTION AND OVERVOL-
TAGE SHUTDOWN
ESD PROTECTED
L5950
MULTIPLE MULTIFUNCTION
Multiwatt15
DESCRIPTION
The ASPM (Audio System Power Module) is an
integration of three high side drivers and five
regulators developed to provide the power for an
audio system.
The outputs of the IC are controlled via the I
bus and the Enable input.
External protection must be provided for reverse
battery protection.
2
C
BLOCK DIAGRAM
BAT
GND
VREF
ENABLE
SCL
SDA
VOLTAGE
REFERENCE
8.5 & 5V
ENABLE
PC OUTPUT
CONTROL
CURRENT
LIMIT
PROTECTION
LOGIC
INDIVIDUAL
THERMAL
SHUTDOWN
OVERVOLTAGE
PROTECTION
REG 1
10V 350mA
REG 2
8.5V 175mA
REG 3
5V 350mA
REG 4
8V/10V 1A
REG 5
5V 250mA
DRIVE 1
2A
DRIVE 2
450mA
DRIVE 3
450mA
REG1
REG2
REG3
REG4
REG5
HSD1
HSD2
HSD3
D99AU1002
March 2001
1/8
Page 2
L5950
ABSOLUTE MAXIMUM RATINGS
SymbolParameterValueUnit
V
S
V
S
V
in
V
out
T
op
T
stg
PIN CONNECTION
DC Operating Supply Voltage-0.6 to 26.5V
Transient Supply Overvoltages, rise time = 10ms
34V
delay time = 115ms
Input Voltages (EN, SDA, SCL)-0.6 to 9V
Output Control Voltage-0.6 to 6.0V
Operating Temperature Range-40 to 85
Storage Temperature Range-40 to 150
C
°
C
°
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
REG4
BAT
REG5
REG3
REG2
REG1
VREF
GND
SCL
Enable
SDA
HSD3
HSD2
BAT
HSD1
D99AU1006
THERMAL D AT A
SymbolParameterValueUnit
Rth j-caseThermal Resistance Junction-case2°C/W
2/8
Page 3
L5950
ELECTRICAL CHARACTERISTICS
(Refer to the application circuit, V
= 14.4V; T
S
= 25°C; unless
amb
otherwise specified.)
SymbolParameterTest ConditionMin.Typ.Max.Unit
I
q,ST-BY
I
q
I
EN
, V
V
IL
10V/350mA REG 1 OUTPUT
V
REG1
V
∆
line
V
∆
load
V
DROPOUT
I
lim1
SVRRipple Rejectionf
8.5V/175mA REG 2 OUTPUT
V
REG2
V
∆
line
V
∆
load
V
DROPOUT
I
lim2
SVRRipple Rejectionf
5V/350mA REG 3 OUTPUT
V
REG3
V
∆
line
V
∆
load
Standby Quiescent CurrentAll Outputs Off, V
Maximum Quiescent CurrentV
Enable Input CurrentV
BAT
I
REG2
I
REG4
I
HSD1
BAT
= 14V, I
= 175mA, I
= 1A, I
REG5
= 2A, I
HSD2,3
= 14V,
= 14V2
BAT
= 350mA,
REG1
REG3
= 350mA,
= 250mA,
= 450mA
Enable ≥ 2V
V
BAT
= 14V,
-10
Enable ≥ 0.8V
Enable Threshold VoltageV
IH
Output VoltageI
= 14V, V
BAT
V
= 14V, V
BAT
= 350mA
REG1
11V ≤ V
CC
IL
IH
≤ 16V
2
9.501010.5V
Line Regulation11V ≤ VCC ≤ 26V
(Measure ∆ V
REG1
Across V
CC
Range)
Load Regulation5mA ≤ I
Dropout Voltage (Measure
V
- V
REG1
when V
REG1
BAT
0.1V)
drops
(Measure V
V
REG1
I
REG1
I
REG1
≤ 350mA55mV
REG1
- V
REG1
when
BAT
drops 0.1V)
= 350mA
= 5mA
Current Limit0.511.1A
= 1kHz, V
o
BAT
= 14V
50dB
with 1Vpp AC
I
= 175mA
REG1
Output VoltageI
Line Regulation9.5V ≤ V
= 175mA
REG2
9.5V ≤ V
BAT
BAT
(Measure ∆ V
≤ 16V
≤ 26V
REG2
Across V
8.38.58.7V
BAT
Range)
Load Regulation5mA ≤ I
Dropout Voltage (Measure VBAT- V
V
REG2
I
REG2
I
REG2
≤ 175mA50mV
REG2
when
REG2
drops 0.1V)
= 175mA
= 5mA
Current Limit280525mA
= 1kHz, V
o
BAT
= 14V
50dB
with 1Vpp AC
I
= 100mA
REG2
Voltage Offset from VREF1040mV
Line Regulation7V ≤ V
(Measure ∆ V
BAT
≤ 26V
REG3
Across V
BAT
Range)
Load Regulation5mA ≤ I
≤ 350mA100mV
REG3
150mA
10
0.8V
55mV
900
300
50mV
900
300
40mV
µ
µ
µ
V
mV
mV
mV
mV
A
A
A
3/8
Page 4
L5950
ELECTRICAL CHARACTERI S TICS
(continued)
SymbolParameterTest ConditionMin.Typ.Max.Unit
V
DROPOUT
I
lim3
SVRRipple Rejectionf
Dropout Voltage (Measure
VBAT- V
REG3
when V
REG3
drops 0.1V)
(Measure VBAT- V
V
drops 0.1V)
REG3
I
= 175mA
REG3
I
= 5mA
REG3
REG3
when
950
600
Current Limit0.51A
= 1kHz, V
o
BAT
= 14V
50dB
with 1Vpp AC
I
= 175mA
REG3
8/10V/1A REG 4 OUTPUT
V
∆
REG4
V
line
Output VoltageI
REG4
= 1A
b5 = 0
b5 = 1
Line Regulation11V ≤ V
(Measure ∆ V
≤ 26V, b5 = 1
BAT
REG2
Across V
BAT
7.6
9.50
10
8
8.4
10.5
50mV
Range)
V
∆
V
DROPOUT
I
lim4
load
Load Regulation5mA ≤ I
Dropout Voltage (Measure VBAT- V
Current Limit1.32.4A
SVRRipple Rejectionf
V
REG2
I
REG4
I
REG4
= 1kHz, V
o
≤ 1A150mV
REG4
when
REG2
drops 0.1V)
= 1A
= 5mA
BAT
= 14V
50dB
950
600
with 1Vpp AC
I
= 500mA
REG4
5V/250mA REG 5 OUTPUT
V
∆
REG5
V
line
Output VoltageI
REG5
Line Regulation7V ≤ V
(Measure ∆ V
= 250mA4.7555.25V
BAT
≤ 26V
REG5
Across V
BAT
40mV
Range)
V
∆
V
DROPOUT
I
lim5
load
Load Regulation5mA ≤ I
Dropout Voltage (Measure VBAT- V
Current Limit320700mA
SVRRipple Rejectionf
V
REG5
I
REG5
I
REG5
= 1kHz, V
o
≤250mA100mV
REG5
when
REG5
drops 0.1V)
= 250A
= 5mA
BAT
= 14V
50dB
1.6
1.2
with 1Vpp AC
I
= 125mA
REG5
2A HSD1
V
sat
Output Saturation VoltageIHSD1 = 1A
0.5V
Continuous Time Operation
I
leak1
I
lim
Output Leakage CurrentAll Driver Outputs are Off-5050
Current LimitingR
HSD1
= 0.5
Ω
2.44A
0.45A HSD2 & HSD3
V
sat
Output Saturation VoltageIHSD2,3 = 300mA
0.6V
Continuous Time Operation
I
leak2,3
I
lim
Output Leakage CurrentAll Driver Outputs are Off-5050
Current LimitingR
HSD2,3
= 0.5
Ω
0.561A
mV
mV
V
V
mV
mV
V
V
µ
µ
A
A
4/8
Page 5
L5950
ELECTRICAL CHARACTERI S TICS
(continued)
SymbolParameterTest ConditionMin.Typ.Max.Unit
2
CHARACTERISTICS FOR I
V
IL
V
IH
V
HYS
V
OL1
V
OL2
I
I
f
SCL
LOW Level Input Voltage1.5V
HIGH Level Input Voltage3V
Input Hysteresis0.2V
LOW Level OutputSink Current = 3mA
Input Current0.4V ≤ VI ≤ 0.9V
SCL Clock Frequency400kHz
FUNCTIONAL DESCRIP TION
The three high side drivers are a 2.0A output
(HSD1), and two 450mA outputs (HSD2 & 3). The
five regulator outputs are a 10V at 350mA
(REG1), an 8.5V at 175mA (REG2), a 5V at
350mA (REG3), an 8V/10V at 1A (REG4), and 5V
at 250mA (REG5). The regulators are low dropout. The regulators will operate with output capacitors with ESR of 0.1Ω to 5Ω.
The 8.5V regulator output (REG2) is a tighter tolerance output than the other regulator outputs.
The 8.5V output is a ±2.5% (5% total range) output over temperature. This is required on the
regulator to improve performance and reduce
cost on the 8.5V driven IC’s in the radio. The
tighter tolerance is possible by performing a trim
of the bandgap reference to the 8.5V output. The
other outputs are ±5% variation over temperature.
C
0.4
Sink Current = 6mA
DDmax
-1010
0.6
while 10V is the output voltage when bit5 = ’1’.
When all outputs are turned off the total current
draw must be minimized. I
2
C will run at a clock
speed range of 100kHz to 400kHz. This device
should be capable of operating at any frequency
within this range.
Protection
The L5950 can survive under the following conditions: shorting the outputs to BAT and GND, loss
of BAT, loss of IC GND, double battery(+26.5V),
4000V ESD, 34V load dump. L5950 will not handle a reverse battery condition. External components must be implemented for reverse battery
protection.
Thermal Shutdown: REG1, REG2, REG3, REG4,
REG5 outputs shutdown at 160°C and return to
normal operation at 130°C. The HSD2 and HSD3
shutdown at 160°C and return to normal operation at 130°C. The HSD1 with go into thermal
REG3 is referenced from the VREF input not the
internal bandgap. This is done to minimize the
voltage offset between individual 5V supplies.
The REG2 and REG3 outputs are turned on and
off with the Enable input, a ’1’ turns the outputs on
and a ’0’ turns them off. When Enable is "1", the
other outputs can be independently controlled via
2
C bus. When a given regulator is turned off it
the I
must be guaranteed to be lower than 0.2V. The
output voltage of REG4 is selected via bit 5 of the
2
C data byte: 8V is the output voltage if bit5 = ’0’
I
shutdown at 170°C and returns to operation at
120°C.
Current Limiting: each voltage regulator will contain its own current protection.
Short Circuit: If the outputs are short circuited, the
IC will go into current limiting and eventually the
thermal shutdown will kick in. Current limiting will
not disable the outputs.
Overvoltage: The IC will not operate if the BAT
voltage reaches 27V typ. or above.
V
V
A
µ
Figure 1. Definition of Timing on the I2C Bus.
SDA
t
BUP
SCL
PSP
t
HD;DAT
t
LOW
t
HD;DAT
t
R
t
HIGH
t
F
t
SU;DAT
t
SU;STA
t
HD;STA
Sr
D99AU1007
t
SP
t
SU;STO
5/8
Page 6
L5950
Figure 2. Typical Application Circuit.
EN
FBATT
1000µF0.1µF
(*) ESR of output capacitors should be between 0.1Ω and 5.0Ω.
VREF
ENABLE
BAT
VREF
SCL
SDA
GND
REG1
REG2
REG3
REG4
REG5
HSD1
HSD2
HSD3
REG5
C14
10µF
REG4
C12
10µF
HSD1
HSD2
HSD3
D99AU1010A
REG3
C10
10µF
REG2
C8
10µF
REG1
C6
10µF
WRITE MODE:
CHIP ADDRESSDATA BYTE
S0AA....P
MSBLSBMSBLSB
S = START condition - SDA goes from high to low while SCL is high
A = Acknowledge - the device being written to, pulls down on data line (SDA) during the acknowledge
clock pulse.
P = STOP condition - SDA goes from low to high while SCL is high.
CHIP ADDRESS BYTE:
CHIP ADDRESSREAD/WRITE
A7A6A5A4A3A2A1A0
00010000
DATA BYTE:
DATA BYTE
REG1R4 10VREG4REG5HSD1HSD2HSD3
b7b6b5b4b3b2b1b0
X
Default mode is 0000 0000 which corresponds to all outputs being off, low power mode.
Bit 5 Controls the output voltage of REG4. A ’0’ corresponds to 8V and a ’1’ corresponds to 10V.
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