The KS9287 is a Digital Signal Processor for VCD and Hi-Fi CD players. It has enhanced the picture quality of
VCD. This IC, when compared to the existing product, has vastly improved its performance in the following areas.
— Frame Sync Detect
— Error Correcting Code Ability
— CLV Performance
— DPLL Capture Range
— EFM Signal Compensation
1VDDA-Analog VDD
2DPDOOCharge pump output for Digital PLL
3DPFINIFilter input for Digital PLL
4DPFOUTOFilter output for Digital PLL
5CNTVOLIVCO control voltage for Digital PLL
6VSSA-Analog Ground
7DATXODigital Audio Serial Output
8XINIX'tal oscillator input
9XOUTOX'tal oscillator output
10WDCHOWord clock output of 48 bits/Slot (88.2 kHz)
11LRCHOChannel clock output of 48 bits/Slot (44.1 kHz)
12SADTOSerial audio data output of 48 bits/Slot (MSB first)
13VSS-Digital Ground
14BCKOBit clock output of 48 bits/Slot (2.1168 MHz)
15C2POOC2 Pointer for Serial audio data
16TIM2ONormal or Double speed control output
17EFMFLAGO8 to14 demodulation error flag
18UDTFLAGOUndesiable T Flag (Lower 3T signal in EFM signal)
19FSYNCODetected Frame Sync
20EFMZOEFM signal demodulated NRZI
21V34MOInternal VCO clock (34.5744MHz)
22TEST0ITest input (H: Test, L: Normal)
23RBCKIRead base clock
24EMPHOEmphasis output (H: Emphasis On, L: Emphasis Off)
25LKFSOThe Lock Status output of frame sync
26S0S1OOutput of subcode sync signal (S0+S1)
27RESETISystem reset at "L"
28SQENISQCK control signal (H: External clock, L: Internal clock)
29SQCKI/OSubcode-Q data bit clock
30SQDTOSerial output of Subcode-Q data
31SQOKOThe CRC check result signal output of Subcode-Q
32SBCKISubcode data bit clock
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DIGITAL SIGNAL PROCESSORKS9287
PIN DESCRIPTION (Continued)
No.Pin NameI/ODescription
33SBDTOSubcode data serial output
34VDD-Digital VDD
35MUTEIMute control input ("H": Mute ON)
36MLTILatch Signal Input from MICOM
37MDATISerial data input from MICOM
38MCKISerial data transfering clock input from MICOM
39RD7I/OSRAM data I/O port (MSB)
40RD6I/OSRAM data I/O port 6
41RD5I/OSRAM data I/O port 5
42RD4I/OSRAM data I/O port 4
43RD3I/OSRAM data I/O port 3
44RD2I/OSRAM data I/O port 2
45RD1I/OSRAM data I/O port 1
46RD0I/OSRAM data I/O port 0 (LSB)
47FLAG1I/OMonitoring output for ECC (RA0)
48FLAG2I/OMonitoring output for ECC (RA1)
49FLAG3I/OMonitoring output for ECC (RA2)
50FLAG4I/OMonitoring output for ECC (RA3)
51FLAG5I/OMonitoring output for ECC (RA4)
52/PBCKI/O VCO/2 clock output (4.3218 MHz) (RA5)
53VSSI/ODigital ground
54FSDWI/OFrame Sync protection Window (RA6)
55ULKFSI/OFrame sync protection status (RA7)
56/JITI/ODisplay of either RAM overflow or underflow for ±4 frame jitter margin (RA8)
57C4MI/O4.2336 MHz signal output (RA9)
58C16MI/O16.9344 MHz signal output (RA10)
59/WEI/OWrite enable signal for external SRAM
65TEST1ITEST input terminal (GND connection)
66EFMIIEFM signal input
67DSVOODigital sum value output
68/ISTATOThe internal status output
69TRCNTITracking counter input signal
70LOCKOOutput signal of LKFS condition sampled PBFR/16
(if LKFS is "H", LOCK is "H",
if LKFS is sampled "L" at least 8 times by PBFR/16, LOCK is "L")
71WBCKOWrite frame clock (Lock : 7.35 kHz)
72SMEFOLPF time constant control of the spindle servo error signal
73SMONOON/OFF control signal for spindle servo
74VDD-Digital VDD
75SMDPOSpindle Motor drive
(Rough control in the SPEED mode, Phase control in the PHASE mode)
76SMDSOSpindle Motor drive (Velocity control in the PHASE mode)
77VCOOOVCO output
78VCOIIVCO input (8.6436MHz when locked by WBCK)
79DSPEEDIDouble speed mode select (H: Normal, L: 2 times)
80APDOOAnalog PLL charge pump output
Data input from MICOM is received in MDAT, and transmitted by MCK. This signal is stored in the Control Register
by MLT. The Timing diagram for this process is shown in Figure 1
.
MDAT
MCK
MLT
Register
(9X ~ FX)
MDAT
MCK
MLT
Register
(88XX ~ 8DXX)
D0D1D2D3D4D5D6D7 <MSB>
D0D1D2D3D4D15 <MSB>D11D12D13D14
Figure 1. MICOM Data Input Timing Diagam
Table 1. Control Register and Data
RegisterName
CNTL-ZData control1001
Address
D7~D4
(9X)
Valid
¡ó
¡ó
Valid
Data
D3D2D1D0
ZCMTHIPDNCLVCRCQHI-Z
/ISTAT
Pin
CNTL-SFrame sync protect,
attenuation control
CNTL-LTracking counter
(lower)
CNTL-UTracking counter
(upper)
1010
(AX)
1011
(BX)
1100
(CX)
CNTL-WCLV control1101
(DX)
CNTL-CCLV-mode1110
(EX)
CNTL-DDouble-speed1111
(FX)
FSEMFSELWSELATTMHI-Z
TRC3TRC2TRC1TRC0/complete
TRC7TRC6TRC5TRC4/count
-WBWPGAINHI-Z
CLV MODE
/(Pw ≥ 64)
--DS1DS2HI-Z
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DIGITAL SIGNAL PROCESSORKS9287
RegisterName
Address
D11~D8
CNTL-FFunction control10001000
(88X)
CNTL-TEFM Signal
control
CNTL-EFrame Sync
detection control
CNTL-HDPLL, monitor
pin control
10001011
(8BX)
10001100
(8CX)
10001101
(8DX)
Data
D7D6D5D4D3D2D1D0
CDROMIIS
VCON
RBSELFWSELFSMD1FSMD0
RES8
-----
---
-
ERA
OFF
C1PNTSADTSWWDCH
SEL1
VSELDSV
----
DUMB3DUMB2DUMB1DUMB0
WDCH
SEL0
INV
/ISTAT
Pin
HI-Z
HI-Z
HI-Z
HI-Z
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DIGITAL SIGNAL PROCESSORKS9287
Detail Description of Control Register
1. CNTL-Z ($9X)
This register carries out the following functions: audios zero cross mute, phase pin control,
phase servos control signal management, and the decision whether or not to include SQOK data
in SQDT.
Bit3210
IdentifierZCMTHIPDNCLVCRCQ
ZCMTZero cross mute
0Zero cross mute is OFF
1Zero cross mute is ON
HIPDPhase pin control
0Phase operates normally
1Phase goes from low to Hi-Z by LKFS
NCLVPhase servos control
0Phase Servo controlled by Frame Sync
1Phase Servo controlled by Base Counter
CRCQ
0SQDT output not including SQOK
1SQDT = SQOK, when SOS1 is “H”.
2. CNTL-S ($AX)
This register sets the frame sync protection and attenuation. FWSEL of CNTL-D is added to define
window size. .
Bit3210
IdentifierFSEMFSELWSELATTM
FSEM, FSEL Frame sync protection
002
014
108
1113
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DIGITAL SIGNAL PROCESSORKS9287
FWSEL, WSEL Frame Sync protection window size
00
01
10
11
+/- 3T
+/- 7T
+/- 13T
+/- 26T
ATTM, MUTEControl the Frame Sync attenuation
00 0 dB
01- ∞ dB
10-12 dB
11-12 dB
3. CNTL-L, U ($BX, $CX)
When the number of tracks to be counted is input from MICOM, the CNTL-L, or CNTL-U register
loads the data into the tracking counter. This tracking counter is used for improving track jump
characteristics.
When the number of tracks to be jumped is input from MICOM, the track number is loaded from
MLTs positive edge to the register. If CNTL-L is selected, /COMPLETE signal is output to the
/ISTAT pin, and if CNTL-U is selected, /COUNT signal is output. The Timing Diagrams of the
tracking counters are Figure-2 and Figure-3.
MLT
CNTL-L,
CNTL-U
TRCNT
/ISTAT
=(/count)
/ISTAT
=(/complete)
N
N
NNNN
Figure 2. Tracking Counter Timing Diagram
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DIGITAL SIGNAL PROCESSORKS9287
MDAT
MLT
CNTL State
CNTL-LCNTL-UCNTL-COther Mode
/complete/count/(PW > 64)Hi-ZCNTL State
Figure 3. /ISTAT Output Signal According to the CNTL Register
4. CNTL-W ($DX)
This register sets the CLV-Servos control period and gain..
The EFM block is composed of the following parts: EFM demodulator to demodulate the EFM signal read from the
disc, EFM phase detector, and the control signal generator.
1) EFM Phase Detector
The EFM signal input from the Disc includes 2.1609 MHz components. To detect the phase of this signal, a Bit
Clock (/PBCK) of 4.3218 MHz is used. PBCK detects the phase of the EFM signals Edge, and sends the results to
the APD0 pin.
VCOI
PBCK
EFMI
EFMD
APDO
¨ç¨è¨é
(1) When theEFM signal is slower than the VCO signal
(2) When the EFM signal is locked to the VCO signal
(3) When the EFM signal is faster than the VCO signal.
Figure 4. EFM Phase Detector Timing Diagram
2) EFM Demodulation
The modulated 14 channel bit data is demodulated into 8-bit data. There are two types of demodulated data:
subcode data and audio data. Subcode data is input into the subcode handling block, and the audio data is stored
in the internal SRAM, and its errors are corrected.
3) Frame Sync Detect/Protect/Insert
• Frame Sync Detect
Data is composed of units of frame, and a frame is composed of frame sync, subcode data, audio data, and
redundancy data. This IC detects frame sync to maintain synchronization, and there are three detection methods
(refer to CNTL-E Command):(1) Pattern Detect Method
(2) Period Detect Method
(3) Compensation Detect Method: Combination of the methods above
• Frame Sync Protect/Insert
There are some cases in which frame sync is not detected, or detected it from other data which does not include
frame sync, due to disc error or jitter. In these cases, the frame sync must be protected and inserted.
To protect frame sync, a window is made by WSEL of the CNTL-S register. The frame sync entering this window is
considered valid data, and the frame sync which leaves this window is ignored. If frame sync is not detected within
the frame sync protect window, insert instead the frame sync made in the internal counter. If frame sync is inserted
continuously, reaching the number of frames set by FSEM and FSEL of the CNTL-S register, the following occurs:
ULKFS becomes H, the frame sync protect window is ignored, and the frame sync detected next is accepted
unconditionally. When a frame sync is accepted, the ULKFS signal becomes L, and accepts the frame sync
detected within the window (refer to below Table).
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DIGITAL SIGNAL PROCESSORKS9287
LKFSULKFSComment
11Play back frame sync and the generated sync coincide.
1) The play back frame sync and the generated frame sync do not coincide,
01
00
ECC
When disc data is damaged, it is corrected using the ECC (Error Correcting Code) block. It uses the CIRC (Cross
Interleaved Reed-Solomon Code), correcting up to 2 errors when C1(32, 28), and up to 4 erasures when C2(28,
24). Error correction handles the data in units of 8-bit 1 symbol.
The ECC block has Pointer handling function, and can generate a C1 pointer in C1 correction, and a C2 pointer in
the C2 correction. The C1 and C2 pointers output a flag about the ECC-handled data to mark it as error data. This
Flag information signal is input into the interpolator, and used for handling the error data. Also, the Error correcting
results can be monitored using the FALF5 ~ FLAG1 pins.
but PBFR sync is detected from within the window selected by WEL.
2) PBFR sync and XTFR sync do not coincide, and are not detected from within the window
selected by WSEL. Sync insert is carried out.
1) Immediately after the following situation: Frame sync is not detected within the window,
so frame is inserted in the amount set by CNTL-S registers FSEM and FSEL.
2) If PBFR sync is still undetected after 1).
Table 2. Error Correction Monitoring Flag Results
ModeFLAG5FLAG4FLAG3FLAG2FLAG1Remark
C1 No error00000C1 Correction start
C1 1 error Correction00001C1 2 error Correction00010C1 No Correction01111C1 flag set
C2 No error10000C2 Correction start
C2 1 error Correction10001C2 2 error Correction10010C2 3 error Correction10011C2 4 error Correction10100C2 No Correction11110C1 flag copy
C2 No Correction11111C2 flag set
Note:When carrying out forward or backward fast search, MICOM must give the Attenuation, or the MUTE command
to the DSP IC. If not, an error can occur when carrying out erasure correction during fast search.
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DIGITAL SIGNAL PROCESSORKS9287
CLV SERVO
CNTL-C, E, G1, G2, and G3 registers are selected to control the CLV (Constant Linear Velocity) servo using the
data input from MICOM. Also, the design is such that the servo control is stable when setting the speed. When
setting the speed, the /(Pw≥64) signal can be detected from the /ISTAT pin only if the CNTL-D register is first set
before the CNTL-C register is selected.
1) Forward
This mode rotates the spindle motor in the forward direction. The related output pin status are as follows.
SMDPSMDSSMEFSMON
HHi-ZLH
2) Reverse
This mode rotates the spindle motor in the reverse direction. The related output pin status are as follows.
SMDPSMDSSMEFSMON
LHi-ZLH
3) Speed-mode
This mode is used for rough control of the spindle motor when the track jump or EFM phase is unlocked. If one
period of VCO is T, the pulse width of the frame sync is 22T. There are some cases in which the signal detected in
the EFM signal is larger than 22T because of disc noise. If you do not eliminate this signal, the correct frame sync
cannot be detected. In that case, the EFM signals pulse width is detected using the period of the peak hold clock
RBCK/2 or RBCK/4. Also, detect the EFM signals pulse width using the period of the bottom hold clock RBCK/16
or RBCK/32.
SMDPSMDSSMEFSMON
H: Accelerate
Hi-ZLH
L: Decelerate
Hi-Z: Maintain
5) Phase-Mode
This mode controls the EFM phase. It detects and outputs to the SMDP pin, the WBCK/4 and RBCKs phase
difference, when in CLV Normal Control mode and when CNTL-Z registers NCLV is “L” (refer to Figure-5). If VCO/
2s signal period is T, the amount of time during which WBCK is “H” is called tHW, and FRSLP is “0”, “H” is output
from WBCKs negative edge to the SMDS pin during (t
- 279T) +1 x 32 or (t
HW
- 560T) x 32 and “L” is output
HW
until the next WBCKs negative edge (refer to Figure 5).
SMDPSMDSSMEFSMON
H: Accelerate
H/LLH
L: Decelerate
Hi-Z: Maintain
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DIGITAL SIGNAL PROCESSORKS9287
6) Stop
This mode stops the spindle motor.
SMDPSMDSSMEFSMON
LHi-ZLL
1) SPEED mode
P22T
N22T
SMDPdecelerationacceleration
= 22 t over 22 t under 22 t
2) PHASE mode
- Phase Error Signal
RBCK/4
WBCK/4
DOWN
UP
SMDP
- Frequency Error Signal
CLV_SW = 0 : Frequency Error Signal = ( t
t
287 t
WBCK
SMDS
CLV_SW = 1 : Frequency Error Signal = ( t
t
570 t
WBCK
- 279 t ) + 1* 32
HW
HW
288t512 t
HW
t
HW
294 t
t
HW
580 t
- 560 t ) * 36
HW
SMDS
360 t720 t
Figure 5. SMDS, SMDP Output Timing Diagram in Normal Control Mode
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DIGITAL SIGNAL PROCESSORKS9287
Q2
SUBCODE
The subcode sync signals S0 and S1 are detected in the Subcode sync block. S1 is detected one frame after S0 is
detected. At this time, S0+S1 signal is output to the S0S1 pin, and when the S0S1 signal is H, the S0S1 signal is
output to the SDAT pin. Out of the data input into the EFMI pin, the 14-bit subcode data is EFM demodulated to 8bit (P, Q, R, S, T, U, V, W) subcode data, synchronized with the WBCK signal , and output to SDAT by the SBCK
clock. Out of the 8 subcode data, only Q data is stored in the 80 shift registers by the WBCK signal. If the CRC
result is error, L is output to the SQCK pin, and if not, H is output. If the CNTL-Z registers CRCQ is H, the CRC
result is output to the SQDT pin from when the S0 and S1 are H to SQCKs negative edge. The Subcode blocks
timing diagram is as follows:
1) The Timing Relation of SQCK, SQDT and S0S1 when SQEN=H
* If subcode-Q datas CRCQ is H, the SQOK signal is output to SQDT according to the SQCK, and if CRCQ is L,
the SQOK signal is not output to SQDT..
2) The Timing Relation of SQCK, SQDT, and S0S1 when SQEN=H
SQCK
S0S1
SQOK
SQDT
Q97 SQOKQ1Q2Q3Q4Q5Q6Q93Q94Q95Q96Q97¡óSQOK¡óQ1
¡ó
¡ó
¡ó
¡ó
Figure 7. Subcode-Q Timing Diagram 2
0
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DIGITAL SIGNAL PROCESSORKS9287
3) Timing Relation of SDAT and SBCK
WBCK
12345678
a
SBCK
SDAT
bQRSTUVW
C
a) After PBFR goes negative edge, SBCK is set to L for about 10 us.
b) If S0S1 is L, subcode P is output, and if S0S1 is H, S0S1 is output.
c) If there are more than 7 pulses input into the SBCK pin, the subcode data P, Q, R, S, T,
U, V, and W data are output repeatedly.
Figure 8. Subcode-Q Data Output Timing Diagram 3
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DIGITAL SIGNAL PROCESSORKS9287
INTERPOLATION / MUTE
Interpolator
If a burst error occurs on the disc, sometimes data cannot be corrected even if you carry out the ECC process. The
Interpolator block uses the ECCs C2 pointer to interpolate the data.
The audio data is input into the Data bus in the following order: for each L/R-ch: 8-bit C2 point, lower data 8-bit, and
upper data 8-bit.
If C2P0 pin is H, and one error has occurred, the average value interpolation is carried out, and if 3 consecutive
errors occurred, the previous value hold interpolation is carried out.
For one period of LRCH, if LRCH is L, R-ch data is output, and if H, L-ch data is output. Please refer to Figure 7 for
the Interpolator blocks Timing Chart.
A
B
C
H
G
DEF
I
J
C2
Pointer
B : Average value Interpolation
F , E , D : Previous value Hold Interpolation
G : Average value Interpolation
Figure 9. Interpolation Method
Mute/Attenuation
The audio data can be muted or weakened by the ATTM signal of the MUTE pin and CNTL-S register.
• Zero Cross Mute
The audio data is muted when the CNTL-Z registers ZCMT is H, mute is H, and the upper 6 bits of audio data
are all H.
•Muting
The audio data is in Muting is the CNTL-Z registers ZCMT is L and the Mute pin is H.
•Attenuation
Audio signal is weakened by the CNTL-Z registers ATTM and Mute signal.
Figure 10. Serial Audio Data Output Timing Diagram
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DIGITAL SIGNAL PROCESSORKS9287
DIGITAL AUDIO OUT
This block serially outputs 2 channel and 16-bit data with the digital audio interface format as reference.
1) Digital audio interface format for CD
191 R0L0R1L1R190 R191L191R0L-R190 L
T
192 T
0L: L-ch format including the block sync preamble
1L ~ 191L: L-ch format including the L-ch sync preamble
0R ~ 191R: R-ch format including the R-ch sync preamble
The Preamble is used to distinguish the datas block and L/R ch data
.
8.4672 MHz
(except block sync)
R-ch. sync
Block sync (L-ch.)
Figure 12. Preamble Signal
control signal
L-ch. sync
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DIGITAL SIGNAL PROCESSORKS9287
• Control Signal
(1) Validity bit: shows the presence of error in 16-bit audio data: “H”=error, “L”=valid data
(2) User definable bit: subcode data out
SOS1
PBFR
SBCK
SBDT
Sync PatternPQRSTUV W
Figure 13. Digital Audio Data Out Timing Diagram
(3) Channel status bit: subcode-Qs upper 4-bit data output, shows number of channels, pre-emphasis, copy, CDPcategory, etc.
SOS1
SQDT
ID0 ID1 COPY EMPH
PBFR
Figure 14. Channel Status Data Out Timing Diagram
(4) Parity Bit: makes even parity
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DIGITAL SIGNAL PROCESSORKS9287
DIGITAL PLL
This IC has a built-in analog PLL and a digital PLL to generate a stable channel clock needed during EFM signal
demodulation. Figure-15 shows the DPLL application.
Frequency Synthesizer
X'tal
EFMI
Phase
Comparator
1/N Devider
Low Pass Filter
Digital Main PLL
Figure 15. Application Diagram of Digital PLL
Voltage
Cotrolled
Oscillator
/PBCK
29
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