Page 1
KM68512A Family CMOS SRAM
Document Title
64Kx8 bit Low Power CMOS Static RAM
Revision History
Revision No.
0.0
0.1
1.0
2.0
3.0
4.0
History
Initial draft
Revision
Finalize
Revision
- Add 45ns part with 30pf test load.
Revision
- Change Data Sheet format :
One data sheets for industrial and commercial product
Revision
- Change Data Sheet format
- Remove 45ns part from commercial product and 100ns part
from industrial product
- Remove low power part form TSOP package
Draft Data
Novemer 28, 1993
May 13, 1994
December 1, 1994
August 12, 1995
April 15, 1996
January 9, 1998
Remark
Design target
Preliminary
Final
Final
Final
Final
The attached data, sheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
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Revision 4.0
January 1997
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KM68512A Family CMOS SRAM
64Kx8 bit Low Power CMOS Static RAM
FEATURES
• Process Technology: Poly Load
• Organization: 64Kx8
• Power Supply Voltage: 4.5~5.5V
• Low Data Retention Voltage: 2V(Min)
• Three state output and TTL Compatible
• Package Type: 32-SOP-525, 32-TSOP1-0820F
GENERAL DESCRIPTION
The KM68512A families are fabricated by SAMSUNG′s
advanced CMOS process technology. The families support
various operating temperature ranges and have various
package types for user flexibility of system design. The
families also support low data retention voltage for battery
back-up operation with low data retention current.
PRODUCT FAMILY
Product Family Operating Temperature VCC Range Speed
(ISB1, Max)
KM68512AL
KM68512AL-L 20µA
KM68512ALI
KM68512ALI-L 50µA
PIN DESCRIPTION
1
N.C
2
N.C
A14
3
A12
4
A7
5
A6
6
A5
7
A4
8
A3
A2
A1
A0
I/O1
I/O2
I/O3
VSS
32-SOP
9
10
11
12
13
14
15
16
Name Function
CS1, CS2 Chip Select Inputs
OE Output Enable Input
WE Write Enable Input
A0~A15 Address Inputs
I/O1~I/O8 Data Inputs/Outputs
Vcc Power
Vss Ground
N.C No Connection
Commercial (0~70°C)
4.5 to 5.5V
Industrial (-40~85°C) 70ns
VCC
32
A15
31
CS2
30
A11
A13
CS2
A15
VCC
A14
A12
WE
1
A9
2
A8
3
4
5
6
7
8
NC
9
NC
10
11
12
A7
13
A6
14
A5
15
A4
16
32-TSOP
Type1 - Forward
WE
29
A13
28
A8
27
A9
26
25
A11
24
OE
23
A10
22
CS1
21
I/O8
20
I/O7
19
I/O6
18
I/O5
17
I/O4
55/70ns
FUNCTIONAL BLOCK DIAGRAM
I/O1
I/O8
A3
A4
A5
A6
A7
A12
A13
A14
A15
Control
Logic
32
OE
A10
31
CS1
30
I/O8
29
I/O7
28
27
I/O6
26
I/O5
25
I/O4
24
VSS
23
I/O3
22
I/O2
21
I/O1
20
A0
19
A1
18
A2
17
A3
CS1
CS2
WE
OE
Power Dissipation
Standby
100µA
100µA
Clk gen.
Row
select
Data
cont
Data
cont
Operating
(ICC2, Max)
70mA
Precharge circuit.
Memory array
512 rows
128×8 columns
A0 A1 A2 A8 A9 A11A10
PKG Type
32-SOP
32-TSOP1-F
I/O Circuit
Column select
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
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KM68512A Family CMOS SRAM
PRODUCT LIST
Commercial Temperature Products(0~70°C) Industrial Temperature Products(-40~85°C)
Part Name Function Part Name Function
KM68512ALG-5
KM68512ALG-5L
KM68512ALG-7
KM68512ALG-7L
KM68512ALT-5L
KM68512ALT-7L
FUNCTIONAL DESCRIPTION
CS1 CS2 OE WE I/O Pin Mode Power
H
1)
X
L H H H High-Z Output Disabled Active
L H L H Dout Read Active
L H
1. X means don′t care.(Must be low or high state)
32-SOP, 55ns, L-pwr
32-SOP, 55ns, LL-pwr
32-SOP, 70ns, L-pwr
32-SOP, 70ns, LL-pwr
32-TSOP1-F, 55ns, LL-pwr
32-TSOP1-F, 70ns, LL-pwr
1)
X
L
1)
X
1)
X
1)
X
KM68512ALGI-7
KM68512ALGI-7L
KM68512ALTI-7L
1)
X
1)
X
High-Z Deselected Standby
High-Z Deselected Standby
32-SOP, 70ns, L-pwr
32-SOP, 70ns, LL-pwr
32-TSOP1-F, 70ns, LL-pwr
L Din Write Active
ABSOLUTE MAXIMUM RATINGS
1)
Item Symbol Ratings Unit Remark
Voltage on any pin relative to Vss VIN,VOUT -0.5 to 7.0 V Voltage on Vcc supply relative to Vss VCC -0.5 to 7.0 V Power Dissipation PD 1.0 W Storage temperature TSTG -65 to 150 °C -
Operating Temperature TA
0 to 70 °C KM68512A
-40 to 85 °C KM68512AI
Soldering temperature and time TSOLDER 260°C, 10sec(Lead Only) - -
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
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KM68512A Family CMOS SRAM
-0.5
1)
Vcc+0.5V
3)
- 0.8 V
2)
V
RECOMMENDED DC OPERATING CONDITIONS
Item Symbol Min Typ Max Unit
Supply voltage Vcc 4.5 5.0 5.5 V
Ground Vss 0 0 0 V
Input high voltage VIH 2.2 Input low voltage VIL
Note
1. Commercial Product : TA=0 to 70°C, unless otherwise specified
Industrial Product : TA=-40 to 85°C, unless otherwise specified
2. Overshoot : VCC+3.0V in case of pulse width≤30ns
3. Undershoot : -3.0V in case of pulse width≤30ns
4. Overshoot and undershoot are sampled, not 100% tested
CAPACITANCE
Input capacitance CIN VIN=0V - 6 pF
Input/Output capacitance CIO VIO=0V - 8 pF
1. Capacitance is sampled, not 100% tested
1)
(f=1MHz, TA=25°C)
Item Symbol Test Condition Min Max Unit
DC AND OPERATING CHARACTERISTICS
Item Symbol
Input leakage current ILI VIN=Vss to Vcc -1 - 1 µA
Output leakage current ILO CS1=VIH or CS2=VIL or OE=VIH or WE=VIL, VIO=Vss to Vcc -1 - 1 µA
Operating power supply current ICC IIO=0mA, CS1=VIL, CS2=VIH, VIN=VIH or VIL - 7 15 mA
Cycle time=1µs, 100% duty, IIO=0mA
ICC1
Average operating current
CS1≤0.2V, CS2≥VCC-0.2V, VIN≤0.2V or VIN≥Vcc -0.2V
Cycle time=Min, 100% duty, IIO=0mA, CS1=VIL, CS2=VIH, VIN=VIH or VIL
ICC2
Test Conditions
Min Typ Max Unit
- - 10 mA
- - 70 mA
Output low voltage VOL IOL=2.1mA - - 0.4 V
Output high voltage VOH IOH=-1.0mA 2.4 - - V
Standby Current(TTL) ISB CS1=VIH, CS2=VIL, Other inputs =VIH or VIL - - 3 mA
Standby
Current
(CMOS)
KM68512AL/L-L
KM68512ALI/LI-L
CS1≥Vcc-0.2V, CS2≥Vcc-0.2V or CS2≤0.2V
ISB1
Other inputs =0 ~ Vcc
Low Power
Low Low Power
Low Power
Low Low Power
4
--21100
20
--21100
50
Revision 4.0
January 1997
µA
µA
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KM68512A Family CMOS SRAM
AC OPERATING CONDITIONS
TEST CONDITIONS( Test Load and Input/Output Reference)
Input pulse level : 0.8 to 2.4V
Input rising and falling time : 5ns
Input and output reference voltage :1.5V
Output load(see right) : CL=100pF+1TTL
AC CHARACTERISTICS (Vcc=4.5~5.5V, KM68512A Family:TA=0 to 70°C, KM68512AI Family:TA=-40 to 85°C)
Parameter List Symbol
Read cycle time tRC 55 - 70 - ns
Address access time tAA - 55 - 70 ns
Chip select to output tCO1, tCO2 - 55 - 70 ns
Output enable to valid output tOE - 25 - 35 ns
Read
Write
Chip select to low-Z output tLZ 10 - 10 - ns
Output enable to low-Z output tOLZ 5 - 5 - ns
Chip disable to high-Z output tHZ 0 20 0 25 ns
Output disable to high-Z output tOHZ 0 20 0 25 ns
Output hold from address change tOH 10 - 10 - ns
Write cycle time tWC 55 - 70 - ns
Chip select to end of write tCW 45 - 60 - ns
Address set-up time tAS 0 - 0 - ns
Address valid to end of write tAW 45 - 60 - ns
Write pulse width tWP 40 - 50 - ns
Write recovery time tWR 0 - 0 - ns
Write to output high-Z tWHZ 0 20 0 25 ns
Data to write time overlap tDW 25 - 30 - ns
Data hold from write time tDH 0 - 0 - ns
End write to output low-Z tOW 5 - 5 - ns
1)
CL
1. Including scope and jig capacitance
Speed Bins
55ns 70ns
Min Max Min Max
Units
DATA RETENTION CHARACTERISTICS
Item Symbol
Vcc for data retention VDR
KM68512AL/L-L
Data retention current IDR
KM68512ALI/LI-L
Data retention set-up time tSDR
Recovery time tRDR 5 - -
1. CS1≥Vcc-0.2V, CS2≥Vcc-0.2V( CS1 controlled) or CS2≤0.2V(CS2 controlled).
CS11)≥Vcc-0.2V
Vcc=3.0V CS1≥Vcc-0.2V
CS2≥Vcc-0.2V or CS2≤0.2V
See data retention waveform
Test Condition
L-Ver
LL-Ver
L-Ver
LL-Ver
5
Min Typ Max Unit
2.0 - 5.5 V
-
1
-
0.5
-
-
0 - -
-
-
50
10
50
25
January 1997
µA
ms
Revision 4.0
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KM68512A Family CMOS SRAM
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1=OE=VIL, WE=VIH)
tRC
Address
tAA
tAA
Data Valid
tRC
tOH
tCO1
tHZ(1,2)
tOH
Data Out
Previous Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
Address
CS1
CS2
OE
Data out
NOTES (READ CYCLE)
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device
interconnection.
High-Z
tLZ
tOLZ
tCO2
tOE
tOHZ
Data Valid
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Revision 4.0
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KM68512A Family CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)
tWC
Address
tCW(2)
CS1
tAW
tWR(4)
CS2
WE
tAS(3)
Data in
tWHZ
Data out
Data Undefined
TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 Controlled)
Address
tAS(3)
CS1
CS2
WE
Data in
tWC
tCW(2)
tAW
tCW(2)
tWP(1)
tWP(1)
tDW
Data Valid
tDW
Data Valid
tDH
tOW
tWR(4)
tDH
Data out
High-Z
High-Z
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Revision 4.0
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KM68512A Family CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(3) (CS2 Controlled)
tWC
Address
tAS(3)
CS1
CS2
WE
Data in
Data out
NOTES (WRITE CYCLE)
1. A write occurs during the overlap of a low CS1, a high CS2 and a low WE. A write begins at the latest transition among CS1 goes low,
CS2 going high and WE going low : A write end at the earliest transition among CS1 going high, CS2 going low and WE going high,
tWP is measured from the begining of write to the end of write.
2. tCW is measured from the CS1 going low or CS2 going high to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR(1) applied in case a write ends as CS1 or WE going high tWR(2)
applied in case a write ends as CS2 going to low.
High-Z
tAW
tCW(2)
tCW(2)
tWP(1)
tDW
Data Valid
tWR(4)
tDH
High-Z
DATA RETENTION WAVE FORM
CS1 controlled
VCC
4.5V
tSDR
Data Retention Mode
tRDR
2.2V
VDR
CS1
GND
CS2 controlled
VCC
4.5V
CS2
VDR
0.4V
GND
tSDR
CS1≥VCC - 0.2V
Data Retention Mode
CS2≤0.2V
8
tRDR
Revision 4.0
January 1997
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KM68512A Family CMOS SRAM
PACKAGE DIMENSIONS
32 PIN SMALL OUTLINE PACKAGE (525mil)
#32
0.71
( )
0.028
#1
0.41
0.016
20.87
0.822
20.47±0.20
0.806±0.008
+0.100
-0.050
+0.004
-0.002
MAX
1.27
0.050
#17
#16
14.12±0.30
0.556±0.012
2.74±0.20
0.108±0.008
0.05
MIN
0.002
3.00
0.118
11.43±0.20
0.450±0.008
MAX
+0.10
0.20
-0.05
+0.004
0.008
-0.002
0.10 MAX
0.004 MAX
Units: millimeter(Inch)
0~8°
13.34
0.525
0.80±0.20
0.031±0.008
32-THIN SMALL OUTLINE PACKAGE TYPE I (0820F)
0.50
0.0197
0~8°
+0.10
0.20
-0.05
+0.004
0.008
-0.002
#16
0.25
TYP
0.010
0.45 ~0.75
0.018 ~0.030
#1
20.00±0.20
0.787±0.008
18.40±0.10
0.724±0.004
#32
0.331
#17
0.15
0.006
0.50
( )
0.020
MAX
8.40
1.00±0.10
0.039±0.004
1.20
MAX
0.047
+0.10
-0.05
+0.004
-0.002
0.25
( )
0.010
8.00
0.315
0.05
MIN
0.002
0.10 MAX
0.004 MAX
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Revision 4.0
January 1997
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