Datasheet KM68257ETGI-15, KM68257ETGI-12, KM68257ETGI-10, KM68257ETG-15, KM68257ETG-10 Datasheet (Samsung)

KM68257E, KM68257EI

CMOS SRAM

PRELIMINARY

Revision 0.0

- 1 -

August 1998

Document Title

32Kx8 Bit High-Speed CMOS Static RAM(5V Operating)
Operated at Commercial and Industrial Temperature Ranges.

Revision History

The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the

right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters
of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.

Rev .No.

Rev. 0.0

Remark

Preliminary

History

Initial Draft

Draft Data

Aug. 1. 1998

KM68257E, KM68257EI

CMOS SRAM

PRELIMINARY

Revision 0.0

- 2 -

August 1998

PIN FUNCTION

Pin Name Pin Function

A0 - A14 Address Inputs

WE Write Enable

CS Chip Select
OE Output Enable

I/O1 ~ I/O8 Data Inputs/Outputs

VCC Power(+5.0V)
VSS Ground

32K x 8 Bit High-Speed CMOS Static RAM

The KM68257E is a 262,144-bit high-speed Static Random
Access Memory organized as 32,768 words by 8 bits. The
KM68257E uses 8 common input and output lines and has an
output enable pin which operates faster than address access
time at read cycle. The device is fabricated using SAMSUNG′s
advanced CMOS process and designed for high-speed circuit
technology. It is particularly well suited for use in high-density
high-speed system applications. The KM68257E is packaged in
a 300mil 28-pin plastic SOJ or TSOP1 forward.

GENERAL DESCRIPTIONFEATURES

• Fast Access Time 10, 12, 15ns(Max.)

• Low Power Dissipation
Standby (TTL) : 20mA(Max.)
(CMOS) : 2mA(Max.)
Operating KM68257E - 10 : 80mA(Max.)
KM68257E - 12 : 80mA(Max.)
KM68257E - 15 : 80mA(Max.)

• Single 5.0V±10% Power Supply

• TTL Compatible Inputs and Outputs

• I/O Compatible with 3.3V Device

• Fully Static Operation

- No Clock or Refresh required

• Three State Outputs

• Standard Pin Configuration
KM68257EJ : 28-SOJ-300
KM68257ETG : 28-TSOP1-0813. 4F

Clk Gen.

A0

I/O1~I/O8

CS

WE

OE

PIN CONFIGURATION(Top View)

FUNCTIONAL BLOCK DIAGRAM

A1
A2
A3
A4
A5
A6
A7
A8

Row Select

Data

Cont.

A9 A10 A11 A12 A13 A14

CLK

Gen.

Pre-Charge-Circuit

Memory Array

512 Rows

64x8 Columns

SOJ

TSOP1

1
2
3
4
5
6
7
8
9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17
16
15

OE
A11

A9
A8

A13
WE
Vcc

A14

A12

A7
A6
A5
A4
A3

A10
CS
I/O8
I/O7
I/O6
I/O5
I/O4
Vss
I/O3
I/O2
I/O1
A0
A1
A2

1
2
3
4
5
6
7
8

9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17
16
15

A14
A12

A7
A6
A5
A4
A3
A2
A1

A0
I/O1
I/O2
I/O3
Vss

Vcc
WE
A13
A8
A9
A11
OE
A10
CS
I/O8
I/O7
I/O6
I/O5
I/O4

Column Select

I/O Circuit

KM68257E -10/12/15 Commercial Temp.
KM68257EI -10/12/15 Industrial Temp.

ORDERING INFORMATION

KM68257E, KM68257EI

CMOS SRAM

PRELIMINARY

Revision 0.0

- 3 -

August 1998

RECOMMENDED DC OPERATING CONDITIONS(TA=0 to 70°C)

NOTE: The above parameters are also guaranteed at industrial temperature range.
* VIL(Min) = -2.0(Pulse Width≤7ns) for I≤20mA

** VIH(Max) = VCC+2.0V(Pulse Width≤7ns) for I≤20mA

Parameter Symbol Min Typ Max Unit

Supply Voltage VCC 4.5 5.0 5.5 V
Ground VSS 0 0 0 V
Input High Voltage VIH 2.2 - VCC+0.5**

V

Input Low Voltage VIL -0.5* - 0.8

V

DC AND OPERATING CHARACTERISTICS(TA=0 to 70°C,VCC=5.0V±10% unless otherwise specified)

NOTE: The above parameters are also guaranteed at industrial temperature range.
* VCC=5.0V, Temp.=25°C

Parameter Symbol Test Conditions

Min Max

Unit

Input Leakage Current ILI VIN = VSS to VCC -1 1 µA
Output Leakage Current ILO CS=VIH or OE=VIH or WE=VIL

VOUT = VSS to VCC

-1 1 µA

Operating Current ICC Min. Cycle, 100% Duty

CS=VIL, VIN = VIH or VIL,
IOUT=0mA

10ns - 80

mA

12ns - 80
15ns - 80

Standby Current ISB Min. Cycle, CS=VIH - 20 mA

ISB1 f=0MHz, CS≥VCC-0.2V,

VIN≥VCC-0.2V or VIN≤0.2V

- 2

mA

Output Low Voltage Level VOL IOL=8mA - 0.4 V
Output High Voltage Level VOH IOH=-4mA 2.4 - V

VOH1* IOH1=0.1mA - 3.95 V

CAPACITANCE*(TA=25°C, f=1.0MHz)

* NOTE : Capacitance is sampled and not 100% tested.

Item Symbol Test Conditions MIN Max Unit

Input/Output Capacitance CI/O VI/O=0V - 8 pF
Input Capacitance CIN

VIN=0V

- 7 pF

ABSOLUTE MAXIMUM RATINGS*

* Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and

functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Parameter Symbol Rating Unit

Voltage on Any Pin Relative to VSS VIN, VOUT -0.5 to 7.0 V
Voltage on VCC Supply Relative to VSS VCC -0.5 to 7.0 V
Power Dissipation PD 1.0

W

Storage Temperature TSTG -65 to 150 °C
Operating Temperature Commercial TA 0 to 70 °C

Industrial TA -40 to 85 °C

KM68257E, KM68257EI

CMOS SRAM

PRELIMINARY

Revision 0.0

- 4 -

August 1998

TEST CONDITIONS

NOTE : The above test conditions are also applied at industrial temperature range.

Parameter Value

Input Pulse Levels 0V to 3V
Input Rise and Fall Times 3ns
Input and Output timing Reference Levels 1.5V
Output Loads See below

AC CHARACTERISTICS(TA=0 to 70°C, VCC=5.0V±10%, unless otherwise noted.)

Output Loads(A) Output Loads(B)

DOUT

5pF*

480Ω

255Ω

for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ

+5.0V

READ CYCLE

NOTE : The above parameters are also guaranteed at industrial temperature range.

Parameter Symbol

KM68257E-10 KM68257E-12 KM68257E-15

Unit

Min Max Min Max Min Max

Read Cycle Time tRC 10 - 12 - 15 - ns
Address Access Time tAA - 10 - 12 - 15 ns
Chip Select to Output tCO - 10 - 12 - 15 ns
Output Enable to Valid Output tOE - 5 - 6 - 7 ns
Chip Enable to Low-Z Output tLZ 3 - 3 - 3 - ns
Output Enable to Low-Z Output tOLZ 0 - 0 - 0 - ns
Chip Disable to High-Z Output tHZ 0 5 0 6 0 7 ns
Output Disable to High-Z Output tOHZ 0 5 0 6 0 7 ns
Output Hold from Address Change tOH 3 - 3 - 3 - ns
Chip Selection to Power Up Time tPU 0 - 0 - 0 - ns
Chip Selection to Power DownTime tPD - 10 - 12 - 15 ns

DOUT

30pF*

480Ω

255Ω

+5V

* Including Scope and Jig Capacitance

KM68257E, KM68257EI

CMOS SRAM

PRELIMINARY

Revision 0.0

- 5 -

August 1998

WRITE CYCLE

NOTE : The above parameters are also guaranteed at industrial temperature range.

Parameter Symbol

KM68257E-10 KM68257E-12 KM68257E-15

Unit

Min Max Min Max Min Max

Write Cycle Time tWC 10 - 12 - 15 -

ns
Chip Select to End of Write tCW 8 - 9 - 10 - ns
Address Setup Time tAS 0 - 0 - 0 - ns
Address Valid to End of Write tAW 8 - 9 - 10 - ns
Write Pulse Width(OE High) tWP 8 - 9 - 10 - ns
Write Pulse Width(OE Low) tWP1 10 - 12 - 15 - ns
Write Recovery Time tWR 0 - 0 - 0 - ns
Write to Output High-Z

tWHZ

0 5 0 6 0 7

ns
Data to Write Time Overlap tDW 5 - 6 - 7 -

ns
Data Hold from Write Time tDH 0 - 0 - 0 -

ns
End Write to Output Low-Z tOW 0 - 0 - 0 - ns

Address

Data Out

Previous Valid Data

Valid Data

TIMMING DIAGRAMS

TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH)

tAA

tRC

tOH

TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)

CS

Address

OE

Data out

tAA

tOLZ

tLZ(4,5)

tOH

tOHZ

tRC

tOE

tCO

tPU tPD

Valid Data

tHZ(3,4,5)

50%

50%

VCC
Current

ICC
ISB

KM68257E, KM68257EI

CMOS SRAM

PRELIMINARY

Revision 0.0

- 6 -

August 1998

TIMING WAVEFORM OF WRITE CYCLE(1) (OE= Clock)

Address

CS

tWP(2)

tDW tDH

Valid Data

WE

Data in

Data out

tWC

tWR(5)

tAW

tCW(3)

High-Z(8)

High-Z

OE

tOHZ(6)

tAS(4)

NOTES(READ CYCLE)

1. WE is high for read cycle.

2. All read cycle timing is referenced from the last valid address to the first transition address.

3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or VOL
levels.

4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to
device.

5. Transition is measured ±200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.

6. Device is continuously selected with CS=VIL.

7. Address valid prior to coincident with CS transition low.

8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.

TIMING WAVEFORM OF WRITE CYCLE(2) (OE=Low Fixed)

Address

CS

tWP1(2)

tDW tDH

tOW

tWHZ(6)

Valid Data

WE

Data in

Data out

tWC

tAS(4)

tWR(5)

tAW

tCW(3)

(10)

(9)

High-Z(8)

High-Z

KM68257E, KM68257EI

CMOS SRAM

PRELIMINARY

Revision 0.0

- 7 -

August 1998

TIMING WAVEFORM OF WRITE CYCLE(3) (CS = Controlled)

Address

CS

tAW

tDW

tDH

Valid Data

WE

Data in

Data out

High-Z

High-Z(8)

tCW(3)

tWP(2)tAS(4)

tWC

tWR(5)

High-Z

High-Z

tLZ

tWHZ(6)

NOTES(WRITE CYCLE)

1. All write cycle timing is referenced from the last valid address to the first transition address.

2. A write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low ;
A write ends at the earliest transition CS going high or WE going high. tWP is measured from the beginning of write to the end
of write.

3. tCW is measured from the later of CS going low to end of write.

4. tAS is measured from the address valid to the beginning of write.

5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.

6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase
of the output must not be applied because bus contention can occur.

7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.

8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state.

9. Dout is the read data of the new address.

10. When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be
applied.

FUNCTIONAL DESCRIPTION

* NOTE : X means Don′t Care.

CS WE OE Mode I/O Pin Supply Current

H X X* Not Select High-Z ISB, ISB1

L H H Output Disable High-Z ICC
L H L Read DOUT ICC
L L X Write DIN ICC

KM68257E, KM68257EI

CMOS SRAM

PRELIMINARY

Revision 0.0

- 8 -

August 1998

PACKAGE DIMENSIONS

Units:millimeters/Inches

#1

28-SOJ-300

#28

18.41 ±0.12

0.725 ±0.005

7.62

0.300

+0.10

MAX

18.82

0.741

0.20

-0.05

+0.004

0.008

-0.002

6.86 ±0.25

0.270 ±0.010

MAX

0.148

3.76

MIN

0.69

0.027

1.30

( )

0.051

1.30

( )

0.051

#14

#15

0.95

( )

0.0375

+0.10

0.43

-0.05

+0.004

0.017

-0.002

+0.10

0.71

-0.05

+0.004

0.028

-0.002

1.27

0.050

0.004

0.10

MAX

8.51 ±0.12

0.335 ±0.005

28-TSOP1-0813.4F

1.00 ±0.10

0.039 ±0.004

MAX

8.40

0.331

0.004 MAX

0.10 MAX

0.50

( )

0.020

11.80 ±0.10

0.465 ±0.004

0.45 ~0.75

0.018 ~0.030

+0.10

0.15

-0.05
+0.004

0.006

-0.002

0~8°

0.425

( )

0.017

MIN

0.05

0.002

MAX

1.20

0.047

8.00

0.315

TYP

0.25

0.010

#28#1

13.40 ±0.20

0.528 ±0.008

#15#14

+0.10

0.20

-0.05
+0.004

0.008

-0.002

0.55

0.0217

Units:millimeters/Inches