Datasheet KM68257CP-20, KM68257CP-15, KM68257CLTG-15, KM68257CLP-15, KM68257CLP-12 Datasheet (Samsung)
...Page 1
PRELIMINARY
KM68257C/CL CMOS SRAM
Document Title
32Kx8 Bit High Speed Static RAM(5V Operating), Evolutionary Pin out.
Operated at Commercial Temperature Range.
Revision History
Rev No.
Rev. 0.0
Rev. 1.0
Rev. 2.0
Rev. 3.0
History
Initial release with Preliminary.
Release to final Data Sheet.
1. Delete Preliminary
Update A.C parameters
2.1. Updated A.C parameters
Items
tOE - / 8/10ns - / 7 /9 ns
tCW - /12/ - ns - /11/ - ns
tHZ 8/10/10ns 6/7/8ns
tOHZ - / 8 / - ns - / 7 / - ns
tDW - / 9 / - ns - / 8 / - ns
2.2. Add Voh1=3.95V with the test condition as Vcc=5V±5% at 25°C
3.1. Add 28-TSOP1 Package.
3.2. Add L-version.
3.3. Add Data Rentention Characteristics.
Previous spec.
(12/15/20ns part)
Updated spec.
(12/15/20ns part)
Draft Data
Apr. 1st, 1994
May 14th,1994
Oct. 4th, 1994
Feb. 22th, 1996
Remark
Preliminary
Final
Final
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this
device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
- 1 -
Rev 3.0
February-1996
Page 2
PRELIMINARY
KM68257C/CL CMOS SRAM
32K x 8 Bit High-Speed CMOS Static RAM
FEATURES
¡Ü
Fast Access Time 12, 15, 20§À(Max.)
¡Ü
Low Power Dissipation
Standby (TTL) : 40§Ì(Max.)
(CMOS) : 2§Ì(Max.)
0.1§Ì(Max.)- L-ver. only
Operating KM68257C/CL - 12 : 165§Ì(Max.)
KM68257C/CL - 15 : 150§Ì(Max.)
KM68257C/CL - 20 : 140§Ì(Max.)
¡Ü
Single 5.0V±10% Power Supply
¡Ü
TTL Compatible Inputs and Outputs
¡Ü
I/O Compatible with 3.3V Device
¡Ü
Fully Static Operation
- No Clock or Refresh required
¡Ü
Three State Outputs
¡Ü
Low Data Retention Voltage : 2V(Min.)- L-ver. only
¡Ü
Standard Pin Configuration
KM68257C/CLP : 28-DIP-300
KM68257C/CLJ : 28-SOJ-300
KM68257C/CLTG : 28-TSOP1-0813, 4F
FUNCTIONAL BLOCK DIAGRAM
Clk Gen.
Pre-Charge-Circuit
GENERAL DESCRIPTION
The KM68257C is a 262,144-bit high-speed Static Random
Access Memory organized as 32,768 words by 8 bits. The
KM68257C uses 8 common input and output lines and has an
output enable pin which operates faster than address access
time at read cycle. The device is fabricated using SAMSUNG's
advanced CMOS process and designed for high-speed circuit
technology. It is particularly well suited for use in high-density
high-speed system applications. The KM68257C is packaged in
a 300 mil 28-pin plastic DIP, SOJ or TSOP1 forward.
PIN CONFIGURATION(Top View)
OE
A11
A9
A8
A13
WE
Vcc
A14
A12
A7
A6
A5
A4
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
TSOP1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A10
CS
I/O8
I/O7
I/O6
I/O5
I/O4
Vss
I/O3
I/O2
I/O1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A12
A13
A14
I/O1 ~ I/O8
CS
WE
OE
Data
Cont.
CLK
Gen.
Memory Array
512 Rows
64x8 Columns
Row Select
I/O Circuit
Column Select
A0 A1 A2 A9 A10 A11
1
A14
2
A12
3
A7
4
A6
5
A5
6
A4
7
A3
A2
A1
A0
I/O1
I/O2
I/O3
Vss
8
9
10
11
12
13
14
SOJ/DIP
PIN FUNCTION
Pin Name Pin Function
A0 - A14 Address Inputs
WE Write Enable
CS Chip Select
OE Output Enable
I/O1 ~ I/O8 Data Inputs/Outputs
VCC Power(+5.0V)
VSS Ground
28
Vcc
27
WE
26
A13
25
A8
24
A9
23
A11
22
OE
21
A10
20
CS
19
I/O8
18
I/O7
17
I/O6
16
I/O5
15
I/O4
- 2 -
Rev 3.0
February-1996
Page 3
PRELIMINARY
KM68257C/CL CMOS SRAM
ABSOLUTE MAXIMUM RATINGS*
Parameter Symbol Rating Unit
Voltage on Any Pin Relative to VSS VIN, VOUT -0.5 to 7.0 V
Voltage on VCC Supply Relative to VSS VCC -0.5 to 7.0 V
Power Dissipation PD 1.0
Storage Temperature TSTG -65 to 150 °C
Operating Temperature TA
* Stresses greater than those listed under "Absolute Maximum Rating" may cause permanent damage to the device. This is a stress ra ting only and func-
tional operation of the device at these at these or any other conditions above those indicated in the operating sections of thi s specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
0 to 70
RECOMMENDED DC OPERATING CONDITIONS(TA=0 to 70°C)
Parameter Symbol Min Typ Max Unit
Supply Voltage VCC 4.5 5.0 5.5 V
Ground VSS 0 0 0 V
Input Low Voltage VIH 2.2 - VCC+0.5** V
Input Low Voltage VIL -0.5* - 0.8 V
W
°C
* VIL(Min) = -2.0(Pulse Width≤10ns) for I≤20§Ì
** VIH(Max) = VCC+2.0V(Pulse Width ≤10ns) for I≤20
§Ì
DC AND OPERATING CHARACTERISTICS(TA=0 to 70°C,VCC=5.0V±10% unless otherwise specified)
Parameter Symbol Test Conditions Min Max Unit
Input Leakage Current ILI VIN = VSS to VCC -2 2
Output Leakage Current ILO
Operating Current ICC
ISB Min. Cycle, CS=VIH - 40
Standby Current
Output Low Voltage Level VOL IOL=8mA - 0.4 V
Output High Voltage Level
* VCC=5.0V±5% Temp.=25°C
ISB1
VOH IOH=-4mA 2.4 - V
VOH1* IOH1=0.1mA - 3.95 V
CS=VIH or OE=VIH or WE=VIL
VOUT = VSS to VCC
Min. Cycle, 100% Duty
CS=VIL, VIN = VIH or VIL,
IOUT=0mA
f=0MHz, CS≥VCC-0.2V,
VIN≥VCC-0.2V or VIN≤0.2V
-2 2
12ns - 165
15ns - 150
20ns - 140
Normal - 2
L-ver - 0.1
µA
µA
§Ì
§Ì
§Ì
CAPACITANCE*(TA =25°C, f=1.0MHz)
Item Symbol Test Conditions MIN Max Unit
Input/Output Capacitance CI/O VI/O=0V - 8 pF
Input Capacitance CIN
* NOTE : Capacitance is sampled and not 100% tested.
VIN=0V
- 3 -
- 7 pF
February-1996
Rev 3.0
Page 4
PRELIMINARY
KM68257C/CL CMOS SRAM
AC CHARACTERISTICS(TA=0 to 70°C, VCC=5.0V±10%, unless otherwise noted.)
TEST CONDITIONS
Parameter Value
Input Pulse Levels 0V to 3V
Input Rise and Fall Times
Input and Output timing Reference Levels 1.5V
Output Loads See below
Output Loads(A) Output Loads(B)
for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ
+5V
§À
3
+5.0V
DOUT
255Ω
480Ω
30pF*
DOUT
255Ω
* Including Scope and Jig Capacitance
480Ω
5pF*
READ CYCLE
Parameter Symbol
Read Cycle Time tRC 12 - 15 - 20 - §À
Address Access Time tAA - 12 - 15 - 20
Chip Select to Output tCO - 12 - 15 - 20
Output Enable to Valid Output tOE - 6 - 7 - 9
Chip Enable to Low-Z Output Access
tLZ 3 - 3 - 3 - §À
KM68257C/CL-12 KM68257C/CL-15 KM68257C/CL-20
Min Max Min Max Min Max
Unit
§À
§À
§À
Output Enable to Low-Z Output tOLZ 0 - 0 - 0 - §À
Chip Disable to High-Z Output tHZ 0 6 0 7 0 10 §À
Output Disable to High-Z Output
Output Hold from Address Change tOH 3 - 3 - 3 Chip Selection to Power Up Time tPU 0 - 0 - 0 Chip Selection to Power DownTime tPD - 12 - 15 - 20
tOHZ
0 6 0 7 0 10 §À
§À
§À
§À
- 4 -
Rev 3.0
February-1996
Page 5
PRELIMINARY
KM68257C/CL CMOS SRAM
WRITE CYCLE
Parameter Symbol
Write Cycle Time tWC 12 - 15 - 20 Chip Select to End of Write tCW 9 - 11 - 13 - §À
Address Setup Time tAS 0 - 0 - 0 - §À
Address Valid to End of Write tAW 9 - 12 - 13 - §À
Write Pulse Width(OE High) tWP 9 - 12 - 13 - §À
Write Pulse Width(OE Low) tWP1 12 - 15 - 20 Write Recovery Time tWR 0 - 0 - 0 Write to Output High-Z
Data to Write Time Overlap tDW 7 - 8 - 10 - §À
Data Hold from Write Time tDH 0 - 0 - 0 - §À
End Write to Output Low-Z tOW 0 - 0 - 0 - §À
tWHZ
KM68257C/CL-12 KM68257C/CL-15 KM68257C/CL-20
Min Max Min Max Min Max
0 6 0 8 0 8
Unit
§À
§À
§À
§À
TIMING DIAGRAMS
TIMING WAVE FORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH)
tRC
ADD
tAA
Data Out
tOH
Previous Data Valid Data Valid
- 5 -
Rev 3.0
February-1996
Page 6
PRELIMINARY
KM68257C/CL CMOS SRAM
TIMING WAVE FORM OF READ CYCLE(2) (WE=VIH)
tRC
ADD
tAA
tCO
CS
tOE
OE
tOLZ
tLZ(4,5)
Data Out
Vcc
Current
NOTES (READ CYCLE)
1. WE is high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to V OH or VOL Levels.
4. At any given temperature and voltage condition, t HZ(Max.) is less than tLZ (Min.) both for a given device and from device to device.
5. Transition is measured ±200§Æ from steady state voltage with Load(B). This parameter is sampled and not 100% tested.
6. Device is continuously selected with CS=VIL.
7. Address valid prior to coincident with CS transition low.
8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycl e.
Icc
ISB
tPU
50% 50%
Data Valid
tHZ(3,4,5)
tOHZ
tOH
tPD
TIMING WAVE FORM OF WRITE CYCLE(1) (OE=Clock)
ADD
OE
CS
tAS(4)
WE
Data In
Data Out
High-Z
tOHZ(6)
tAW
tWC
tCW(3)
tWP(2)
tDW
Data Valid
tWR(5)
tDH
High-Z(8)
- 6 -
Rev 3.0
February-1996
Page 7
PRELIMINARY
KM68257C/CL CMOS SRAM
TIMING WAVE FORM OF WRITE CYCLE(2) (OE=Low Fixed)
tWC
ADD
CS
tAS(4)
WE
Data In
Data Out
High-Z
tWHZ(6)
TIMING WAVE FORM OF WRITE CYCLE(3) (CS=Controlled)
tAW
tCW(3)
tWP1(2)
tDW
Data Valid
High-Z(8)
tWR(5)
tDH
tOW
tOH
(10) (9)
ADD
CS
WE
Data In
Data Out
High-Z
tAS(4)
tLZ
tAW
tWHZ(6)
tWC
tCW(3)
tWP(2)
tDW
Data Valid
tWR(5)
tDH
High-Z
High-Z(8)High-Z
- 7 -
Rev 3.0
February-1996
Page 8
PRELIMINARY
KM68257C/CL CMOS SRAM
NOTES (WRITE CYCLE)
1. All write cycle timing is referenced from the last valid address to the first transition address.
2. A write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low ; A write ends at the earliest transition CS going high or WE going high. tWP is measured from the beginning of write to the end of write.
3. tCW is measured from the later of CS going low to end of write.
4. tAS is measured from the address valid to the beginning of write.
5. tWR is measured from the end of write to the address change. t WR applied in case a write ends as CS or WE going high.
6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the output mus t not
be applied because bus contention can occur.
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycl e.
8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state.
9. Dout is the read data of the new address.
10. When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied.
FUNCTIONAL DESCRIPTION
CS WE OE Mode I/O Pin Supply Current
H X X* Not Select High-Z ISB, ISB1
L H H Output Disable High-Z ICC
L H L Read DOUT ICC
L L X Write DIN ICC
* NOTE : X means Don't Care.
DATA RETENTION CHARACTERISTICS*(TA = 0 to 70°C)
Parameter Symbol Test Condition Min. Typ. Max. Unit
VCC for Data Retention VDR
Data Retention Current IDR
Data Retention Set-Up Time tSDR
Recovery Time tRDR 5 - - ms
* L-Ver only.
CS≥VCC - 0.2V
VCC = 3.0V, CS≥VCC - 0.2V
VIN≥VCC - 0.2V or VIN≤0.2V
See Data Retention
Wave form(below)
2.0 - 5.5 V
- - 0.07 §Ì
0 - - ns
DATA RETENTION WAVE FORM(CS Controlled)
VCC
4.5V
2.2V
VDR
tSDR
Data Retention Mode
tRDR
CS
GND
CS≥VCC - 0.2V
- 8 -
Rev 3.0
February-1996
Page 9
PRELIMINARY
KM68257C/CL CMOS SRAM
PACKAGE DIMENSIONS
28-DIP-300
7.01±0.20
0.276±0.008
0.65
( )
0.025
#28
#1
34.69
1.366
34.29±0.20
1.350±0.008
0.46±0.10
0.018±0.004
1.27±0.10
0.050±0.004
MAX
2.54
0.100
#15
#14
7.62
0.300
3.81±0.20
0.150±0.008
0.51
MIN
0.020
Units : Inches (millimeters)
¡É
0~15
5.08
MAX
0.200
+0.30
3.18
-0.25
+0.012
0.125
-0.010
0.25
0.010
+0.10
-0.05
+0.004
-0.002
28-SOJ-300
8.51±0.12
0.335±0.005
0.95
( )
0.0375
#28
#1
0.43
0.017
+0.10
-0.05
+0.004
-0.002
18.82
MAX
0.741
18.41±0.12
0.725±0.005
1.27
0.050
0.71
0.028
+0.10
-0.05
+0.004
-0.002
#15
#14
1.30
( )
0.051
1.30
( )
0.051
3.76
0.148
MAX
6.86±0.25
0.270±0.010
0.20
0.008
+0.10
-0.05
+0.004
-0.002
7.62
0.300
0.69
MIN
0.027
MAX
0.10
0.004
- 9 -
Rev 3.0
February-1996
Page 10
PRELIMINARY
KM68257C/CL CMOS SRAM
PACKAGE DIMENSIONS
PACKAGE DIMENSIONS
28-TSOP1-0813.4F
+0.10
0.20
-0.05
+0.004
0.008
-0.002
#1
0.55
0.0217
0.25
TYP
0.010
¡É
0~8
0.45 ~0.75
0.018 ~0.030
13.40±0.20
0.528±0.008
11.80±0.10
0.465±0.004
#28
#15#14
0.15
0.006
0.50
( )
0.020
+0.10
-0.05
+0.004
-0.002
MAX
8.40
0.331
1.00±0.10
0.039±0.004
1.20
0.047
Units : Inches (millimeters)
1.10 MAX
0.004 MAX
0.425
( )
0.017
8.00
0.315
0.05
MIN
0.002
MAX
- 10
Rev 3.0
February-1996
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