Datasheet KM6264BLP-7L, KM6264BLP-7, KM6264BLP-10L, KM6264BLP-10, KM6264BLGI-10L Datasheet (Samsung)

KM6264B Family

8Kx8 bit Low Power CMOS Static RAM

FEATURE SUMMARY GENERAL DESCRIPTION

CMOS SRAM

• Process Technology : CMOS

• Organization : 8K x 8

• Power Supply Voltage : Single 5V ± 10%

• Low Data Retention Voltage : 2V(Min)

• Three state output and TTL Compatible

• Package Type : JEDEC Standard

28-DIP, 28-SOP

PRODUCT FAMILY

Product

Family

KM6264BL
KM6264BL-L
KM6264BLE
KM6264BLE-L
KM6264BLI
KM6264BLI-L

* measured with 30pF test load

Operating

Temperature

Commercial
(0~70 °C)
Extended
(-25~-85 °C)
Industrial
(-40~85 °C)

70/100/120ns

100*ns

100*ns

PIN DESCRIPTION

The KM6264B family is fabricated by SAMSUNG's
advanced CMOS process technology. The family
can support various operating temperature ranges
and has various package types for user flexibility of
system design. The family also support low data
retention voltage for battery back-up operations with
low data retention current.

PKG TypeSpeed

Standby(Isb1, Max)

Power Dissipation

Operating(Icc2)

100uA

28-DIP, 28-SOP

28-SOP

10uA

100uA

50uA

55mA

100uA

28-SOP

50uA

FUNCTIONAL BLOCK DIAGRAM

N.C
A12

I/O1
I/O2
I/O3

Vss

A7
A6
A5
A4
A3
A2
A1
A0

1
2
3
4
5
6
7

28-Pin DIP

8

28-Pin SOP

9
10
11
12
13
14

ELECTRONICS

Y-Decoder

Vcc

28

/WE

27

CS2

26

A8

25

A9

24

A11

23

/OE

22

A10

21

/CS1

20

I/O8

19

I/O7

18

I/O6

17

I/O5

16

I/O4

15

A0~A12

1

X-Decoder

I/O1~8

Pin Name

A0~A12
/WE
/CS1, CS2
/OE
I/O1~I/O8
Vcc
Vss
N.C

Cell Array

I/O Buffer

Function

Address Inputs
Write Enable Input
Chip Select Input
Output Enable Input
Data Input/Output
Power(5V)
Ground
No Connection

Control Logic

/CS1, CS2
/WE, /OE

Revision. 0.0

Auust. 1996

KM6264B Family

PRODUCT LIST & ORDERING INFORMATION

PRODUCT LIST

Commercial Temp Products

(0~70 °C)

Extended Temp Products

(-25~85 °C)

CMOS SRAM

Industrial Temp Products

(-40~85 °C)

Part Name

KM6264BLP-7
KM6264BLP-7L
KM6264BLP-10
KM6264BLP-10L
KM6264BLP-12
KM6264BLP-12L
KM6264BLG-7
KM6264BLG-7L
KM6264BLG-10
KM6264BLG-10L
KM6264BLG-12
KM6264BLG-12L

Function

28-DIP, 70ns, L-pwr
28-DIP, 70ns, , LL-pwr
28-DIP, 100ns, , L-pwr
28-DIP, 100ns, LL-pwr
28-DIP, 120ns, , L-pwr
28-DIP, 120ns, LL-pwr
28-SOP, 70ns, L-pwr
28-SOP, 70ns, LL-pwr
28-SOP, 100ns, L-pwr
28-SOP, 100ns, LL-pwr
28-SOP, 120ns, L-pwr
28-SOP, 120ns, LL-pwr

ORDERING INFORMATION

K M6 2 X 64 B X X XX - XX X

Part Name Function

KM6264BLGE-10
KM6264BLGE-10L

Function

28-SOP, 100ns, L-pwr
28-SOP, 100ns, LL-pwr

Part Name

KM6264BLGI-10
KM6264BLGI-10L

28-SOP, 100ns, L-pwr
28-SOP, 100ns, LL-pwr

ELECTRONICS

L-Low Low Power, Blank-Low Power or High Power

Access Time : 7=70ns, 10=100ns, 12=120ns
Operating Temperature :

I=Industrial, E=Extended, Blank=Commercial
Package Type : G=SOP, P=DIP,

L-Low Power or Low Low Power, Blank-High Power

Die Version : B=3rd generation
Density : 64=64K bit
Blank=5V

Organization : 2= x8
SEC Standard SRAM

2

Revision. 0.0

Auust. 1996

KM6264B Family

ABSOLUTE MAXIMUM RATINGS *

CMOS SRAM

Item Ratings

Voltage on any pin relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
Storage temperature
Operating Temperature

Symbol

Vin, Vout
Vcc
Pd
Tstg
Ta

-0.5 to Vcc+0.5

-0.5 to 7.0

1.0

-65 to 150
0 to 70

-25 to 85

-40 to 85

Soldering temperature and time

* Stresses greater than those listed under 'Absolute Maximum Ratings' may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operating section of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Tsolder

260 °C, 10sec(Lead Only)

Unit

V
V

W

°C

°C
°C
°C

-

Remark

-

-

-

-

KM6264BL/L-L

KM6264BLE/LE-L

KM6264BLI/LI-L

-

RECOMMENDED DC OPERATING CONDITIONS*

Item

Supply voltage
Ground
Input high voltage
Input low voltage

* 1) Commercial Product : Ta=0 to 70 ° C, unless otherwise specified

2) Extended Product : Ta=-25 to 85 ° C, unless otherwise specified

3) Industrial Product : Ta=-40 to 85 ° C, unless otherwise specified
** Ta=25 °C
*** Vil(min)=-3.0V for ¡Â50ns pulse

Symbol

Vcc
Vss

Vih

Vil

Min

4.5
0

2.2

-0.5***

Typ**

5.0
0

-

-

Max

5.5
0

Vcc+0.5

0.8

Unit

V
V
V
V

CAPACITANCE * (f=1MHz, Ta=25 °C)

Item

Symbol

Input capacitance
Input/Output capacitance

* Capacitance is sampled not 100% tested

ELECTRONICS

Cin
Cio

Test Condition

Vin=0V
Vio=0V

Min

-

-

3

Max

6
8

Unit

pF
pF

Revision. 0.0

Auust. 1996

KM6264B Family

DC AND OPERATING CHARACTERISTICS

CMOS SRAM

Item

Input leakage current
Output leakage current

Operating power supply current
Average operating current

Output low voltage
Output high voltage
Standby Current(TTL)
Standby
Current
(CMOS)

KM6264BL
KM6264BL-L
KM6264BLE
KM6264BLE-L
KM6264BLI
KM6264BLI-L

Symbol

Ili

Ilo

Icc

Icc1

Icc2

Vol

Voh

Isb

Isb1

Test Conditions*

Vin=Vss to Vcc
/CS1=Vih or CS2=Vil or /WE=Vil
Vi/o=Vss to Vcc
/CS1=Vil, CS2=Vih
Vin=Vil or Vih, Ii/o=0mA
Cycle time=1us, 100% duty
/CS1¡Â0.2V, CS2 ¡ÃVcc-0.2V
Min cycle, 100% duty
/CS1=Vil, CS2=Vih, Ii/o=0mA
Iol=2.1mA
Ioh= -1.0mA
/CS1=Vih or CS2=Vil
/CS1¡ÃVcc-0.2V
CS2¡ÃVcc-0.2V or
CS2 ¡Â0.2V
Others 0~Vcc

L
LL
L
LL
L
LL

Min

-1

-1

-

-

-

-

2.4

-

-

-

-

-

-

-

Typ**

-

-

7

-

-

-

-

­2
1

-

-

-

-

Max

1
1

15
10

55

0.4

-

1

100

10

100

50

100

50

Unit

uA
uA

mA
mA

mA

V
V

mA

uA
uA
uA
uA
uA
uA

* 1) Commercial Product : Ta=0 to 70 ° C, Vcc=5V+/-10%, unless otherwise specified

2) Extended Product : Ta=-25 to 85 ° C, Vcc=5V+/-10%, unless otherwise specified

3) Industrial Product : Ta=-40 to 85 ° C, Vcc=5V+/-10%, unless otherwise specified
** Ta=25 °C

A.C CHARACTERISTICS

TEST CONDITIONS(1. Test Load and Test Input/Output Reference)*

Item

Input pulse level
Input rise fall time
Input and output reference voltage
Output load(See right)

* See test condition of DC and AC Operating characteristics

Value

0.8 to 2.4V
5ns

1.5V
CL=100pF+1TTL

Remark

-

-

-

-

CL*

* Including scope and jig capacitance

ELECTRONICS

4

Revision. 0.0

Auust. 1996

KM6264B Family

TEST CONDITIONS(2. Temperature and Vcc Conditions)

CMOS SRAM

Product Family

KM6264BL/L-L
KM6264BLE/LE-L
KM6264BLI/LI-L

* measured with 30pF test load

Temperature

0~70 °C

-25~85 °C

-40~85 °C

Power Supply(Vcc)

PARAMETER LIST FOR EACH SPEED BIN

Read

Write

Parameter List

Read cycle time
Address access time
Chip select to output
Output enable to valid output
Chip select to low-Z output
Output enable to low-Z output
Chip disable to high-Z output
Output disable to high-Z output
Output hold from address change
Write cycle time
Chip select to end of write
Address set-up time
Address valid to end of write
Write pulse width
Write recovery time
Write to output high-Z
Data to write time overlap
Data hold from write time
End write to output low-Z

Symbol

tRC
tAA

tCO

tOE

tLZ

tOLZ

tHZ

tOHZ

tOH
tWC
tCW

tAS
tAW
tWP
tWR

tWHZ

tDW

tDH

tOW

5V +/- 10%
5V +/- 10%
5V +/- 10%

Min

70

5
5
0

0
10
70
60

0
60
40

0

0
30

0

5

Max

-

70

-

70

-

35

30
30

30

Speed Bins

-

-

-

-

-

-

-

-

-

-

-

-

-

70/100/120ns

Min
100

-

-

-

10

5
0
0

10

100

80

0
80
60

0

0
40

0

5

Speed Bin

100*ns
100*ns

Max

100
100

50

35
35

30

Min

-

120

-

10

-

-

-

-

-

-

-

-

-

-

-

5
0
0

10

120

85

0
85
70

0

0
50

0
10

Comments

Commercial
Extended
Industrial

120ns 70ns 100ns

Max

-

120

-

120

-

60

40
40

30

Units

-

-

-

-

-

-

-

-

-

-

-

-

-

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

ELECTRONICS

5

Revision. 0.0

Auust. 1996

KM6264B Family

DATA RETENTION CHARACTERISTICS

CMOS SRAM

Item

Vcc for data retention
Data retention current

Symbol Test Condition*

Vdr
Idr

KM6264BL
KM6264BL-L

/CS***¡ÃVcc-0.2V
Vcc=3.0V

/CS¡ÃVcc-0.2V
KM6264BLE
KM6264BLE-L
KM6264BLI
KM6264BLI-L

Data retention set-up time
Recovery time

* 1) Commercial Product : Ta=0 to 70 ° C, unless otherwise specified

2) Extended Product : Ta=-25 to 85 ° C, unless otherwise specified

3) Industrial Product : Ta=-40 to 85 ° C, unless otherwise specified
** Ta=25 °C
*** /CS1¡ÃVcc-0.2, CS2¡ÃVcc-0.2(/CS1 Controlled) or CS2 ¡Ã0.2(CS2 Controlled)

tSDR
tRDR

See data retention

waveform

DATA RETENTION TIMING DIAGRAM

1) /CS1 controlled

Vcc

tSDR tRDRData retention mode

L-Ver
LL-Ver
L-Ver
LL-Ver
L-Ver
LL-Ver

Min

2.0

-

-

-

-

-

­0
5

Typ**

-

1

0.5

-

-

-

-

-

-

Max

5.5
50

5
50
25
50
25

-

-

Unit

V

uA

ms

4.5V

2.2V
Vdr

/CS1
GND

2) CS2 controlled

Vcc

4.5V

CS2
Vdr

0.4V
GND

tSDR

/CS1¡ÃVcc-0.2V

Data retention mode

tRDR

CS2¡Â0.2V

ELECTRONICS

6

Revision. 0.0

Auust. 1996

KM6264B Family

TIMING DIAGRAMS

TIMING WAVEFORM OF READ CYCLE (1) (Address Controlled)

(/CS=/OE=Vil, CS2=/WE=Vih)

tRC

Address

CMOS SRAM

tAA

Data Out

OH

t

Previous Data Valid Data Valid

TIMING WAVEFORM OF READ CYCLE(2) (/WE= VIH)

t

RC

Address

t

AA

tCO1

/CS1

CS2

/OE

Data out Data Vailid

High - Z

tCO2

t

OE

t

OLZ

t

LZ

t

OH

tHZ(1,2)

t

HZ

tOHZ

Notes(Read Cycle)

1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not
referenced to output voltage levels.

2. At any given temperature and voltage condition, tHZ(Max) is less than tLZ(Min) both for a given device and
device to device interconnection.

7

ELECTRONICS

Revision. 0.0

Auust. 1996

KM6264B Family

TIMING WAVEFORM OF WRITE CYCLE(1) (/WE Controlled)

t

Address

WC

CMOS SRAM

t

CW(2)

/CS

t

AW

CS2

tCW(2)

t

WP(1)

/WE

t

AS

Data in

t

WHZ

Data out

Data Undefined

TIMING WAVEFORM OF WRITE CYCLE(2) (/CS1 Controlled)

t

WC

Address

t

AS

t

CW(2)

t

DW

Data Vailid

t

WR1(4)

t

DH

t

OW

t

WR1(4)

/CS1

CS2

/WE

Data in

Data out

ELECTRONICS

t

AW

tCO2

t

WP(1)

t

t

DW

DH

Data Vailid

High - Z High - Z

8

Revision. 0.0

Auust. 1996

KM6264B Family

TIMING WAVEFORM OF WRITE CYCLE(3) (CS2 Controlled)

t

WC

Address

t

tAS(3)

/CS1

CW(2)

t

AW

CMOS SRAM

t

WR2(4)

CS2

/WE

Data in

Data out

Notes(Write Cycle)

1. A write occurs during the overlap of a low /CS1, a high CS2 and a low /WE. A write begins at the latest transition
among /CS1 going low, CS2 going high and /WE going low. A write ends at the earliest transition among /CS1 going
high, CS2 going low and /WE going high, tWP is measured from the beginning of write to the end of write.

2. tCW is measured from the later of /CS1 going low or CS2 going high to the end of write.

3. tAS is measured from the address valid to the beginning of write.

4. tWR is measured from the end of write to the address change. tWR1 applied in case a write ends at /CS1, or /WE
going high, tWR2 applied in case a write ends at CS2 going to low.

High - Z High - Z

t

CW(2)

t

WP(1)

t

DW

Data Vailid

t

DH

FUNCTIONAL DESCRIPTION

/CS1

H
X

L
L
L

CS2

X
L
H
H
H

* X means don't care

ELECTRONICS

/WE

X
X
H
H
L

/OE

X
X
H
L
X

Mode

Power Down

Power Down

Output Disable

Read
Write

9

I/O Pin

High-Z
High-Z
High-Z

Dout

Din

Current Mode

Isb, Isb1

Isb, Isb1

Icc
Icc
Icc

Revision. 0.0

Auust. 1996

KM6264B Family

CMOS SRAM

PACKAGE DIMENSION

28 PIN PLASTIC SMALL OUTLINE PACKAGE (450mil )

0.89

0.035

#28

#1 #14

1.27

18.69

0.736

MAX

0.050

18.29 ± 0.20

0.720± 0.008

#15

0.41 ± 0.10

0.016 ± 0.004

8.38 ± 0.20

0.330 ± 0.008

2.59 ± 0.20

0.102 ± 0.008

3.00

MAX

0.118

0.05

0.002

MIN

0.10

0.004

MAX

0 ~ 8°

Unit : Millimeters (Inches)

1.02 ± 0.20

0.040± 0.008

11.81 ± 0.30

0.465 ± 0.012

+ 0.10

0.15

- 0.05

+ 0.004

0.006

- 0.002

28 PIN PLASTIC DUAL INLINE PACKAGE (600mil)

36.72

MAX

1.446

1.65

0.065

#28

#1

2.54

0.100

36.32 ± 0.20

1.430 ± 0.008

0.46 ± 0.10

0.018 ± 0.004

1.52 ± 0.10

0.060 ± 0.004

#15

#14

13.60 ± 0.20

0.535 ± 0.008

3.81 ± 0.20

0.150 ± 0.008

5.08

0.200

3.30 ± 0.30

0.130 ± 0.012

0.38

MIN

0.015

MAX

0.25

0.010

0 ~ 15°

15.24

0.600

+ 0.10

- 0.05
+ 0.004

- 0.002

ELECTRONICS

10

Revision. 0.0

Auust. 1996