Datasheet KM62256CLP-5L, KM62256CLP-5, KM62256CLGI-7L, KM62256CLGI-7, KM62256CLGE-7L Datasheet (Samsung)

KM62256C Family CMOS SRAM

Document Title

32Kx8 bit Low Power CMOS Static RAM

Revision History

Revision No

0.0

0.1

1.0

2.0

3.0

4.0

History

Advance information

Initial draft

Finalize

Revise

- Add 45ns part with 30pF test load

Revise

- Change specification format and merge :
Commercial, Extended, Industrial product in same datasheets.

Revise

- Change Speed bin
Erase 45ns part from commercial product and 100ns from

extended and industrial product.

- Production change
Erase Low power product from TSOP package

Draft Data

February 12th 1993

November 2nd 1993

September 24th 1994

August 12th 1995

April 15th 1996

December 19 1997

Remark

Design target

Preliminary

Final

Final

Final

Final

The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right

to change the specifications and product. SAMSUNG Electronics will evaluate and reply to your requests and questions about
device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.

1

Revision 4.0

December 1997

KM62256C Family CMOS SRAM

32Kx8 bit Low Power CMOS Static RAM

GENERAL DESCRIPTIONFEATURES

• Process Technology : 0.7µm CMOS

• Organization : 32Kx8

• Power Supply Voltage : Single 5V±10%

• Low Data Retention Voltage : 2V(Min)

• Three state output and TTL Compatible

• Package Type : 28-DIP-600, 28-SOP-450,

28-TSOP1 -0813.4F/R

PRODUCT FAMILY

Product Family Operating Temperature. Speed(ns) PKG Type

KM62256CL
KM62256CL-L 20µA
KM62256CLE
KM62256CLE-L 50µA
KM62256CLI
KM62256CLI-L 50µA

Commercial (0~70°C) 55/70ns

Extended (-25~85°C) 70ns

Industrial (-40~85°C) 70ns

The KM62256C family is fabricated by SAMSUNG′s advanced
CMOS process technology. The family supports various operat­ing temperature ranges and has various package types for user
flexibility of system design. The family also support low data
retention voltage for battery back-up operation with low data
retention current.

Power Dissipation

28-DIP, 28-SOP

Standby

(ISB1, Max)

100µA

Operating

(Icc2)

28-TSOP I R/F
28-SOP

28-TSOP I R/F
28-SOP

100µA

100µA

70mA

28-TSOP I R/F

PIN DESCRIPTION

1

OE

2

A11

3

A9

4

A14
A12

I/O1
I/O2
I/O3

VSS

A7
A6
A5
A4
A3
A2
A1
A0

1
2
3
4
5
6

28-DIP

7

28-SOP

8
9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17
16
15

VCC
WE
A13
A8
A9
A11
OE
A10
CS
I/O8
I/O7
I/O6
I/O5
I/O4

A13

VCC

A14
A12

A12
A14

VCC

A13

A11

WE

WE

A8

5
6
7
8
9
10

A7

11

A6

12

A5

13

A4

14

A3

14

A3

13

A4

12

A5

11

A6
A7

10
9
8
7
6
5

A8

4

A9

3
2
1

OE

NameName Function

A0~A14 Address Inputs

WE Write Enable Input

CS Chip Select Input
OE Output Enable Input

I/O1~I/O8 Data Inputs/Outputs

Vcc Power(5V)

Vss Ground

28-TSOP

Type I - Forward

28-TSOP

Type I - Reverse

FUNCTIONAL BLOCK DIAGRAM

A10

28
27

CS
I/O8

26
25

I/O7

24

I/O6
I/O5

23
22

I/O4
VSS

21
20

I/O3

19

I/O2
I/O1

18
17

A0
A1

16
15

A2

15

A2

16

A1

17

A0

18

I/O1

19

I/O2

20

I/O3

21

VSS

22

I/O4

23

I/O5

24

I/O6

25

I/O7

26

I/O8

27

CS

28

A10

A3
A4
A5
A6
A7
A8
A12
A13
A14

I/O1
I/O8

CS

Control

WE

Logic

OE

Clk gen.

Row
select

Data
cont

Data
cont

Precharge circuit.

Memory array
512 rows
64×8 columns

I/O Circuit

Column select

A0 A1 A2 A9 A10 A11

SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.

2

Revision 4.0

December 1997

KM62256C Family CMOS SRAM

PRODUCT LIST

Commercial Temp Product

(0~70°C)

Part Name Function Part Name Function Part Name Function

KM62256CLP-5
KM62256CLP-5L
KM62256CLP-7
KM62256CLP-7L
KM62256CLG-5
KM62256CLG-5L
KM62256CLG-7
KM62256CLG-7L
KM62256CLTG-5L
KM62256CLTG-7L
KM62256CLRG-5L
KM62256CLRG-7L

Note : LL means Low Low standby current.

28-DIP, 55ns, L-pwr
28-DIP, 55ns, LL-pwr
28-DIP, 70ns, L-pwr
28-DIP, 70ns, LL-pwr
28-SOP, 55ns, L-pwr
28-SOP, 55ns, LL-pwr
28-SOP, 70ns, L-pwr
28-SOP, 70ns, LL-pwr
28-TSOP F, 55ns, LL-pwr
28-TSOP F, 70ns, LL-pwr
28-TSOP R, 55ns, LL-pwr
28-TSOP R, 70ns, LL-pwr

KM62256CLGE-7
KM62256CLGE-7L
KM62256CLTGE-7L
KM62256CLRGE-7L

FUNCTIONAL DESCRIPTION

CS OE WE I/O Pin Mode Power

H X X High-Z Deselected Standby
L H H High-Z Output Disabled Active
L L H Dout Read Active
L X L Din Write Active

1. X means don′t care

Extended Temp Products

(-25~85°C)

28-SOP, 70ns, L-pwr
28-SOP, 70ns, LL-pwr
28-TSOP F, 70ns, LL-pwr
28-TSOP R, 70ns, LL-pwr

Industrial Temp Products

KM62256CLGI-7
KM62256CLGI-7L
KM62256CLTGI-7L
KM62256CLRGI-7L

(-40~85°C)

28-SOP, 70ns, L-pwr
28-SOP, 70ns, LL-pwr
28-TSOP F, 70ns, LL-pwr
28-TSOP R, 70ns, LL-pwr

ABSOLUTE MAXIMUM RATINGS

1)

Item Symbol Ratings Unit Remark

Voltage on any pin relative to Vss VIN,VOUT -0.5 to VCC+0.5 V -
Voltage on Vcc supply relative to Vss VCC -0.5 to 7.0 V ­Power Dissipation PD 1.0 W ­Storage temperature TSTG -65 to 150 °C -

0 to 70 °C KM62256CL

Operating Temperature TA

-25 to 85 °C KM62256CLE

-40 to 85 °C KM62256CLI

Soldering temperature and time TSOLDER 260°C, 10sec(Lead Only) - -

1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

3

Revision 4.0

December 1997

KM62256C Family CMOS SRAM

RECOMMENDED DC OPERATING CONDITIONS

Item Symbol Min

1)

Typ

Max Unit

Supply voltage Vcc 4.5 5.0 5.5 V
Ground Vss 0 0 0 V
Input high voltage VIH 2.2 ­Input low voltage VIL

Note

1. Commercial Product : TA=0 to 70°C, unless otherwise specified

Extended Product : TA=-25 to 85°C, unless otherwise specified
Industrial Product : TA=-40 to 85°C, unless otherwise specified

2. Overshoot : VCC+3.0V in case of pulse width ≤30ns

3. Undershoot : -3.0V in case of pulse width≤30ns

4. Overshoot and undershoot is sampled, not 100% tested

CAPACITANCE

1)

(f=1MHz, TA=25°C)

-0.5

3)

Vcc+0.5V

- 0.8 V

2)

V

Item Symbol Test Condition Min Max Unit

Input capacitance CIN VIN=0V - 6 pF
Input/Output capacitance CIO VIO=0V - 8 pF

1. Capacitance is sampled, not 100% tested

DC AND OPERATING CHARACTERISTICS

Item Symbol

Test Conditions

Input leakage current ILI VIN=Vss to Vcc -1 - 1 µA
Output leakage current ILO CS=VIH or WE=VIL, VIO=Vss to Vcc -1 - 1 µA
Operating power supply current ICC IIO=0mA, CS=VIL, VIN=VIH or VIL - 7

Cycle time=1µs, 100% duty, IIO=0mA
CS≤0.2V, VIN≤0.2V, VIN≥Vcc -0.2V

Cycle time=Min,100% duty, IIO=0mA, CS=VIL, VIN=VIH or VIL

Average operating current

ICC1

ICC2
Output low voltage VOL IOL=2.1mA - - 0.4 V
Output high voltage VOH IOH=-1.0mA 2.4 - - V
Standby Current(TTL) ISB CS=VIH, Other inputs=VIH or VIL - -

KM62256CL

KM62256CL-L
Standby Current
(CMOS)

KM62256CLE

KM62256CLE-L

KM62256CLI

KM62256CLI-L

1. 20mA for Extended and Industrial Products

2. 10mA for Extended and Industrial Products

3. 2mA for Extended and Industrial Products

ISB1

CS≥Vcc-0.2V,
Other inputs=0~Vcc

L(Low Power)
LL(L Low Power)--

L(Low Power)
LL(L Low Power)--

L(Low Power)
LL(L Low Power)--

Min Typ Max Unit

1)

15

- -

2)

7

- - 70 mA

3)

1

21100

20

--100
50

--100
50

mA
mA

mA

µA

µA

µA

4

Revision 4.0

December 1997

KM62256C Family CMOS SRAM

AC OPERATING CONDITIONS

TEST CONDITIONS (Test Load and Test Input/Output Reference)

Input pulse level : 0.8 to 2.4V
Input rising and falingl time : 5ns
input and output reference voltage : 1.5V

Output load (See right) :C L=100pF+1TTL

AC CHARACTERISTICS(Vcc=4.5~5.5V, KM62256C Family : TA=0 to 70°C, KM62256CE Family : TA=-25 to 85°C,

KM62256CI Family : TA=-40 to 85°C)

Parameter List Symbol

Read cycle time tRC 55 - 70 - ns
Address access time tAA - 55 - 70 ns
Chip select to output tCO - 55 - 70 ns
Output enable to valid output tOE - 25 - 35 ns

Read

Write

Chip select to low-Z output tLZ 10 - 10 - ns
Output enable to low-Z output tOLZ 5 - 5 - ns
Chip disable to high-Z output tHZ 0 20 0 30 ns
Output disable to high-Z output tOHZ 0 20 0 30 ns
Output hold from address change tOH 5 - 5 - ns
Write cycle time tWC 55 - 70 - ns
Chip select to end of write tCW 45 - 60 - ns
Address set-up time tAS 0 - 0 - ns
Address valid to end of write tAW 45 - 60 - ns
Write pulse width tWP 40 - 50 - ns
Write recovery time tWR 0 - 0 - ns
Write to output high-Z tWHZ 0 20 0 25 ns
Data to write time overlap tDW 25 - 30 - ns
Data hold from write time tDH 0 - 0 - ns
End write to output low-Z tOW 5 - 5 - ns

1)

CL

1. Including scope and jig capacitance

Speed Bins

55ns 70ns

Min Max Min Max

Units

DATA RETENTION CHARACTERISTICS

Item Symbol

Vcc for data retention VDR CS≥Vcc-0.2V 2.0 - 5.5 V

KM62256CL
KM62256CL-L

Data retention current IDR

Data retention set-up time tSDR
Recovery time tRDR 5 - -

KM62256CLE
KM62256CLE-L

KM62256CLI
KM62256CLI-L

Vcc=3.0V
CS≥Vcc-0.2V

See data retention waveform

Test Condition

L-Ver
LL-Ver

L-Ver
LL-Ver

L-Ver
LL-Ver

5

Min

0 - -

Typ

-

-

-

-

-

-

1

0.5

-

-

-

-

Max Unit

50
10

50
25

50
25

Revision 4.0

December 1997

µA

ms

KM62256C Family CMOS SRAM

TIMMING DIAGRAMS

TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH)

tRC

Address

tAA

tCO

tOE

tAA

Data Valid

tRC

tOH

tHZ

tOHZ

Data Valid

tOH

Data Out

Previous Data Valid

TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)

Address

CS

OE

tOLZ

Data out

High-Z

tLZ

NOTES (READ CYCLE)

1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage

levels.

2. At any given temperature and voltage condition, tHZ (Max.) is less than tLZ(Min.) both for a given device and from device to device

interconnection.

6

Revision 4.0

December 1997

KM62256C Family CMOS SRAM

TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)

tWC

Address

CS

tAW

WE

tAS(3)

Data in

tWHZ

Data out

Data Undefined

TIMING WAVEFORM OF WRITE CYCLE(2) (CS Controlled)

Address

tAS(3)

CS

tCW(2)

tWP(1)

tDW tDH

tWC

tCW(2)

tAW

tWP(1)

tWR(4)

Data Valid

tOW

tWR(4)

WE

tDW tDH

Data in

Data out

NOTES (WRITE CYCLE)

1. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition among CS going Low and WE
going low : A write end at the earliest transition among CS going high and WE going high, t WP is measured from the begining of write
to the end of write.

2. tCW is measured from the CS going low to end of write.

3. tAS is measured from the address valid to the beginning of write.

4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.

High-Z

Data Valid

High-Z

DATA RETENTION WAVE FORM

CS controlled

VCC

4.5V

2.2V

VDR

tSDR

Data Retention Mode

tRDR

CS
GND

CS≥VCC - 0.2V

7

Revision 4.0

December 1997

KM62256C Family CMOS SRAM

PACKAGE DIMENSIONS Units :millimeters(inches)

28 PIN DUAL INLINE PACKAGE(600mil)

#28

13.60±0.20

0.535±0.008

#15

15.24

0.600

0.25

0.010

+0.10

-0.05
+0.004

-0.002

#1

36.72

MAX

1.446

36.32±0.20

1.430±0.008

0.46±0.10

1.65

( )

0.065

0.018±0.004

1.52±0.10

0.060±0.004

28 PIN PLASTIC SMALL OUTLINE PACKAGE(450mil)

#28

#15

2.54

0.100

11.81±0.30

0.465±0.012

#14

3.81±0.20

0.150±0.008

0.200

0.38

MIN

0.015

8.38±0.20

0.330±0.008

5.08

MAX

3.30±0.30

0.130±0.012

0~8°

11.43

0~15°

0.450

0.89

( )

0.035

#1 #14

18.69

MAX

0.736

18.29±0.20

0.720±0.008

0.41±0.10

0.016±0.004

1.27

0.050

8

2.59±0.20

0.102±0.008

0.118

0.05

MIN

0.002

3.00

MAX

+0.10

0.15

-0.05
+0.004

0.006

-0.002

0.10 MAX

0.004 MAX

1.02±0.20

0.040±0.008

Revision 4.0

December 1997

KM62256C Family CMOS SRAM

PACKAGE DIMENSIONS

28 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0813.4F)

13.40±0.20

0.528±0.008

0.55

0.0217

0.20

0.008

+0.10

-0.05
+0.004

-0.002
#1

#28

#15#14

MAX

8.40

0.331

1.00±0.10

0.039±0.004

1.20

0.047

Units :millimeters(inches )

0.10 MAX

0.004 MAX

0.425

( )

0.017

8.00

0.315

0.05

MIN

0.002

MAX

28 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0813.4R)

13.40±0.20

0.528±0.008

11.80±0.10

0.465±0.004

0.55

0.0217

0~8°

+0.10

0.20

-0.05
+0.004

0.008

-0.002

0.25

TYP

0.010

0.45 ~0.75

0.018 ~0.030

#1

#15#14

#28

0.15

0.006

0.50

( )

0.020

+0.10

-0.05
+0.004

-0.002

MAX

8.40

0.331

1.00±0.10

0.039±0.004

1.20

0.047

MAX

0.10 MAX

0.004 MAX

0.425

( )

0.017

8.00

0.315

0.05

MIN

0.002

9

Revision 4.0

December 1997