Datasheet KM6164002, KM6164002E, KM6164002I Datasheet (SAMSUNG)

查询KM6164002供应商

PRELIMINARY

KM6164002, KM6164002E, KM6164002I CMOS SRAM

PACKAGE DIMENSIONS

44-SOJ-400

11.18±0.12

0.440±0.005

0.95

( )

0.0375

#44

#1

0.43

0.017

+0.10

-0.05

+0.004

-0.002

28.98

MAX

1.141

25.58±0.12

1.125±0.005

1.27

0.050

0.71

0.028

+0.10

-0.05

+0.004

-0.002

#23

#22

Units : Inches (millimeters)

10.16

0.400

0.69

MIN

0.027

1.19

( )

0.047

3.76
MAX

0.148

1.27

( )

0.050

9.40±0.25

0.370±0.010

0.20

0.008

0.10

MAX

0.004

+0.10

-0.05

+0.004

-0.002

- 9 -

Rev 2.0

June -1997

PRELIMINARY

KM6164002, KM6164002E, KM6164002I CMOS SRAM

TIMING WAVE FORM OF WRITE CYCLE(4) (UB, LB Controlled)

tWC

ADD

tAW

tCW(3)

CS

tBW

UB, LB

tWR(5)

tAS(4)

WE

Data In

Data Out

NOTES (WRITE CYCLE)

1. All write cycle timing is referenced from the last valid address to the first transition address.

2. A write occurs during the overlap of a low CS,WE,LB and UB. A write begins at the latest transition CS going low and WE going low ; A write ends at
the earliest transition CS going high or WE going high. tWP is measured from the beginning of write to the end of write.

3. tCW is measured from the later of CS going low to end of write.

4. tAS is measured from the address valid to the beginning of write.

5. tWR is measured from the end of write to the address change. t WR applied in case a write ends as CS, or WE going high.

6. If OE. CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the output mus t not
be applied because bus contention can occur.

7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycl e.

8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state.

9. Dout is the read data of the new address.

10. When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied.

High-Z

High-Z

tBLZ

tWHZ(6)

tWP(2)

tDW tDH

Data Valid

High-Z(8)

FUNCTIONAL DESCRIPTION

CS WE OE LB UB Mode

H X X* X X Not Select High-Z High-Z ISB, ISB1

L H H X X
L X X H H

L H

L H L

L L X

* NOTE : X means Don't Care.

H L High-Z DOUT

L L DOUT DOUT
L H

H L High-Z DIN

L L DIN DIN

Output Disable High-Z High-Z ICC

Read

Write

- 8 -

I/O1~I/O8 I/O9~I/O16

DOUT High-Z

I/O Pin

DIN High-Z

Supply Current

ICC

ICC

Rev 2.0

June -1997

PRELIMINARY

KM6164002, KM6164002E, KM6164002I CMOS SRAM

TIMING WAVE FORM OF WRITE CYCLE(2) (OE=Low Fixed)

tWC

ADD

CS

UB, LB

tAS(4)

WE

Data In

Data Out

High-Z

TIMING WAVE FORM OF WRITE CYCLE(3) (CS=Controlled)

tAW

tWHZ(6)

tCW(3)

tBW

tWP1(2)

High-Z

tWR(5)

tDW tDH

Data Valid

tOW

tOH

(10) (9)

ADD

CS

UB, LB

WE

Data In

Data Out

High-Z

High-Z

tAS(4)

tLZ

tAW

tWHZ(6)

tWC

tCW(3)

tBW

tWP(2)

tDW

Data Valid

tWR(5)

tDH

High-Z(8)

- 7 -

Rev 2.0

June -1997

PRELIMINARY

KM6164002, KM6164002E, KM6164002I CMOS SRAM

TIMING WAVE FORM OF READ CYCLE(2) (WE=VIH)

tRC

ADD

tAA

tCO

CS

tBA

UB, LB

tBLZ(4,5)

tOE

OE

tOLZ

tLZ(4,5)

Data Out

NOTES (READ CYCLE)

1. WE is high for read cycle.

2. All read cycle timing is referenced from the last valid address to the first transition address.

3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to V OH or VOL Levels.

4. At any given temperature and voltage condition, t HZ(Max.) is less than tLZ (Min.) both for a given device and from device to device.

5. Transition is measured ±200§Æ from steady state voltage with Load(B). This parameter is sampled and not 100% tested.

6. Device is continuously selected with CS=VIL.

7. Address valid prior to coincident with CS transition low.

8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycl e.

Data Valid

tHZ(3,4,5)

tBHZ(3,4,5)

tOHZ

tOH

TIMING WAVE FORM OF WRITE CYCLE(1) (OE=Clock)

ADD

OE

CS

UB, LB

tAS(4)

WE

Data In

Data Out

High-Z

tOHZ(6)

tAW

tWC

tCW(3)

tBW

tWP(2)

High-Z(8)

tDW

Data Valid

tWR(5)

tDH

- 6 -

Rev 2.0

June -1997

PRELIMINARY

KM6164002, KM6164002E, KM6164002I CMOS SRAM

WRITE CYCLE

Parameter Symbol

Write Cycle Time tWC 20 - 25 ­Chip Select to End of Write tCW 15 - 17 - §À
Address Set-up Time tAS 0 - 0 - §À
Address Valid to End of Write tAW 15 - 17 - §À
Write Pulse Width(OE High) tWP 15 - 17 - §À
Write Pulse Width(OE Low) tWP1 20 - 25 ­UB, LB Valid to End of Write tBW 15 - 17 - ns
Write Recovery Time tWR 0 - 0 - §À
Write to Output High-Z
Data to Write Time Overlap tDW 10 - 12 - §À
Data Hold from Write Time tDH 0 - 0 ­End Write to Output Low-Z tOW 3 - 4 -

tWHZ

KM6164002-20 KM6164002-25

Min Max Min Max

0 8 0 8 §À

Unit

§À

§À

§À

§À

NOTE: Above parameters are also guaranteed at extended and industrial temperature ranges.

TIMING DIAGRAMS

TIMING WAVE FORM OF READ CYCLE(1) (Address Controlled, CS=OE=UB=LB=VIL, WE=VIH)

tRC

ADD

tAA

tOH

Data Out

Previous Data Valid Data Valid

- 5 -

Rev 2.0

June -1997

PRELIMINARY

KM6164002, KM6164002E, KM6164002I CMOS SRAM

AC CHARACTERISTICS(TA=0 to 70°C, VCC=5.0V±10%, unless otherwise noted.)

TEST CONDITIONS

Parameter Value

Input Pulse Levels 0V to 3V
Input Rise and Fall Times
Input and Output timing Reference Levels 1.5V
Output Loads See below

NOTE: Above test conditions are also applied at extended and industrial temperature ranges .

Output Loads(A) Output Loads(B)

for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ

+5.0V

§À

3

+5.0V
480Ω

5pF*

DOUT

255Ω

480Ω

30pF*

DOUT

255Ω

* Including Scope and Jig Capacitance

READ CYCLE

Parameter Symbol

Read Cycle Time tRC 20 - 25 ­Address Access Time tAA - 20 - 25
Chip Select to Output tCO - 20 - 25
Output Enable to Valid Output tOE - 10 - 12 §À
UB, LB Access Time tBA - 10 - 12 ns

Chip Enable to Low-Z Output
Output Enable to Low-Z Output tOLZ 0 - 0 -

UB, LB Enable to Low-Z Output

tLZ 5 - 5 -

tBLZ 0 - 0 - ns

KM6164002-20 KM6164002-25

Min Max Min Max

Unit

§À

§À

§À

§À

§À

Chip Disable to High-Z Output tHZ 0 7 0 8 §À
Output Disable to High-Z Output

UB, LB Disable to High-Z Output
Output Hold from Address Change tOH 4 - 5 -

NOTE: Above parameters are also guaranteed at extended and industrial temperature ranges.

tOHZ
tBHZ 0 7 0 8 ns

0 7 0 8 §À

- 4 -

Rev 2.0

June -1997

§À

PRELIMINARY

KM6164002, KM6164002E, KM6164002I CMOS SRAM

ABSOLUTE MAXIMUM RATINGS*

Parameter Symbol Rating Unit

Voltage on Any Pin Relative to VSS VIN, VOUT -0.5 to 7.0 V
Voltage on VCC Supply Relative to VSS VCC -0.5 to 7.0 V
Power Dissipation PD 1.0
Storage Temperature TSTG -65 to 150 °C

Commercial

Operating Temperature

* Stresses greater than those listed under "Absolute Maximum Rating" may cause permanent damage to the device. This is a stress ra ting only and func-

tional operation of the device at these at these or any other conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Extended
Industrial

TA
TA
TA

0 to 70 °C

-25 to 85 °C

-40 to 85 °C

RECOMMENDED DC OPERATING CONDITIONS(TA=0 to 70°C)

Parameter

Supply Voltage VCC 4.5 5.0 5.5 V
Ground VSS 0 0 0 V

Input Low Voltage VIH 2.2 - VCC+0.5**
Input Low Voltage VIL -0.5* - 0.8

Symbol

Min

Typ Max Unit

W

V
V

NOTE: Above parameters are also guaranteed at extended and industrial temperature ranges.

* VIL(Min) = -2.0V a.c(Pulse Width≤10ns) for I≤20§Ì

** VIH(Max) = VCC + 2.0V a.c (Pulse Width≤10ns) for I≤20

§Ì

DC AND OPERATING CHARACTERISTICS(TA=0 to 70°C, Vcc=5.0V±10%, unless otherwise specified)

Parameter Symbol Test Conditions Min Max Unit

Input Leakage Current ILI VIN = VSS to VCC -2 2 µA
Output Leakage Current ILO

Operating Current ICC

ISB Min. Cycle, CS=VIH - 60

Standby Current

Output Low Voltage Level VOL IOL=8mA - 0.4 V
Output High Voltage Level

NOTE: Above parameters are also guaranteed at extended and industrial temperature ranges.

* VCC=5.0V±5% Temp. = 25°C

ISB1

VOH IOH=-4mA 2.4 - V

VOH1* IOH1=-0.1mA - 3.95 V

CS=VIH or OE=VIH or WE=VIL
VOUT = VSS to VCC

Min. Cycle, 100% Duty
CS=VIL, VIN = VIH or VIL, IOUT=0mA

f=0MHz, CS≥VCC-0.2V,
VIN≥VCC-0.2V or VIN≤0.2V

-2 2 µA

20ns - 240
25ns - 220

- 10 §Ì

§Ì

§Ì

CAPACITANCE*(TA=25°C, f=1.0MHz)

Item Symbol Test Conditions MIN Max Unit

Input/Output Capacitance CI/O VI/O=0V - 8 pF
Input Capacitance CIN

* NOTE : Capacitance is sampled and not 100% tested.

VIN=0V

- 3 -

- 6 pF

Rev 2.0

June -1997

PRELIMINARY

KM6164002, KM6164002E, KM6164002I CMOS SRAM

256K x 16 Bit High-Speed CMOS Static RAM

GENERAL DESCRIPTIONFEATURES

¡Ü

Fast Access Time 20,25§À(Max.)

¡Ü

Low Power Dissipation
Standby (TTL) : 60§Ì(Max.)
CMOS) : 10§Ì(Max.)
Operating KM6164002 - 20 : 240§Ì(Max.)
KM6164002 - 25 : 220§Ì(Max.)

¡Ü

Single 5.0V±10% Power Supply

¡Ü

TTL Compatible Inputs and Outputs

¡Ü

I/O Compatible with 3.3V Device

¡Ü

Fully Static Operation

- No Clock or Refresh required

¡Ü

Three State Outputs

¡Ü

Center Power/Ground Pin Configuration

¡Ü

Data Byte Control : LB : I/O1~ I/O8, UB : I/O9~ I/O16

¡Ü

Standard Pin Configuration
KM6164002J : 44-SOJ-400

ORDERING INFORMATION

KM6164002 -20/25 Commercial Temp.
KM6164002E -20/25 Extended Temp.
KM6164002I -20/25 Industrial Temp.

FUNCTIONAL BLOCK DIAGRAM

A0
A1
A2
A3
A4
A6
A7
A8

A12
A13

Clk Gen.

Row Select

Pre-Charge Circuit

Memory Array

1048 Rows

256x16 Columns

The KM6164002 is a 4,194,304-bit high-speed Static Random
Access Memory organized as 262,144 words by 16 bits. The
KM6164002 uses 16 common input and output lines and has an
output enable pin which operates faster than address access
time at read cycle. Also it allows that lower and upper byte
access by data byte control (UB, LB). The device is fabricated
using SAMSUNG's advanced CMOS process and designed for
high-speed circuit technology. It is particularly well suited for use
in high-density high-speed system applications. The
KM6164002 is packaged in a 400mil 44-pin plastic SOJ.

PIN CONFIGURATION (Top View)

CS
I/O1
I/O2
I/O3
I/O4

Vcc

Vss
I/O5
I/O6
I/O7
I/O8

WE

1

A0

2

A1

3

A2

4

A3

5

A4

6
7
8

9
10
11
12
13
14
15
16
17
18

A5

19

A6

20

A7

21

A8

22

A9

SOJ

A17

44

A16

43

A15

42

OE

41

UB

40

LB

39

I/O16

38

I/O15

37

I/O14

36

I/O13

35

Vss

34

Vcc

33

I/O12

32

I/O11

31

I/O10

30

I/O9

29

N.C

28

A14

27

A13

26

A12

25

A11

24

A10

23

I/O1 ~ I/O8

I/O9 ~ I/O16

WE
OE

UB
LB

CS

Data

Cont.

Data

Cont.

Gen.
CLK

I/O Circuit &

Column Select

A5 A9 A10 A11A14 A15A16 A17

PIN FUNCTION

Pin Name Pin Function

A0 - A17 Address Inputs

WE Write Enable

CS Chip Select
OE Output Enable
LB Lower-byte Control(I/O1~I/O8)
UB Upper-byte Control(I/O9~I/O16)

I/O1 ~ I/O16 Data Inputs/Outputs

VCC Power(+5.0V)
VSS Ground

- 2 -

Rev 2.0

June -1997

PRELIMINARY

KM6164002, KM6164002E, KM6164002I CMOS SRAM

Document Title

64Kx16 Bit High Speed Static RAM(5V Operating), Revolutionary Pin out.
Operated at Commercial, Extended and Industrial Temperature Range.

Revision History

Rev No.

Rev. 0.0
Rev. 1.0

Rev. 2.0

History

Initial release with Preliminary.
Release to final Data Sheet.

1.1. Delete Preliminary

2.1.Delete Low power product with Data Retention Mode.

2.1.1. Delete Data Retention Characteristics

2.2.Add Industrial and Extended Temperature Range parts with the
same parameters as Commercial Temperature Range parts.

2.2.1 Add KM6164002I for Industrial Temperature Range.

2.2.2.Add KM6164002E for Extended Temperature Range.

2.2.3.Add ordering information.

2.2.4. Add the condition for operating at Industrial and Extended
Temperature Range.

2.3.Add timing diagram to define tWP1 as ″(Timing Wave Form of

Write Cycle(OE=Low fixed)″

2.4.Delete 35ns part.

Draft Data

Jun. 1th, 1991
Oct. 4th, 1993

Jun. 17th, 1997

Remark

Preliminary
Final

Final

The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right

to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this
device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.

- 1 -

Rev 2.0

June -1997