Datasheet KM44C4105CSL-6, KM44C4105CSL-5, KM44C4105CS-6, KM44C4105CKL-5, KM44C4105CK-6 Datasheet (Samsung)

CMOS DRAMKM44C4005C, KM44C4105C

This is a family of 4,194,304 x 4 bit Quad CAS with Extended Data Out Mode CMOS DRAMs. Extended Data Out Mode offers high
speed random access of memory cells within the same row, so called Hyper Page Mode. Refresh cycle (2K Ref. or 4K Ref.), access
time (-5 or -6), power consumption(Normal or Low power) and package type(SOJ or TSOP-II) are optional features of this family. All of
this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is avail­able in L-version. Four separate CAS pins provide for seperate I/O operation allowing this device to operate in parity mode.
This 4Mx4 Extended Data Out Quad CAS DRAM family is fabricated using Samsung′s advanced CMOS process to realize high band­width, low power consumption and high reliability.

• Part Identification

- KM44C4005C/C-L (5V, 4K Ref.)

- KM44C4105C/C-L (5V, 2K Ref.)

• Extended Data Out mode operation
(Fast Page Mode with Extended Data Out)

• Four separate CAS pins provide for separate I/O operation

• CAS-before-RAS refresh capability

• RAS-only and Hidden refresh capability

• Self-refresh capability (L-ver only)

• Fast parallel test mode capability

• TTL compatible inputs and outputs

• Early Write or output enable controlled write

• JEDEC Standard pinout

• Available in Plastic SOJ and TSOP(II) packages

• Single +5V±10% power supply

Control
Clocks

RAS

CAS0 - 3

W

Vcc
Vss

DQ0

to

DQ3

A0-A11

(A0 - A10)*1

A0 - A9

(A0 - A10)*1

Memory Array

4,194,304 x 4

Cells

SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.

4M x 4Bit CMOS Quad CAS DRAM with Extended Data Out

DESCRIPTION

FEATURES

FUNCTIONAL BLOCK DIAGRAM

• Refresh Cycles
Part

NO.

Refresh

cycle

Refresh period

Normal L-ver

C4005C 4K 64ms

128ms

C4105C 2K 32ms

• Performance Range

Speed

tRAC tCAC tRC tHPC

-5 50ns 13ns 84ns 20ns

-6 60ns 15ns 104ns 25ns

• Active Power Dissipation

Speed

Refresh Cycle

4K 2K

-5 495 605

-6 440 550

Unit : mW

Sense Amps & I/O

Data out

Buffer

Data in

Buffer

OE

Note) *1 : 2K Refresh

Col. Address Buffer

Row Address Buffer

Refresh Counter

Refresh Control

Refresh Timer

Column Decoder

Row Decoder

VBB Generator

CMOS DRAMKM44C4005C, KM44C4105C

PIN CONFIGURATION (Top Views)

Pin Name Pin Function

A0 - A11 Address Inputs (4K Product)
A0 - A10 Address Inputs (2K Product)

DQ0 - 3 Data In/Out

VSS Ground

RAS Row Address Strobe

CAS0~CAS3 Column Address Strobe

W Read/Write Input

OE Data Output Enable
VCC Power(+5.0V)
N.C No Connection

VCC
DQ0
DQ1

W

RAS

*A11(N.C)

CAS0
CAS1

A10

A0
A1
A2
A3

VCC

VSS
DQ3
DQ2
CAS3
OE
A9
CAS2
N.C
A8
A7
A6
A5
A4
VSS

1
2
3
4
5
6
7
8
9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17
16
15

VCC
DQ0
DQ1

W

RAS

*A11(N.C)

CAS0
CAS1

A10

A0
A1
A2
A3

VCC

VSS
DQ3
DQ2
CAS3
OE
A9
CAS2
N.C
A8
A7
A6
A5
A4
VSS

1
2
3
4
5
6
7
8
9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17
16
15

*A11 is N.C for KM44C4105C(5V, 2K Ref. product)
K : 300mil 28 SOJ

S : 300mil 28 TSOP II

•KM44C40(1)05CK

•KM44C40(1)05CS

CMOS DRAMKM44C4005C, KM44C4105C

ABSOLUTE MAXIMUM RATINGS

* Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted

to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

Parameter Symbol Rating Units

Voltage on any pin relative to VSS VIN,VOUT -1.0 to +7.0 V
Voltage on VCC supply relative to VSS VCC -1.0 to +7.0 V
Storage Temperature Tstg -55 to +150 °C
Power Dissipation PD 1 W
Short Circuit Output Current IOS 50 mA

RECOMMENDED OPERATING CONDITIONS (Voltage referenced to Vss, TA= 0 to 70°C)

*1 : VCC+2.0V/20ns, Pulse width is measured at VCC
*2 : -2.0/20ns, Pulse width is measured at VSS

Parameter Symbol Min Typ Max Units

Supply Voltage VCC 4.5 5.0 5.5 V
Ground VSS 0 0 0 V
Input High Voltage VIH 2.4 -

VCC+1.0

*1

V

Input Low Voltage VIL

-1.0

*2

- 0.8 V

DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.)

Parameter Symbol Min Max Units

Input Leakage Current (Any input 0≤VIN≤VIN+0.5V,
all other input pins not under test=0 Volt)

II(L) -5 5 uA

Output Leakage Current
(Data out is disabled, 0V≤VOUT≤VCC)

IO(L) -5 5 uA

Output High Voltage Level(IOH=-5mA) VOH 2.4 - V
Output Low Voltage Level(IOL=4.2mA) VOL - 0.4 V

CMOS DRAMKM44C4005C, KM44C4105C

*Note :

ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open.
ICC is specified as an average current. In ICC1, ICC3 and ICC6 address can be changed maximum once while RAS=VIL. In ICC4,
address can be changed maximum once within one Hyper page mode cycle time, tHPC.

DC AND OPERATING CHARACTERISTICS (Continued)

ICC1* : Operating Current (RAS and CAS cycling @tRC=min.)
ICC2 : Standby Current (RAS=CAS=W=VIH)
ICC3* : RAS-only Refresh Current (CAS=VIH, RAS cycling @tRC=min.)
ICC4* : Hyper Page Mode Current (RAS=VIL, CAS, Address cycling @tHPC=min.)
ICC5 : Standby Current (RAS=CAS=W=VCC-0.2V)
ICC6* : CAS-Before-RAS Refresh Current (RAS and CAS cycling @tRC=min.)
ICC7 : Battery back-up current, Average power supply current, Battery back-up mode
Input high voltage(VIH)=VCC-0.2V, Input low voltage(V IL)=0.2V, CAS=0.2V,
DQ=Don′t care, TRC=31.25us(4K/L-ver), 62.5us(2K/L-ver), TRAS=TRASmin~300ns
ICCS : Self Refresh Current
RAS=CAS=0.2V, W=OE=A0 ~ A11=VCC-0.2V or 0.2V,
DQ0 ~ DQ3=VCC-0.2V, 0.2V or Open

Symbol Power Speed

Max

Units

KM44C4005C KM44C4105C

ICC1 Don′t care

-5

-6

90
80

110
100

mA
mA
mA

ICC2

Normal

L

Don′t care

2
1

2
1

mA
mA

ICC3 Don′t care

-5

-6

90
80

110
100

mA
mA
mA

ICC4 Don′t care

-5

-6

80
70

90
80

mA
mA
mA

ICC5

Normal

L

Don′t care

1

250

1

250

mA

uA

ICC6 Don′t care

-5

-6

90
80

110
100

mA
mA

mA
ICC7 L Don′t care 300 300 uA
ICCS L Don′t care 250 250 uA

CMOS DRAMKM44C4005C, KM44C4105C

CAPACITANCE (TA=25°C, VCC=5V, f=1MHz)

Parameter Symbol Min Max Units

Input capacitance [A0 ~ A11] CIN1 - 5 pF
Input capacitance [RAS, CASx, W, OE] CIN2 - 7 pF
Output capacitance [DQ0 - DQ3] CDQ - 7 pF

Test condition : VCC=5.0V±10%, Vih/Vil=2.4/0.8V, Voh/Vol=2.0/0.8V

Parameter Symbol

-5 -6
Units Notes

Min Max Min Max

Random read or write cycle time

tRC

84 104 ns

Read-modify-write cycle time

tRWC

106 140 ns

Access time from RAS

tRAC

50 60 ns 3,4,10

Access time from CAS

tCAC

13 15 ns 3,4,5,20

Access time from column address

tAA

25 30 ns 3,10

CAS to output in Low-Z

tCLZ

3 3 ns 3,20

Output buffer turn-off delay from CAS

tCEZ

3 13 3 15 ns 6,13

OE to output in Low-Z

tOLZ

3 3 ns 3

Transition time (rise and fall)

tT

2 50 2 50 ns 2

RAS precharge time

tRP

30 40 ns

RAS pulse width

tRAS

50 10K 60 10K ns

RAS hold time

tRSH

13 15 ns 16

CAS hold time

tCSH

38 45 ns 19

CAS pulse width

tCAS

8 10K 10 10K ns 25

RAS to CAS delay time

tRCD

20 37 20 45 ns 4,18

RAS to column address delay time

tRAD

15 25 15 30 ns 10

CAS to RAS precharge time

tCRP

5 5 ns 17

Row address set-up time

tASR

0 0 ns

Row address hold time

tRAH

10 10 ns

Column address set-up time

tASC

0 0 ns 18

Column address hold time

tCAH

8 10 ns 18

Column address to RAS lead time

tRAL

25 30 ns

Read command set-up time

tRCS

0 0 ns

Read command hold time referenced to CAS

tRCH

0 0 ns 8,17

Read command hold time referenced to RAS

tRRH

0 0 ns 8

Write command hold time

tWCH

10 10 ns 16

Write command pulse width

tWP

10 10 ns

Write command to RAS lead time

tRWL

13 15 ns

Write command to CAS lead time

tCWL

8 10 ns 19

AC CHARACTERISTICS (0°C≤TA≤70°C, See note 1,2)

CMOS DRAMKM44C4005C, KM44C4105C

AC CHARACTERISTICS (Continued)

Parameter Symbol

-5 -6
Units Notes

Min Max Min Max

Data set-up time

tDS

0 0 ns 9

Data hold time

tDH

8 10 ns 9

Refresh period (2K, Normal)

tREF

32 32 ms

Refresh period (4K, Normal)

tREF

64 64 ms

Refresh period (L-ver)

tREF

128 128 ms

Write command set-up time

tWCS

0 0 ns 7,18

CAS to W delay time

tCWD

30 34 ns 7,16

RAS to W delay time

tRWD

67 79 ns 7

Column address to W delay time

tAWD

42 49 ns 7

CAS precharge to W delay time

tCPWD

47 54 ns 7

CAS set-up time (CAS -before-RAS refresh)

tCSR

5 5 ns 18

CAS hold time (CAS -before-RAS refresh)

tCHR

10 10 ns 17

RAS to CAS precharge time

tRPC

5 5 ns 18

Access time from CAS precharge

tCPA

28 35 ns 3,17

Hyper Page mode cycle time

tHPC

20 24 ns 14,21

Hyper Page read-modify-write cycle time

tHPRWC

62 71 ns 14,21

CAS precharge time (Hyper Page cycle)

tCP

8 10 ns 22

RAS pulse width (Hyper Page cycle)

tRASP

50 200K 60 200K ns

RAS hold time from CAS precharge

tRHCP

30 35 ns

OE access time

tOEA

13 15 ns 23

OE to data delay

tOED

13 15 ns 24

Output buffer turn off delay time from OE

tOEZ

3 13 3 15 ns 6

OE command hold time

tOEH

13 15 ns

Write command set-up time (Test mode in)

tWTS

10 10 ns 11

Write command hold time (Test mode in)

tWTH

10 10 ns 11

W to RAS precharge time(C-B-R refresh)

tWRP

10 10 ns

W to RAS hold time(C-B-R refresh)

tWRH

10 10 ns

Output data hold time

tDOH

5 5 ns

Output buffer turn off delay from RAS

tREZ

3 13 3 15 ns 6,13

Output buffer turn off delay from W

tWEZ

3 13 3 15 ns 6

W to data delay

tWED

15 15 ns

OE to CAS hold time

tOCH

5 5 ns

CAS hold time to OE

tCHO

5 5 ns

OE precharge time

tOEP

5 5 ns

W pulse width (Hyper Page Cycle)

tWPE

5 5 ns

RAS pulse width (C-B-R self refresh)

tRASS

100 100 us 27,28,29

RAS precharge time (C-B-R self refresh)

tRPS

90 110 ns 27,28,29

CAS hold time (C-B-R self refresh)

tCHS

-50 -50 ns 27,28,29

Hold time CAS low to CAS high

tCLCH

5 5 ns 15,26

CMOS DRAMKM44C4005C, KM44C4105C

TEST MODE CYCLE

Parameter Symbol

-5 -6
Units Notes

Min Max Min Max

Random read or write cycle time

tRC

89 109 ns

Read-modify-write cycle time

tRWC

121 145 ns

Access time from RAS

tRAC

55 65 ns 3,4,10,12

Access time from CAS

tCAC

18 20 ns 3,4,5,12

Access time from column address

tAA

30 35 ns 3,10,12

RAS pulse width

tRAS

55 10K 65 10K ns

CAS pulse width

tCAS

13 10K 15 10K ns

RAS hold time

tRSH

18 20 ns

CAS hold time

tCSH

43 50 ns

Column address to RAS lead time

tRAL

30 35 ns

CAS to W delay time

tCWD

35 39 ns 7

RAS to W delay time

tRWD

72 84 ns 7

Column address to W delay time

tAWD

47 54 ns 7

CAS precharge to W delay time

tCPWD

52 59 ns 7

Hyper Page mode cycle time

tHPC

25 30 ns 14

Hyper Page read-modify-write cycle time

tHPRWC

52 61 ns 14

RAS pulse width (Hyper Page cycle)

tRASP

55 200K 65 200K ns

Access time from CAS precharge

tCPA

33 40 ns 3

OE access time

tOEA

18 20 ns

OE to data delay

tOED

18 20 ns

OE command hold time

tOEH

18 20 ns

( Note 11 )

CMOS DRAMKM44C4005C, KM44C4105C

NOTES

An initial pause of 200us is required after power-up followed by any 8 RAS-only refresh or CAS-before-RAS refresh cycles
before proper device operation is achieved.
VIH(min) and VIL(max) are reference levels for measuring timing of input signals.
Transition times are measured between VIH(min) and VIL(max) and are assumed to be 2ns for all inputs.
Measured with a load equivalent to 2 TTL loads and 100pF.
Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only.

If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC.
Assumes the tRCD≥tRCD(max).
This parameter defines the time at which the output achieves the open circuit condition and is not referenced to Voh or Vol.

tWCS, tRWD, tCWD, tAWD and tCPWD are non restrictive operating parameters. They are included in the data sheet as electrical

characteristics only. If tWCS≥tWCS(min), the cycle is an early write cycle and the data output will remain high impedance for the
duration of the cycle. If tCWD≥tCWD(min), tRWD≥tRWD(min), tAWD≥tAWD(min) and tCPWD≥tCPWD(min), then the cycle is a read­modify-write cycle and the data output will contain the data read from the selected address. If neither of the above conditions
is satisfied, the condition of the data out is indeterminate.

tRCH and tRRH must be satisfied for a read cycle.

These parameters are referenced to the first CAS falling edge in early write cycles and to W falling edge in OE controlled write
cycle and read-modify-write cycles.
Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference point only.
If tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA.
These specifications are applied in the test mode.
In test mode read cycle, the values of tRAC, tAA and tCAC are delayed by 2ns to 5ns for the specified values. These parame­ters should be specified in test mode cycles by adding 5ns to the specified value in this data sheet.
If RAS goes high before CAS high going, the open circuit condition of the output is achieved by CAS high going.
If CAS goes high before RAS high going, the open circuit condition of the output is achieved by RAS high going.

tASC≥6ns, Assume tT = 2.0ns.

In order to hold the address latched by the first CAS going low, the parameter tCLCH must be met.
The last CASx edge to go low.
The last CASx edge to go high.
The first CASx edge to go low.
The first CASx edge to go high.
Output parameter is refrenced to corresponding CASx input.
The last rising CASx edge to next cycle′s last rising CASx edge.
The last rising CASx edge to first falling CASx edge.
The first DQx controlled by the first CASx to go low.
The last DQx controlled by the last CASx to go high.
Each CASx must meet minimum pulse width.
The last falling CASx edge to the first rising CASx edge.
If tRASS≥100us, then RAS precharge time must use tRPS instead of tRP.
For RAS-only refresh and burst CAS-before-RAS refresh mode, 4096(4K)/2048(2K) cycles of burst refresh must be executed
within 64ms/32ms before and after self refresh, in order to meet refresh specification.
For distributed CAS-before-RAS with 15.6us interval, CAS-before-RAS refresh should be executed with in 15.6us immedi­ately before and after self refresh in order to meet refresh specification.

8.

6.

5.

10.

9.

3.

2.

1.

4.

14.

15.

16.

17.

18.

19.

20.

21.

22.

23.

24.

11.

12.

13.

25.

26.

27.

28.

29.

7.

CMOS DRAMKM44C4005C, KM44C4105C

tCRP

RAS

VIH -
VIL -

CAS0

VIH -
VIL -

A

VIH -
VIL -

W

VIH -
VIL -

OE

VIH -
VIL -

VIH -
VIL -

DQ0 ~ DQ3

READ CYCLE

COLUMN

ADDRESS

ROW

ADDRESS

tRAS

tRC

tCRP

tRP

tCSH

tRSHtRCD

tCAS

tRAL

tRAD

tASR tRAH

tASC

tCAH

tAA

tOEA

tCAC

tCLZ

tRAC

OPEN

tRRH

tRCH

Don′t care

Undefined

tRCS

tCRP

CAS1

VIH -
VIL -

tCRP

CAS2

VIH -
VIL -

tCRP

CAS3

VIH -
VIL -

tCLCH

tREZ

tOEZ

tCEZ

tWEZ

DATA-OUT

tOLZ

tROH

CMOS DRAMKM44C4005C, KM44C4105C

tWCS

WRITE CYCLE ( EARLY WRITE )

NOTE : DOUT = OPEN

A

VIH -
VIL -

W

VIH -
VIL -

OE

VIH -
VIL -

ROW

ADDRESS

tRAL

tRAD

tASR tRAH

tASC

tCAH

tWP

tDS

tDH

tWCH

Don′t care

DATA-IN

Undefined

tCRP

RAS

VIH -
VIL -

CAS0

VIH -
VIL -

tRAS

tRC

tCRP

tRP

tCSH

tRSHtRCD

tCAS

tCRP

CAS1

VIH -
VIL -

tCRP

CAS2

VIH -
VIL -

tCRP

CAS3

VIH -
VIL -

tCLCH

VIH -
VIL -

DQ0 ~ DQ3

COLUMN

ADDRESS

tCSH

CMOS DRAMKM44C4005C, KM44C4105C

tOED

A

VIH -
VIL -

W

VIH -
VIL -

OE

VIH -
VIL -

VIH -
VIL -

DQ0 ~ DQ3

COLUMN

ADDRESS

ROW

ADDRESS

tRAL

tRAD

tASR tRAH

tASC

tCAH

DATA-IN

tWP

Don′t care

WRITE CYCLE ( OE CONTROLLED WRITE )

NOTE : DOUT = OPEN

tCWL

tRWL

tDS

tDH

tOEH

Undefined

tCRP

RAS

VIH -
VIL -

CAS0

VIH -
VIL -

tRAS

tRC

tCRP

tRP

tCSH

tRSHtRCD
tCAS

tCRP

CAS1

VIH -
VIL -

tCRP

CAS2

VIH -
VIL -

tCRP

CAS3

VIH -
VIL -

tCLCH

CMOS DRAMKM44C4005C, KM44C4105C

W

VIH -
VIL -

OE

VIH -
VIL -

VIH -
VIL -

DQ0 ~ DQ3

VALID

tWP

Don′t care

READ - MODIFY - WRTIE CYCLE

tRWL

tCWL

tOEZ

tOED

tAWD

tCWD

DATA-OUT

Undefined

VALID

DATA-IN

tRAC

tAA

tDS

tDH

tCRP

RAS

VIH -
VIL -

CAS0

VIH -
VIL -

tRAS

tRC

tCRP

tRP

tCSH

tRSHtRCD

tCAS

tCRP

CAS1

VIH -
VIL -

tCRP

CAS2

VIH -
VIL -

tCRP

CAS3

VIH -
VIL -

tCLCH

A

VIH -
VIL -

ROW

ADDRESS

tRAL

tRAD

tASR tRAH

tASC

tCAH

tOEA

tRWD

COLUMN

ADDRESS

tCAC

tCLZ

tOLZ

CMOS DRAMKM44C4005C, KM44C4105C

DQ0

DQ1

DQ2

DQ3

tRCH

tOEZ

tCLZ

RAS

VIH -
VIL -

VIH -
VIL -

A

VIH -
VIL -

W

VIH -
VIL -

OE

VIH -
VIL -

VIH -
VIL -

COLUMN

ADDRESS

ROW

ADDR

tRHCP

tRASP

tCAS

tASC

tRAD

tASR

tRAH

tCRP

VALID

Don't care

HYPER PAGE MODE READ CYCLE

tOEZ

tRRH

DATA-OUT

Undefined

VALID

DATA-OUT

COLUMN

ADDRESS

COLUMN

ADDRESS

tRSH

tCAS

tRCD

tHPC

¡ó

tCAH

¡ó

¡ó

¡ó

tRCH

¡ó

tRCS tRCS

tRCS

tOEA

tCLZ

tAA

tOEZ

tRAC

tAA

¡ó

¡ó

tCP

tCAS

tRP

tCP

VIH -
VIL -

VIH -
VIL -

VIH -
VIL -

CAS0

CAS1

CAS2

CAS3

¡ó

¡ó

tCLCH

tASC

VIH -
VIL -

VIH -
VIL -

VIH -
VIL -

tHPC

tCPA

tAA

tCPA

tCAC

¡ó

tCLZ

VALID

DATA-OUT

VALID

DATA-OUT

VALID

DATA-OUT

VALID

DATA-OUT

VALID

DATA-OUT

¡ó

VALID

DATA-OUT

tCLCH

tRCH

tOLZ

tCSH
tASC

tRAL

tRAC

tCLZ

¡ó

¡ó

tCAH

tCAH

tASC

CMOS DRAMKM44C4005C, KM44C4105C

tASC

tCAH

RAS

VIH -
VIL -

CAS0

VIH -
VIL -

A

VIH -
VIL -

W

VIH -
VIL -

OE

VIH -
VIL -

VIH -
VIL -

COLUMN

ADDRESS

ROW

ADDR

tRHCP

tRASP

tCAS

tRAD

tASR tRAH

tASC

tCRP

VALID

Don′t care

HYPER PAGE MODE WRITE CYCLE ( EARLY WRITE )

DATA-IN

Undefined

VALID

DATA-IN

tDS

NOTE : DOUT = OPEN

COLUMN

ADDRESS

tRSH

tCAS

tRCD

tHPC

¡ó

tCSH

tCAH tASC

¡ó

¡ó

¡ó

tWCS tWCH

tWCS

tWP

tWP

tWCH

tWCS

tWCH

tDH tDS tDH tDS

¡ó

¡ó

¡ó

tRP

tCP

tCP

tCAS

tHPC

CAS1

VIH -
VIL -

tCAS

¡ó

tCAS

CAS2

VIH -
VIL -

tCAS

¡ó

tCAS

CAS3

VIH -
VIL -

tCAS

¡ó

VIH -
VIL -

VALID

DATA-IN

tDS

VALID

DATA-IN

tDH tDS

VIH -
VIL -

VALID

DATA-IN

VALID

DATA-IN

tDS tDH tDS tDH

VIH -
VIL -

VALID

DATA-IN

tDS

DQ0

DQ1

DQ2

DQ3

tDH

tDH

VALID

DATA-IN

tDH

¡ó

¡ó

¡ó

¡ó

¡ó

¡ó

¡ó

¡ó

tWP

COLUMN

ADDRESS

tCAH

CMOS DRAMKM44C4005C, KM44C4105C

tCAC

tASC

tASC

RAS

VIH -
VIL -

A

VIH -
VIL -

W

VIH -
VIL -

OE

VIH -
VIL -

VIH -
VIL -

DQ0 ~ DQ3

ROW

ADDR

tRASP

tASR

VALID

Don′t care

HYPER PAGE READ - MODIFY - WRITE CYCLE

DATA-OUT

Undefined

tRCD

tCP

tRAD

tCAH

tWP

tDH

COL.

ADDR

COL.

ADDR

tCAS

tCAS

tCRP

tCAH

tRAL

tPRWC

tRCS

tCWL

tCWD

tAWD

tRWD

tWP

tCWD

tAWD

tAA

tRAC

tOEA

tCLZ

tCAC

tOEZ

tOED

VALID

DATA-IN

VALID

DATA-OUT

VALID

DATA-IN

tCLZ

tDS

tOEA

tAA

tDH

tDS

tOEZ

tOED

tRWL

tRP

tRSH

tRAH

tCLCH

tCAS

tCAS

tCAS

tCAS

CAS0

VIH -
VIL -

CAS1

VIH -
VIL -

CAS2

VIH -
VIL -

CAS3

VIH -
VIL -

tCLCH

tCWL

tCSH

CMOS DRAMKM44C4005C, KM44C4105C

RAS

VIH -
VIL -

CASX

VIH -
VIL -

A

VIH -
VIL -

ROW

ADDR

tRAS

tRC

tRP

tASR tRAH

tCRP

Don′t care

RAS - ONLY REFRESH CYCLE*

Undefined

NOTE : W, OE, DIN = Don′t care

DOUT = OPEN

tRPC

tCRP

CAS - BEFORE - RAS REFRESH CYCLE

NOTE : OE, A = Don′t care

RAS

VIH -
VIL -

CASX

VIH -
VIL -

tRAS

tRC

tRP

tWRP

tRPC

tRP

tCP

tCHR

tCSR

W

VIH -
VIL -

tWRH

tCEZ

tRPC

VIH -
VIL -

DQ0 ~ DQ3

OPEN

CMOS DRAMKM44C4005C, KM44C4105C

tCEZ

RAS

VIH -
VIL -

CASX

VIH -
VIL -

A

VIH -
VIL -

W

VIH -
VIL -

OE

VIH -
VIL -

VIH -
VIL -

DQX

HIDDEN REFRESH CYCLE ( READ )

COLUMN

ADDRESS

ROW

ADDRESS

tRAS

tRC

tCHRtRCD

tRAD

tASR tRAH tASC

tCAH

tCRP

tRCS

tAA

tOEA

tCAC

tCLZ

tRAC

OPEN

Don′t care

tRSH

tOEZ

Undefined

tRC

DATA-OUT

tRP tRP

tRAS

tWRH

CMOS DRAMKM44C4005C, KM44C4105C

RAS

VIH -
VIL -

CASX

VIH -
VIL -

A

VIH -
VIL -

W

VIH -
VIL -

OE

VIH -
VIL -

VIH -
VIL -

HIDDEN REFRESH CYCLE ( WRITE )

COLUMN

ADDRESS

ROW

ADDRESS

tRAS

tRC

tCHR

tRCD

tRAD

tASR tRAH tASC

tCAH

tCRP

Don′t care

tRSH

DATA-IN

Undefined

tRC

NOTE : DOUT = OPEN

tWCH

tWP

tDH

tRPtRP

tRAS

tDS

tWCS

DQX

tWRH

tWRP

CMOS DRAMKM44C4005C, KM44C4105C

Don′t care

Undefined

CAS - BEFORE - RAS SELF REFRESH CYCLE

NOTE : OE, A = Don′t care, WE=Vcc-0.2V

RAS

VIH -
VIL -

CASX

VIH -
VIL -

tRASS tRPS

tRPC

tCHS

tRP

tCP

tCSR

tCEZ

tRPC

OPEN

VOH -
VOL -

DQ0 ~ DQ3

TEST MODE IN CYCLE

NOTE : OE, A = Don′t care

RAS

VIH -
VIL -

CASX

VIH -
VIL -

tRAS

tRC

tRP

tCRP

tWTS

tRPC

tRP

tCP

tCHR

tCSR

W

VIH -
VIL -

tWTH

tCEZ

OPEN

VIH -
VIL -

DQ0 ~ DQ3

CMOS DRAMKM44C4005C, KM44C4105C

PACKAGE DIMENSION

28 SOJ 300mil

0.300 (7.62)

0.330 (8.39)

0.340 (8.63)

0.730 (18.54)

0.720 (18.30)

MAX

0.741 (18.82)

MAX

0.148 (3.76)

0.0375 (0.95) 0.050 (1.27)

0.032 (0.81)

0.026 (0.66)

0.021 (0.53)

0.015 (0.38)

0.027 (0.69)

0.012 (0.30)

0.006 (0.15)

0.280 (7.11)

0.260 (6.61)

MIN

#28

#1

Units : Inches (millimeters)

28 TSOP(II) 300mil

MAX

0.047 (1.20)

MIN

0.002 (0.05)

0.020 (0.50)

0.012 (0.30)

0.050 (1.27)0.037 (0.95)

0.721 (18.31)

0.729 (18.51)

0.741 (18.81)
MAX

0.010 (0.25)

0.004 (0.10)

0.300 (7.62)

0.371 (9.42)

0.355 (9.02)

Units : Inches (millimeters)

0~8

0.030 (0.75)

0.018 (0.45)

TYP

0.010 (0.25)

O