Datasheet KM416V1200CT-5, KM416V1200CJL-6, KM416V1200CJL-5, KM416V1200CTL-6, KM416V1200CTL-5 Datasheet (Samsung)
...Page 1
KM416C1000C, KM416C1200C
CMOS DRAMKM416V1000C, KM416V1200C
This is a family of 1,048,576 x 16 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory
cells within the same row. Power supply voltage (+5.0V or +3.3V), refresh cycle (1K Ref. or 4K Ref.), access time (-5 or -6), power consumption(Normal or Low power) and package type(SOJ or TSOP-II) are optional features of this family. All of this family have CASbefore-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This
1Mx16 Fast Page Mode DRAM family is fabricated using Samsung′s advanced CMOS process to realize high band-width, low power
consumption and high reliability. It may be used as graphic memory unit for microcomputer, personal computer and portable machines.
• Part Identification
- KM416C1000C/C-L (5V, 4K Ref.)
- KM416C1200C/C-L (5V, 1K Ref.)
- KM416V1000C/C-L (3.3V, 4K Ref.)
- KM416V1200C/C-L (3.3V, 1K Ref.)
• Fast Page Mode operation
• 2 CAS Byte/Word Read/Write operation
• CAS-before-RAS refresh capability
• RAS-only and Hidden refresh capability
• Self-refresh capability (L-ver only)
• TTL(5V)/LVTTL(3.3V) compatible inputs and outputs
• Early Write or output enable controlled write
• JEDEC Standard pinout
• Available in 42-pin SOJ 400mil and 50(44)-pin TSOP(II)
400mil packages
• Single +5V±10% power supply (5V product)
• Single +3.3V±0.3V power supply (3.3V product)
Control
Clocks
VBB Generator
Refresh Timer
Refresh Control
Refresh Counter
Row Address Buffer
Col. Address Buffer
Row Decoder
Column Decoder
Lower
Data out
Buffer
RAS
UCAS
LCAS
W
Vcc
Vss
DQ0
to
DQ7
A0-A11
(A0 - A9)*1
A0 - A7
(A0 - A9)*1
Memory Array
1,048,576 x16
Cells
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.
1M x 16Bit CMOS Dynamic RAM with Fast Page Mode
DESCRIPTION
FEATURES
FUNCTIONAL BLOCK DIAGRAM
• Refresh Cycles
Part
NO.
VCC
Refresh
cycle
Refresh period
Normal L-ver
C1000C 5V
4K 64ms
128ms
V1000C 3.3V
C1200C 5V
1K 16ms
V1200C 3.3V
• Perfomance Range
Speed
tRAC tCAC tRC tPC
Remark
-5 50ns 15ns 90ns 35ns 5V/3.3V
-6 60ns 15ns 110ns 40ns 5V/3.3V
• Active Power Dissipation
Speed
3.3V 5V
4K 1K 4K 1K
-5 324 504 495 770
-6 288 468 440 715
Unit : mW
Sense Amps & I/O
Upper
Data in
Buffer
Upper
Data out
Buffer
Lower
Data in
Buffer
DQ8
to
DQ15
OE
Note) *1 : 1K Refresh
Page 2
KM416C1000C, KM416C1200C
CMOS DRAMKM416V1000C, KM416V1200C
VCC
DQ0
DQ1
DQ2
DQ3
VCC
DQ4
DQ5
DQ6
DQ7
N.C
N.C
N.C
W
RAS
*A11(N.C)
*A10(N.C)
A0
A1
A2
A3
VCC
VSS
DQ15
DQ14
DQ13
DQ12
VSS
DQ11
DQ10
DQ9
DQ8
N.C
N.C
LCAS
UCAS
OE
A9
A8
A7
A6
A5
A4
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
PIN CONFIGURATION (Top Views)
Pin Name Pin Function
A0 - A11 Address Inputs (4K Product)
A0 - A9 Address Inputs (1K Product)
DQ0 - 15 Data In/Out
VSS Ground
RAS Row Address Strobe
UCAS Upper Column Address Strobe
LCAS Lower Column Address Strobe
W Read/Write Input
OE Data Output Enable
VCC
Power(+5V)
Power(+3.3V)
N.C No Connection
VCC
DQ0
DQ1
DQ2
DQ3
VCC
DQ4
DQ5
DQ6
DQ7
N.C
N.C
W
RAS
*A11(N.C)
*A10(N.C)
A0
A1
A2
A3
VCC
VSS
DQ15
DQ14
DQ13
DQ12
VSS
DQ11
DQ10
DQ9
DQ8
N.C
LCAS
UCAS
OE
A9
A8
A7
A6
A5
A4
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
*A10 and A11 are N.C for KM416C/V1200C(5V/3.3V, 1K Ref. product)
J : 400mil 42 SOJ
T : 400mil 50(44) TSOP II
•KM416C/V10(2)00CJ
•KM416C/V10(2)00CT
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KM416C1000C, KM416C1200C
CMOS DRAMKM416V1000C, KM416V1200C
ABSOLUTE MAXIMUM RATINGS
* Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted
to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Parameter Symbol
Rating
Units
3.3V 5V
Voltage on any pin relative to VSS VIN,VOUT -0.5 to +4.6 -1.0 to +7.0 V
Voltage on VCC supply relative to VSS VCC -0.5 to +4.6 -1.0 to +7.0 V
Storage Temperature Tstg -55 to +150 -55 to +150 °C
Power Dissipation PD 1 1 W
Short Circuit Output Current IOS 50 50 mA
RECOMMENDED OPERATING CONDITIONS (Voltage referenced to Vss, TA= 0 to 70°C)
*1 : VCC+1.3V/15ns(3.3V), VCC+2.0V/20ns(5V), Pulse width is measured at VCC
*2 : -1.3V/15ns(3.3V), -2.0V/20ns(5V), Pulse width is measured at VSS
Parameter Symbol
3.3V 5V
Units
Min Typ Max Min Typ Max
Supply Voltage VCC 3.0 3.3 3.6 4.5 5.0 5.5 V
Ground VSS 0 0 0 0 0 0 V
Input High Voltage VIH 2.0 -
VCC+0.3
*1
2.4 -
VCC+1.0
*1
V
Input Low Voltage VIL
-0.3
*2
- 0.8
-1.0
*2
- 0.8 V
DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.)
Max Parameter Symbol Min Max Units
3.3V
Input Leakage Current (Any input 0≤VIN≤VIN+0.3V,
all other input pins not under test=0 Volt)
II(L) -5 5 uA
Output Leakage Current
(Data out is disabled, 0V≤VOUT≤VCC)
IO(L) -5 5 uA
Output High Voltage Level(IOH=-2mA) VOH 2.4 - V
Output Low Voltage Level(IOL=2mA) VOL - 0.4 V
5V
Input Leakage Current (Any input 0≤VIN≤VIN+0.5V,
all other input pins not under test=0 Volt)
II(L) -5 5 uA
Output Leakage Current
(Data out is disabled, 0V≤VOUT≤VCC)
IO(L) -5 5 uA
Output High Voltage Level(IOH=-5mA) VOH 2.4 - V
Output Low Voltage Level(IOL=4.2mA) VOL - 0.4 V
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KM416C1000C, KM416C1200C
CMOS DRAMKM416V1000C, KM416V1200C
*Note :
ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open.
ICC is specified as an average current. In ICC1, ICC3 and ICC6, address can be changed maximum once while RAS=VIL. In ICC4,
address can be changed maximum once within one fast page mode cycle time, tPC.
DC AND OPERATING CHARACTERISTICS (Continued)
ICC1* : Operating Current (RAS and UCAS, LCAS cycling @tRC=min.)
ICC2 : Standby Current (RAS=UCAS=LCAS=W=VIH)
ICC3* : RAS-only Refresh Current (UCAS=LCAS=VIH, RAS cycling @tRC=min.)
ICC4* : Fast Page Mode Current (RAS=VIL, UCAS or LCAS, Address cycling @tPC=min.)
ICC5 : Standby Current (RAS=UCAS=LCAS=W=VCC-0.2V)
ICC6* : CAS-Before-RAS Refresh Current (RAS, UCAS or LCAS cycling @tRC=min.)
ICC7 : Battery back-up current, Average power supply current, Battery back-up mode
Input high voltage(VIH)=VCC-0.2V, Input low voltage(V IL)=0.2V, UCAS, LCAS=0.2V,
DQ=Don′t care, TRC=31.25us(4K/L-ver), 125us(1K/L-ver),
TRAS=TRASmin~300ns
ICCS : Self Refresh Current
RAS=UCAS=LCAS=VIL, W=OE=A0 ~ A11=VCC-0.2V or 0.2V,
DQ0 ~ DQ15=VCC-0.2V, 0.2V or Open
Symbol Power Speed
Max
Units
KM416V1000C KM416V1200C KM416C1000C KM416C1200C
ICC1 Don′t care
-5
-6
90
80
140
130
90
80
140
130
mA
mA
ICC2
Normal
L
Don′t care
1
1
1
1
2
1
2
1
mA
mA
ICC3 Don′t care
-5
-6
90
80
140
130
90
80
140
130
mA
mA
ICC4 Don′t care
-5
-6
90
80
90
80
90
80
90
80
mA
mA
ICC5
Normal
L
Don′t care
0.5
200
0.5
200
1
200
1
200
mA
uA
ICC6 Don′t care
-5
-6
90
80
140
130
90
80
140
130
mA
mA
ICC7 L Don′t care 300 200 350 250 uA
ICCS L Don′t care 150 150 200 200 uA
Page 5
KM416C1000C, KM416C1200C
CMOS DRAMKM416V1000C, KM416V1200C
CAPACITANCE (TA=25°C, VCC=5V or 3.3V, f=1MHz)
Parameter Symbol Min Max Units
Input capacitance [A0 ~ A11] CIN1 - 5 pF
Input capacitance [RAS, UCAS, LCAS, W, OE] CIN2 - 7 pF
Output capacitance [DQ0 - DQ15] CDQ - 7 pF
Test condition (5V device) : VCC=5.0V±10%, Vih/Vil=2.4/0.8V, Voh/Vol=2.4/0.4V
Parameter Symbol
-5 -6
Units Notes
Min Max Min Max
Random read or write cycle time
tRC
90 110 ns
Read-modify-write cycle time
tRWC
133 155 ns
Access time from RAS
tRAC
50 60 ns 3,4,10
Access time from CAS
tCAC
15 15 ns 3,4,5
Access time from column address
tAA
25 30 ns 3,10
CAS to output in Low-Z
tCLZ
0 0 ns 3
Output buffer turn-off delay
tOFF
0 13 0 15 ns 6
Transition time (rise and fall)
tT
3 50 3 50 ns 2
RAS precharge time
tRP
30 40 ns
RAS pulse width
tRAS
50 10K 60 10K ns
RAS hold time
tRSH
13 15 ns
CAS hold time
tCSH
50 60 ns
CAS pulse width
tCAS
13 10K 15 10K ns
RAS to CAS delay time
tRCD
20 37 20 45 ns 4
RAS to column address delay time
tRAD
15 25 15 30 ns 10
CAS to RAS precharge time
tCRP
5 5 ns
Row address set-up time
tASR
0 0 ns
Row address hold time
tRAH
10 10 ns
Column address set-up time
tASC
0 0 ns 11
Column address hold time
tCAH
10 10 ns 11
Column address to RAS lead time
tRAL
25 30 ns
Read command set-up time
tRCS
0 0 ns
Read command hold time referenced to CAS
tRCH
0 0 ns 8
Read command hold time referenced to RAS
tRRH
0 0 ns 8
Write command hold time
tWCH
10 10 ns
Write command pulse width
tWP
10 10 ns
Write command to RAS lead time
tRWL
13 15 ns
Write command to CAS lead time
tCWL
13 15 ns
AC CHARACTERISTICS (0°C≤TA≤70°C, See note 1,2)
Test condition (3.3V device) : VCC=3.3V±0.3V, Vih/Vil=2.2/0.7V, Voh/Vol=2.0/0.8V
Page 6
KM416C1000C, KM416C1200C
CMOS DRAMKM416V1000C, KM416V1200C
AC CHARACTERISTICS (Continued)
Parameter Symbol
-5 -6
Units Notes
Min Max Min Max
Data set-up time
tDS
0 0 ns 9,17
Data hold time
tDH
10 10 ns 9,17
Refresh period (1K, Normal)
tREF
16 16 ms
Refresh period (4K, Normal)
tREF
64 64 ms
Refresh period (L-ver)
tREF
128 128 ms
Write command set-up time
tWCS
0 0 ns 7
CAS to W delay time
tCWD
36 40 ns 7,13
RAS to W delay time
tRWD
73 85 ns 7
Column address to W delay time
tAWD
48 55 ns 7
CAS precharge to W delay time
tCPWD
53 60 ns 7
CAS set-up time (CAS-before-RAS refresh)
tCSR
5 5 ns 15
CAS hold time (CAS-before-RAS refresh)
tCHR
10 10 ns 16
RAS to CAS precharge time
tRPC
5 5 ns
Access time from CAS precharge
tCPA
30 35 ns 3
Fast Page mode cycle time
tPC
35 40 ns
Fast Page read-modify-write cycle time
tPRWC
76 80 ns
CAS precharge time (Fast Page cycle)
tCP
10 10 ns 12
RAS pulse width (Fast Page cycle)
tRASP
50 200K 60 200K ns
RAS hold time from CAS precharge
tRHCP
30 35 ns
OE access time
tOEA
13 15 ns 3
OE to data delay
tOED
13 15 ns
Output buffer turn off delay time from OE
tOEZ
0 13 0 15 ns
OE command hold time
tOEH
13 15 ns
RAS pulse width (C-B-R self refresh)
tRASS
100 100 us 18,19,20
RAS precharge time (C-B-R self refresh)
tRPS
90 110 ns 18,19,20
CAS hold time (C-B-R self refresh)
tCHS
-50 -50 ns 18,19,20
Page 7
KM416C1000C, KM416C1200C
CMOS DRAMKM416V1000C, KM416V1200C
NOTES
An initial pause of 200us is required after power-up followed by any 8 RAS-only refresh or CAS-before-RAS refresh cycles
before proper device operation is achieved.
Input voltage levels are Vih/Vil. VIH(min) and VIL(max) are reference levels for measuring timing of input signals.
Transition times are measured between VIH(min) and VIL(max) and are assumed to be 5ns for all inputs.
Measured with a load equivalent to 2 TTL(5V)/1TTL(3.3V) loads and 100pF.
Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only.
If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC.
Assumes that tRCD≥tRCD(max).
This parameter defines the time at which the output achieves the open circuit condition and is not referenced to Voh or Vol.
tWCS, tRWD, tCWD, tAWD and tCPWD are non restrictive operating parameters. They are included in the data sheet as electrical
characteristics only. If tWCS≥tWCS(min), the cycle is an early write cycle and the data output will remain high impedance for the
duration of the cycle. If tCWD≥tCWD(min), tRWD≥tRWD(min), tAWD≥tAWD(min) and tCPWD≥tCPWD(min), then the cycle is a readmodify-write cycle and the data output will contain the data read from the selected address. If neither of the above conditions
is satisfied, the condition of the data out is indeterminate.
Either tRCH or tRRH must be satisfied for a read cycle.
These parameters are referenced to CAS falling edge in early write cycles and to W falling edge in OE controlled write cycle
and read-modify-write cycles.
Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference point only.
If tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA.
tASC, tCAH are referenced to the earlier CAS falling edge.
tCP is specified from the later CAS rising edge in the previous cycle to the earlier CAS falling edge in the next cycle.
KM416C/V10(2)00C/C-L Truth Table
RAS LCAS UCAS W OE DQ0 - DQ7 DQ8-DQ15 STATE
H X X X X Hi-Z Hi-Z Standby
L H H X X Hi-Z Hi-Z Refresh
L L H H L DQ-OUT Hi-Z Byte Read
L H L H L Hi-Z DQ-OUT Byte Read
L L L H L DQ-OUT DQ-OUT Word Read
L L H L H DQ-IN - Byte Write
L H L L H - DQ-IN Byte Write
L L L L H DQ-IN DQ-IN Word Write
L L L H H Hi-Z Hi-Z -
6.
5.
10.
8.
3.
2.
1.
4.
11.
12.
7.
9.
Page 8
KM416C1000C, KM416C1200C
CMOS DRAMKM416V1000C, KM416V1200C
tCWD is referenced to the later CAS falling edge at word read-modify-write cycle.
tCWL is specified from W falling edge to the earlier CAS rising edge.
tCSR is referenced to the earlier CAS falling edge before RAS transition low.
tCHR is referenced to the later CAS rising edge after RAS transition low.
tCSR tCHR
RAS
LCAS
UCAS
16.
15.
14.
13.
tDS, tDH is independently specified for lower byte DQ(0-7), upper byte DQ(8-15)
If tRASS≥100us, then RAS precharge time must use tRPS instead of tRP.
For RAS-only refresh and burst CAS-before-RAS refresh mode, 4096(4K)/1024(1K) cycles of burst refresh must be executed
within 64ms/16ms before and after self refresh, in order to meet refresh specification.
For distributed CAS-before-RAS with 15.6us interval CAS-before-RAS refresh should be executed with in 15.6us immediately
before and after self refresh in order to meet refresh specification.
17.
18.
19.
20.
Page 9
KM416C1000C, KM416C1200C
CMOS DRAMKM416V1000C, KM416V1200C
RAS
VIH -
VIL -
UCAS
VIH -
VIL -
A
VIH -
VIL -
W
VIH -
VIL -
OE
VIH -
VIL -
VOH -
VOL -
DQ0 ~ DQ7
COLUMN
ADDRESS
ROW
ADDRESS
tRAS
tRC
tCRP
tRP
tCSH
tRSHtRCD
tCAS
tRAL
tASR tRAH
tASC
tCAH
tCRP
tAA
tOEA
tCAC
tCLZ
tRAC
OPEN
tOFF
tRCH
Don′t care
Undefined
LCAS
VIH -
VIL -
tCRP
tCSH
tRSHtRCD
tCAS
tRAD
tCRP
tRRH
VOH -
VOL -
DQ8 ~ DQ15
tCAC
tCLZ
tRAC
OPEN DATA-OUT
DATA-OUT
tOFF
tOEZ
tOEZ
tRCS
WORD READ CYCLE
Page 10
KM416C1000C, KM416C1200C
CMOS DRAMKM416V1000C, KM416V1200C
tCRP
NOTE : DIN = OPEN
LOWER BYTE READ CYCLE
RAS
VIH -
VIL -
LCAS
VIH -
VIL -
A
VIH -
VIL -
W
VIH -
VIL -
OE
VIH -
VIL -
VOH -
VOL -
DQ0 ~ DQ7
COLUMN
ADDRESS
ROW
ADDRESS
tRAS
tRC
tRP
tCSH
tRSHtRCD
tCAS
tRAL
tRAD
tASR tRAH
tASC
tCAH
tCRP
tAA
tOEA
tCAC
tCLZ
tRAC
OPEN DATA-OUT
tOEZ
tOFF
tRCH
Don′t care
Undefined
tRPC
UCAS
VIH -
VIL -
OPEN
VOH -
VOL -
DQ8 ~ DQ15
tRCS
tRRH
Page 11
KM416C1000C, KM416C1200C
CMOS DRAMKM416V1000C, KM416V1200C
NOTE : DIN = OPEN
UPPER BYTE READ CYCLE
RAS
VIH -
VIL -
LCAS
VIH -
VIL -
A
VIH -
VIL -
W
VIH -
VIL -
OE
VIH -
VIL -
VOH -
VOL -
DQ0 ~ DQ7
COLUMN
ADDRESS
ROW
ADDRESS
tRAS
tRC
tCRP
tRP
tCSH
tRSHtRCD
tCAS
tRAL
tRAD
tASR tRAH tASC
tCAH
tCRP
tAA
tOEA
tCAC
tCLZ
tRAC
OPEN
DATA-OUT
tOEZ
tOFF
tRRH
tRCH
Don′t care
Undefined
UCAS
VIH -
VIL -
OPEN
VOH -
VOL -
DQ8 ~ DQ15
tCRP
tRPC
tRCS
Page 12
KM416C1000C, KM416C1200C
CMOS DRAMKM416V1000C, KM416V1200C
RAS
VIH -
VIL -
UCAS
VIH -
VIL -
A
VIH -
VIL -
W
VIH -
VIL -
OE
VIH -
VIL -
COLUMN
ADDRESS
ROW
ADDRESS
tRAS
tRC
tCRP
tRP
tCSH
tRSHtRCD
tCAS
tRAL
tRAD
tASR tRAH tASC
tCAH
tCRP
Don′t care
WORD WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
Undefined
LCAS
VIH -
VIL -
tWCS
VIH -
VIL -
DQ0 ~ DQ7
tDS
VIH -
VIL -
DQ8 ~ DQ15
tCRP
tCSH
tRSHtRCD
tCAS
tCRP
tWCH
tWP
tDH
DATA-IN
tDS
tDH
DATA-IN
Page 13
KM416C1000C, KM416C1200C
CMOS DRAMKM416V1000C, KM416V1200C
tCRP
RAS
VIH -
VIL -
UCAS
VIH -
VIL -
A
VIH -
VIL -
W
VIH -
VIL -
OE
VIH -
VIL -
COLUMN
ADDRESS
ROW
ADDRESS
tRAS
tRC
tRP
tRAL
tRAD
tASR tRAH tASC
tCAH
Don′t care
LOWER BYTE WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
Undefined
LCAS
VIH -
VIL -
tWCS
VIH -
VIL -
DQ0 ~ DQ7
tDS
VIH -
VIL -
DQ8 ~ DQ15
tCRP
tCSH
tRSHtRCD
tCAS
tWCH
tWP
tDH
DATA-IN
tCRP
tRPC
Page 14
KM416C1000C, KM416C1200C
CMOS DRAMKM416V1000C, KM416V1200C
RAS
VIH -
VIL -
UCAS
VIH -
VIL -
A
VIH -
VIL -
W
VIH -
VIL -
OE
VIH -
VIL -
COLUMN
ADDRESS
ROW
ADDRESS
tRAS
tRC
tCRP
tRP
tCSH
tRSHtRCD
tCAS
tRAL
tRAD
tASR tRAH tASC
tCAH
tCRP
Don′t care
UPPER BYTE WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
Undefined
LCAS
VIH -
VIL -
tWCS
VIH -
VIL -
DQ0 ~ DQ7
VIH -
VIL -
DQ8 ~ DQ15
tWCH
tWP
tDS
tDH
DATA-IN
tCRP
tRPC
Page 15
KM416C1000C, KM416C1200C
CMOS DRAMKM416V1000C, KM416V1200C
RAS
VIH -
VIL -
UCAS
VIH -
VIL -
A
VIH -
VIL -
W
VIH -
VIL -
OE
VIH -
VIL -
ROW
ADDRESS
tRAS
tRC
tCRP
tRP
tCSH
tRSHtRCD
tCAS
tRAL
tRAD
tASR tRAH tASC
tCRP
Don′t care
WORD WRITE CYCLE ( OE CONTROLLED WRITE )
NOTE : DOUT = OPEN
Undefined
LCAS
VIH -
VIL -
VIH -
VIL -
DQ0 ~ DQ7
VIH -
VIL -
DQ8 ~ DQ15
tCRP
tRSHtRCD
tCAS
tCRP
tRWL
tWP
tCWL
tDH
tDH
DATA-IN
COLUMN
ADDRESS
tOEH
tOED
tDS
tDS
DATA-IN
tCSH
tCAH
Page 16
KM416C1000C, KM416C1200C
CMOS DRAMKM416V1000C, KM416V1200C
RAS
VIH -
VIL -
UCAS
VIH -
VIL -
A
VIH -
VIL -
W
VIH -
VIL -
OE
VIH -
VIL -
COLUMN
ADDRESS
ROW
ADDRESS
tRAS
tRC
tRP
tRAL
tRAD
tASR tRAH tASC
tCAH
Don′t care
LOWER BYTE WRITE CYCLE ( OE CONTROLLED WRITE )
NOTE : DOUT = OPEN
Undefined
LCAS
VIH -
VIL -
tRWL
VIH -
VIL -
DQ0 ~ DQ7
tDS
VIH -
VIL -
DQ8 ~ DQ15
tCRP
tCSH
tRSHtRCD
tCAS
tCRP
tWP
tCWL
tDH
DATA-IN
tCRP
tRPC
tOEH
tOED
Page 17
KM416C1000C, KM416C1200C
CMOS DRAMKM416V1000C, KM416V1200C
RAS
VIH -
VIL -
UCAS
VIH -
VIL -
A
VIH -
VIL -
W
VIH -
VIL -
OE
VIH -
VIL -
COLUMN
ADDRESS
ROW
ADDRESS
tRAS
tRC
tCRP
tRP
tCSH
tRSHtRCD
tCAS
tRAL
tRAD
tASR tRAH tASC
tCAH
tCRP
Don′t care
UPPER BYTE WRITE CYCLE ( OE CONTROLLED WRITE )
NOTE : DOUT = OPEN
Undefined
LCAS
VIH -
VIL -
VIH -
VIL -
VIH -
VIL -
tCRP
tRWL
tWP
tCWL
tDS tDH
DATA-IN
tOEH
tOED
DQ0 ~ DQ7
DQ8 ~ DQ15
tRPC
Page 18
KM416C1000C, KM416C1200C
CMOS DRAMKM416V1000C, KM416V1200C
tRWL
RAS
VIH -
VIL -
UCAS
VIH -
VIL -
A
VIH -
VIL -
W
VIH -
VIL -
OE
VIH -
VIL -
COLUMN
ADDRESS
ROW
ADDR
tRAS
tRWC
tRP
tRSHtRCD
tCAS
tCSH
tRAD
tASR tRAH tASC tCAH
tCRP
Don′t care
WORD READ - MODIFY - WRITE CYCLE
Undefined
LCAS
VIH -
VIL -
VI/OH -
VI/OL -
DQ0 ~ DQ7
VI/OH -
VI/OL -
DQ8 ~ DQ15
tWP
tCWL
tDS tDH
tRSHtRCD
tCAS
tCRP
tAWD
tCWD
tOEA
tRWD
tOED
tOEZ
tRAC
tAA
tOEZ
tRAC
tAA
tDS
tOED
tDH
VALID
DATA-OUT
VALID
DATA-IN
VALID
DATA-OUT
VALID
DATA-IN
tCAC
tCLZ
tCAC
tCLZ
Page 19
KM416C1000C, KM416C1200C
CMOS DRAMKM416V1000C, KM416V1200C
tRWL
RAS
VIH -
VIL -
UCAS
VIH -
VIL -
A
VIH -
VIL -
W
VIH -
VIL -
OE
VIH -
VIL -
COLUMN
ADDRESS
ROW
ADDR
tRAS
tRWC
tRP
tCSH
tRAD
tASR tRAH tASC tCAH
tCRP
Don′t care
LOWER-BYTE READ - MODIFY - WRITE CYCLE
Undefined
LCAS
VIH -
VIL -
VI/OH -
VI/OL -
DQ0 ~ DQ7
VI/OH -
VI/OL -
DQ8 ~ DQ15
tWP
tCWL
tDS tDH
tRSH
tRCD
tCAS
tCRP
tAWD
tCWD
tOEA
tRWD
tOED
tOEZ
tRAC
tAA
VALID
DATA-OUT
VALID
DATA-IN
tRPC
tCAC
tCLZ
OPEN
Page 20
KM416C1000C, KM416C1200C
CMOS DRAMKM416V1000C, KM416V1200C
tCRP
tRWL
RAS
VIH -
VIL -
UCAS
VIH -
VIL -
A
VIH -
VIL -
W
VIH -
VIL -
OE
VIH -
VIL -
COLUMN
ADDRESS
ROW
ADDR
tRAS
tRWC
tRP
tRSHtRCD
tCAS
tCSH
tRAD
tASR tRAH tASC tCAH
tCRP
Don′t care
UPPER-BYTE READ - MODIFY - WRITE CYCLE
Undefined
LCAS
VIH -
VIL -
VI/OH -
VI/OL -
DQ0 ~ DQ7
VI/OH -
VI/OL -
DQ8 ~ DQ15
tWP
tCWL
tAWD
tCWD
tOEA
tRWD
tOEZ
tRAC
tAA
tDS
tOED
tDH
VALID
DATA-OUT
VALID
DATA-IN
tRPC
tCAC
tCLZ
OPEN
Page 21
KM416C1000C, KM416C1200C
CMOS DRAMKM416V1000C, KM416V1200C
RAS
VIH -
VIL -
UCAS
VIH -
VIL -
A
VIH -
VIL -
W
VIH -
VIL -
OE
VIH -
VIL -
COLUMN
ADDRESS
ROW
ADDR
tRASP
tRP
tRCD
tASR
tCRP
Don′t care
FAST PAGE MODE WORD READ CYCLE
Undefined
LCAS
VIH -
VIL -
VOH -
VOL -
DQ0 ~ DQ7
VOH -
VOL -
DQ8 ~ DQ15
tOEZ
tOFF
COLUMN
ADDRESS
tCAS tCAS tCAS tCAS
tCP tCP tCP
tRPC
tPC
tPC tPC
tRHCP
tCSH
tRCD
tCRP
tCAS tCAS tCAS tCAS
tCP tCP
tRPC
tRAD
tRAH tASC tCAH tCAH tCAH tASC tCAH
tRCS
tRCS
tOEA
tAA
tRCS
tRCH tRCH
tRCS
tRCH
tRCH
tRRH
tASC
COLUMN
ADDRESS
COLUMN
ADDR
VALID
DATA-OUT
tOEZ
tOFF
tOEA
tCPA
tAA
tCAC
tOEA
tCPA
tAA
tCAC
tOEA
tCPA
tAA
tCAC
VALID
DATA-OUT
VALID
DATA-OUT
VALID
DATA-OUT
tOEZ
tOFF
tOEZ
tOFF
tOEZ
tOFF
VALID
DATA-OUT
tOEZ
tOFF
VALID
DATA-OUT
VALID
DATA-OUT
VALID
DATA-OUT
tOEZ
tOFF
tOEZ
tOFF
tCLZ
tRAC
tCAC
tCAC
tCLZ
tRAC
¡ó
tASC
tCP
tRAL
Page 22
KM416C1000C, KM416C1200C
CMOS DRAMKM416V1000C, KM416V1200C
tCRP
tCRP
RAS
VIH -
VIL -
UCAS
VIH -
VIL -
A
VIH -
VIL -
W
VIH -
VIL -
OE
VIH -
VIL -
COLUMN
ADDRESS
ROW
ADDR
tRASP tRP
tRCD
tASR
Don′t care
FAST PAGE MODE LOWER BYTE READ CYCLE
Undefined
LCAS
VIH -
VIL -
VOH -
VOL -
DQ0 ~ DQ7
VOH -
VOL -
DQ8 ~ DQ15
tOEZ
tOFF
COLUMN
ADDRESS
tCAS tCAS tCAS tCAS
tCP tCP
tRPC
tPC tPC tPC
tRHCP
tCSH
tRAD
tRAH tASC tCAH tASC tCAH tCAH tASC tCAH
tRCS
tRCS
tOEA
tAA
tRCS
tRCH tRCH
tRCS
tRCH
tRCH
tRRH
tASC
COLUMN
ADDRESS
COLUMN
ADDR
VALID
DATA-OUT
tOEZ
tOFF
tOEA
tCPA
tAA
tCAC
tOEA
tCPA
tAA
tCAC
tOEA
tCPA
tAA
tCAC
VALID
DATA-OUT
VALID
DATA-OUT
VALID
DATA-OUT
tOEZ
tOFF
tOEZ
tOFF
tCLZ
tRAC
tCAC
¡ó
tRPC
OPEN
tRAL
tCP
Page 23
KM416C1000C, KM416C1200C
CMOS DRAMKM416V1000C, KM416V1200C
tCP
RAS
VIH -
VIL -
UCAS
VIH -
VIL -
A
VIH -
VIL -
W
VIH -
VIL -
OE
VIH -
VIL -
COLUMN
ADDRESS
ROW
ADDR
tRASP
tRP
tRCD
tASR
tCRP
Don′t care
FAST PAGE MODE UPPER BYTE READ CYCLE
Undefined
LCAS
VIH -
VIL -
VOH -
VOL -
DQ0 ~ DQ7
VOH -
VOL -
DQ8 ~ DQ15
COLUMN
ADDRESS
tCAS tCAS tCAS tCAS
tCP tCP
tRPC
tPC tPC tPC
tRHCPtCSH
tCRP
tRPC
tRAD
tRAH tASC tCAH tASC tCAH tCAH tCAH
tRCS
tRCS
tOEA
tAA
tRCS
tRCH tRCH
tRCS
tRCH
tRCH
tRRH
tASC
COLUMN
ADDRESS
COLUMN
ADDR
tOEA
tCPA
tOEA
tCPA
tOEA
tCPA
tOEZ
tOFF
VALID
DATA-OUT
tOEZ
tOFF
VALID
DATA-OUT
VALID
DATA-OUT
VALID
DATA-OUT
tOEZ
tOFF
tOEZ
tOFFtCAC
tCLZ
tRAC
OPEN
¡ó
tAA
tCAC
tAA
tCAC
tAA
tCAC
tRAL
tASC
Page 24
KM416C1000C, KM416C1200C
CMOS DRAMKM416V1000C, KM416V1200C
tASC
RAS
VIH -
VIL -
UCAS
VIH -
VIL -
A
VIH -
VIL -
W
VIH -
VIL -
OE
VIH -
VIL -
COLUMN
ADDRESS
ROW
ADDR
tRASP tRP
tRCD
tASR
tCRP
Don′t care
FAST PAGE MODE WORD WRITE CYCLE ( EARLY WRITE )
Undefined
LCAS
VIH -
VIL -
VIH -
VIL -
DQ0 ~ DQ7
VIH -
VIL -
DQ8 ~ DQ15
tCRP
tPC tPC
tRHCP
tRAD
tRAH tCAH tCAH tCAHtASC
VALID
DATA-IN
tDS
¡ó
COLUMN
ADDRESS
COLUMN
ADDRESS
tCAS
tCP
tCAS
tCP
tCAS
tRSH
¡ó
tRCD
tCRP
tPC tPC
tCAS
tCP
tCAS
tCP
tCAS
tRSH
¡ó
tCSH
tASC
¡ó
¡ó
tWP
tWCS tWCH
tWP
tWCS tWCH
tWP
tWCS tWCH
¡ó
¡ó
¡ó
VALID
DATA-IN
VALID
DATA-IN
¡ó
¡ó
tDH tDS tDH tDS tDH
VALID
DATA-IN
VALID
DATA-IN
VALID
DATA-IN
¡ó
¡ó
tDH tDH tDHtDStDStDS
NOTE : DOUT = OPEN
tRAL
Page 25
KM416C1000C, KM416C1200C
CMOS DRAMKM416V1000C, KM416V1200C
RAS
VIH -
VIL -
UCAS
VIH -
VIL -
A
VIH -
VIL -
W
VIH -
VIL -
OE
VIH -
VIL -
COLUMN
ADDRESS
ROW
ADDR
tRASP tRP
tASR
tCRP
Don′t care
FAST PAGE MODE LOWER BYTE WRITE CYCLE ( EARLY WRITE )
Undefined
LCAS
VIH -
VIL -
VIH -
VIL -
DQ0 ~ DQ7
VIH -
VIL -
DQ8 ~ DQ15
tRPC
tRHCP
tRAD
tRAH tCAH tCAH tASC tCAHtASC
VALID
DATA-IN
tDS
¡ó
COLUMN
ADDRESS
COLUMN
ADDRESS
tRCD
tCRP
tPC tPC
tCAS
tCP
tCAS
tCP
tCAS
tRSH
¡ó
tCSH
tASC
¡ó
¡ó
tWP
tWCS tWCH
tWP
tWCS tWCH
tWP
tWCS tWCH
¡ó
¡ó
¡ó
VALID
DATA-IN
VALID
DATA-IN
¡ó
¡ó
tDH tDS tDH tDS tDH
NOTE : DOUT = OPEN
¡ó
tRAL
Page 26
KM416C1000C, KM416C1200C
CMOS DRAMKM416V1000C, KM416V1200C
RAS
VIH -
VIL -
UCAS
VIH -
VIL -
A
VIH -
VIL -
W
VIH -
VIL -
OE
VIH -
VIL -
COLUMN
ADDRESS
ROW
ADDR.
tRASP tRP
tASR
tCRP
Don′t care
FAST PAGE MODE UPPER BYTE WRITE CYCLE ( EARLY WRITE )
Undefined
LCAS
VIH -
VIL -
VIH -
VIL -
DQ0 ~ DQ7
VIH -
VIL -
DQ8 ~ DQ15
tRPC
tRHCP
tRAD
tRAH tCAH tCAH tASC tCAHtASC
VALID
DATA-IN
tDS
¡ó
COLUMN
ADDRESS
COLUMN
ADDRESS
tRCD
tCRP
tPC tPC
tCAS
tCP
tCAS
tCP
tCAS
tRSH
¡ó
tCSH
tASC
¡ó
¡ó
tWP
tWCS tWCH
tWP
tWCS tWCH
tWP
tWCS tWCH
¡ó
¡ó
¡ó
VALID
DATA-IN
VALID
DATA-IN
¡ó
¡ó
tDH tDS tDH tDS tDH
NOTE : DOUT = OPEN
¡ó
¡ó
tRAL
Page 27
KM416C1000C, KM416C1200C
CMOS DRAMKM416V1000C, KM416V1200C
RAS
VIH -
VIL -
UCAS
VIH -
VIL -
A
VIH -
VIL -
W
VIH -
VIL -
OE
VIH -
VIL -
VI/OH -
VI/OL -
DQ0 ~ DQ7
ROW
ADDR
tCSH
tRASP
tRP
tASR
Don′t care
FAST PAGE MODE WORD READ-MODIFY-WRITE CYCLE
Undefined
tRCD tCP
tRAD
tCAH
tWP
tDH
COL.
ADDR
COL.
ADDR
tCAS
tCAS
tCRP
tASC
tCAH
tRAL
tRCS
tCWL
tCWD
tAWD
tRWD
tCWD
tAWD
tCWL
tAA
tRAC
tOEA
tCLZ
tCAC
tOEZ
tCPWD
tOED
tASC
tCLZ
tOEA
tCAC
tAA
tDH
tOED
tRWL
LCAS
VIH -
VIL -
tRCD tCP
tCAS
tCAS
tCRP
tCRP
tCRP
VI/OH -
VI/OL -
DQ8 ~ DQ15
VALID
DATA-OUT
tDH
tAA
tRAC
tCLZ
tCAC
VALID
DATA-IN
VALID
DATA-OUT
VALID
DATA-IN
tCLZ
tCAC
tAA
tDH
tOEZ
tOED
tDS
tDS
tDS
tOEZ
tOEZ
VALID
DATA-OUT
VALID
DATA-IN
VALID
DATA-OUT
VALID
DATA-IN
tDS
tPRWC
tRSH
tWP
tRCS
tRAH
tOED
Page 28
KM416C1000C, KM416C1200C
CMOS DRAMKM416V1000C, KM416V1200C
RAS
VIH -
VIL -
UCAS
VIH -
VIL -
A
VIH -
VIL -
W
VIH -
VIL -
OE
VIH -
VIL -
VI/OH -
VI/OL -
DQ0 ~ DQ7
ROW
ADDR
tCSH
tRASP
tRP
tASR
Don′t care
FAST PAGE MODE LOWER BYTE READ - MODIFY - WRITE CYCLE
Undefined
tRAD
tCAH
tWP
tDH
COL.
ADDR
COL.
ADDR
tASC
tCAH
tRAL
tRCS
tCWL
tCWD
tAWD
tRWD
tWP
tCWD
tAWD
tCWL
tAA
tRAC
tOEA
tCLZ
tCAC
tOEZ
tCPWD
tOED
tASC
tCLZ
tOEA
tCAC
tAA
tDH
tOED
tRWL
LCAS
VIH -
VIL -
tRCD
tCP
tCAS tCAS
tCRP
tCRP
tCRP
VI/OH -
VI/OL -
DQ8 ~ DQ15
tDS
tOEZ
VALID
DATA-OUT
VALID
DATA-IN
VALID
DATA-OUT
VALID
DATA-IN
tDS
tRPC
tRSHtPRWC
OPEN
tRCS
tRAH
Page 29
KM416C1000C, KM416C1200C
CMOS DRAMKM416V1000C, KM416V1200C
RAS
VIH -
VIL -
VIH -
VIL -
A
VIH -
VIL -
W
VIH -
VIL -
OE
VIH -
VIL -
VI/OH -
VI/OL -
DQ0 ~ DQ7
ROW
ADDR
tCSH
tRASP
tRP
tASR
Don′t care
FAST PAGE MODE UPPER BYTE READ - MODIFY - WRITE CYCLE
Undefined
tRAD
tCAH
tWP
tDH
COL.
ADDR
COL.
ADDR
tASC
tCAH
tRAL
tRCS
tCWL
tCWD
tAWD
tRWD
tWP
tCWD
tAWD
tCWL
tAA
tRAC
tOEA
tCLZ
tCAC
tOEZ
tCPWD
tOED
tASC
tCLZ
tOEA
tCAC
tAA
tDH
tOED
tRWL
VIH -
VIL -
tRCD
tCP
tCAS tCAS
tCRP
tCRP
tCRP
VI/OH -
VI/OL -
DQ8 ~ DQ15
tDS
tOEZ
VALID
DATA-OUT
VALID
DATA-IN
VALID
DATA-OUT
VALID
DATA-IN
tDS
tRPC
tRSHtPRWC
OPEN
UCAS
LCAS
tRCS
tRAH
Page 30
KM416C1000C, KM416C1200C
CMOS DRAMKM416V1000C, KM416V1200C
tCSR
OPEN
RAS
VIH -
VIL -
UCAS
VIH -
VIL -
A
VIH -
VIL -
ROW
ADDR
tRC
tRP
tASR
tCRP
RAS - ONLY REFRESH CYCLE
LCAS
VIH -
VIL -
tRAS
tRAH
NOTE : W, OE , DIN = Don′t care
DOUT = OPEN
tRPC
tCRP
CAS - BEFORE - RAS REFRESH CYCLE
NOTE : OE , A = Don′t care
RAS
VIH VIL -
UCAS
VIH VIL -
tRC
tRP
LCAS
VIH VIL -
tRAS
tRPC
tCP
tCRP
tCHR
tCP
tCSR
tCHR
tOFF
OPEN
VOH VOL -
DQ0 ~ DQ7
VOH -
VOL -
DQ8 ~ DQ15
Don′t care
tRP
Undefined
Page 31
KM416C1000C, KM416C1200C
CMOS DRAMKM416V1000C, KM416V1200C
tOEZ
DATA-IN
DATA-OUT
tRP
RAS
VIH -
VIL -
UCAS
VIH -
VIL -
A
VIH -
VIL -
W
VIH -
VIL -
OE
VIH -
VIL -
ROW
ADDRESS
tRAS
tRC
tCHRtRCD tRSH
tRAD
tASR tRAH tASC
tCRP
Don′t care
HIDDEN REFRESH CYCLE ( READ )
Undefined
LCAS
VIH -
VIL -
VOH -
VOL -
DQ0 ~ DQ7
VOH -
VOL -
DQ8 ~ DQ15
tRSHtRCD
tCRP
tWRH
COLUMN
ADDRESS
tOEA
tRAS
tRC
tCHR
tCAH
tRCS
tAA
tRAC
tCLZ
tCAC
DATA-OUT
tOFF
OPEN
OPEN
tRP
tRAL
Page 32
KM416C1000C, KM416C1200C
CMOS DRAMKM416V1000C, KM416V1200C
tWCS
tRP
RAS
VIH -
VIL -
UCAS
VIH -
VIL -
A
VIH -
VIL -
W
VIH -
VIL -
OE
VIH -
VIL -
ROW
ADDRESS
tRAS
tRC
tCHR
tRCD
tRSH
tRAD
tASR tRAH
tASC
tCRP
Don′t care
HIDDEN REFRESH CYCLE ( WRITE )
Undefined
LCAS
VIH -
VIL -
VIH -
VIL -
DQ0 ~ DQ7
VIH -
VIL -
DQ8 ~ DQ15
tRSHtRCD
tCRP
tWRH
COLUMN
ADDRESS
tRAS
tRC
tCHR
tCAH
tWRP
tDS
NOTE : DOUT = OPEN
tWP
tWCH
DATA-IN
tDH
tDS
DATA-IN
tDH
tRP
tRAL
Page 33
KM416C1000C, KM416C1200C
CMOS DRAMKM416V1000C, KM416V1200C
tCSR
OPEN
CAS - BEFORE - RAS SELF REFRESH CYCLE
NOTE : OE , A = Don′t care
RAS
VIH VIL -
UCAS
VIH VIL -
tRPS
LCAS
VIH VIL -
tRAS
tRPC
tCP
tRPC
tCSR
tOFF
OPEN
VOH VOL -
DQ0 ~ DQ7
VOH -
VOL -
DQ8 ~ DQ15
tCHS
tCP
tCHS
tRP
Don′t care
Undefined
Page 34
KM416C1000C, KM416C1200C
CMOS DRAMKM416V1000C, KM416V1200C
42 SOJ 400mil
0.400 (10.16)
0.435 (11.06)
0.445 (11.30)
1.080 (27.43)
1.070 (27.19)
MAX
1.091 (27.71)
MAX
0.148 (3.76)
0.032 (0.81)
0.026 (0.66)
0.021 (0.53)
0.015 (0.38)
0.027 (0.69)
0.012 (0.30)
0.006 (0.15)
0.360 (9.15)
0.380 (9.65)
MIN
#42
#1
0.0375 (0.95)
0.050 (1.27)
Units : Inches (millimeters)
50(44) TSOP(II) 400mil
Units : Inches (millimeters)
MAX
0.047 (1.20)
MIN
0.002 (0.05)
0.018 (0.45)
0.010 (0.25)
0.0315 (0.80)0.034 (0.875)
0.821 (20.85)
0.829 (21.05)
0.841 (21.35)
MAX
0.010 (0.25)
0.004 (0.10)
0.400 (10.16)
0.471 (11.96)
0.455 (11.56)
0~8
0.030 (0.75)
0.018 (0.45)
TYP
0.010 (0.25)
O
PACKAGE DIMENSION
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