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Kawasaki LSI
9M Classification CAM PRELIMINARY
Version 1.2.0 Confidential
Contents
1. Features.........................................................................................1
2. Block Diagram...............................................................................2
3. Pin Descriptions ...........................................................................4
3.1. Pin Assignment (T.B.D.)..............................................................................4
3.2. Pin Descriptions..........................................................................................4
4. Functional Descriptions...............................................................7
4.1. Overview.....................................................................................................7
4.2. Segment Structure......................................................................................7
4.3. Output Format.............................................................................................7
4.4. CAM Table Example....................................................................................8
4.5. CNTL Bus (CNTL[15:0])..............................................................................9
4.6. Timing Chart..............................................................................................10
5. Command Descriptions..............................................................13
6. Register.......................................................................................15
7. Product Information ...................................................................15
7.1. Ordering Information.................................................................................15
7.2. Package Outline........................................................................................15
8. Electrical Characteristics...........................................................16
8.1. Absolute Maximum Rating ........................................................................16
8.2. Operating Range.......................................................................................16
8.3. DC Characteristics....................................................................................16
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Kawasaki LSI
9M Classification CAM PRELIMINARY
Version 1.2.0 1 Confidential
1. Features
Kawasaki’s KE5BCCA9M is a high-performance Content Addressable Memory (CAM). The
following features enable high-speed and high-density “switching," “address filtering,” and "packet
classification" applications required for internetworking switching and routing:
•
Density: 9.4Mbits Ternary or Binary
•
Configurable table Size:
72-bit x 128K, 144-bit x 64K, 288-bit x 32K, or 576-bit x 16K(Ternary or Binary)
•
Mixed table size configuration:
Selected by each bank (8banks). Each bank can be individually configured as a 72-bit x 16K,
144-bit x 8K, 288-bit x 4K, or 576-bit x 2K(Ternary or Binary) table.
•
Input Clock rate: 83MHz/100MHz/125MHz clock (CLK)
•
High-speed search and deterministic latency:
-125: Sustained 125MLPS, (maximum key data width T.B.D.), (latency T.B.D.)
-100: Sustained 100MLPS, 10ns per 144-bit maximum, (latency T.B.D.)
- 83: Sustained 83MLPS, 12ns per 144-bit maximum, 3 cycles latency
•
Dual-port architecture
•
72-bit I/O Port Data Bus:
144-bit per 8(T.B.D.)/10/12ns write-in throughput is possible. 72-bit I/O port data bus is also
configurable as a 40-bit wide bus.
•
24-bit Output Port: Search results are output
•
Multi-hit support (Highest Hit Address output)
•
18 x 72-bit Global MASK Registers
•
Weighted Search without data sorting
•
Effective Command Set for Table Management:
- Purge (Invalidate) all the hit entries in one Cycle
- Automatic Learning
•
Cascading:
Up to 8pcs --- Glueless without degradation in performance --- 72-bit x 512k table
Cascadable up to 32pcs --- Maximum 72-bit x 2M table
•
External SRAM direct connection (Address bypass to SRAM)
•
Space-saving package: 324-pin BGA (27mm x 27mm)
•
Power supply: 1.2V (core), 2.5V or 1.8V(I/O) --- Selectable I/O voltage (T.B.D.)
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Kawasaki LSI
9M Classification CAM PRELIMINARY
Version 1.2.0 2 Confidential
2. Block Diagram
Fig. 2-1 Functional Block Diagram
CEN
RWN
SAD
CLK
RSTN
OEDATN
DAT[63:0]
EDAT[7:0]
DATWDT
CNTL[15:0]
PHOUN[1:0]
PHODN[1:0]
PMIN
PMON
FLIN[6:0]
FLON[1:0]
BHIDN
BHODN
BHIUN
BHOUN
BFLIN
SSHON
SMON
ODBYP
OEODN
OD[23:0]
PHIUN[6:0]
PHIDN[6:0]
INPMD
LMSTN
I/O
Port
Control
Control and
Status Registers
Pipeline
Execution
Control
Global Mask
Registers
CAM Control
Decoder
72bits x 131072
CAM
8 Banks
(72bitsx16Kx8)
structure
Mixable with
72bits x 16384
144bits x 8192
288bits x 4096
576bits x 2048
Empty Bit
Flag Control Output Port Control
Priority Encoder
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Kawasaki LSI
9M Classification CAM PRELIMINARY
Version 1.2.0 3 Confidential
Kawasaki’s KE5BCCA9M has the following components:
•
I/O Port Control
I/O port to input search key data and read/write data. I/O port data bus can be configured as a
72-bit or 40-bit wide bus.
•
Pipeline Execution Control
Controls operation with pipeline through the CNTL [15:0].
•
Control/Status Register
Defines CAM functions.
•
Mask Registers
18 Global Mask Registers in total: 16 72-bit wide user-definable registers and 2 fixed registers
(ALL 0 and ALL 1) for search and write operations.
•
Search Logic/Control Logic
Controls CAM functions.
•
CAM
72-bit x 128k CAM data table partitioned into 8 banks. Each of which can be configured as
ternary or binary and in table width of 72-bit, 144-bit, 288-bit, or 576-bit. The search operations
can be performed simultaneously on multiple banks. By way of these features, various kinds of
data for Layer-2, 3 and 4 can be stored in one device and managed in different ways.
•
Output Port Control
Controls output port, which outputs search results. The DAT data bypass function is provided
for the external SRAM access through this CAM device.
•
Flag Logic
Controls the flag status (e.g. Full and Hit). Interfaces with other devices in a cascaded system.
When the CAM table is divided into multiple blocks, the status of the searched block is output.
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Kawasaki LSI
9M Classification CAM PRELIMINARY
Version 1.2.0 4 Confidential
3. Pin Descriptions
3.1. Pin Assignment (T.B.D.)
Pin assignment is backward compatible with 4.7M CAM (KE5BCCA4M). OD[23] is assigned to the
NC pin of 4.7M CAM, and CNTL[15:14] to the GND pins.
VDDQ (I/O): 2.5V or 1.8V --- Selectable I/O voltage (T.B.D.)
VDD (core): 1.2V
3.2. Pin Descriptions
Pin Name Description Attribute Function
RSTN Hardware Reset Input RSTN low resets the device.
CLK Clock Input CLK is the clock input. All operations are synchronized with CLK.
The internal PLL generate the double rate clock of CLK, called
CLKX2 and all input signals are referenced to the CLKX2.
INPMD Input Mode Input When all input signals are referenced to only CLK rising edge;
not falling edge, fix INPMD high.
DAT[63:0] I/O Port
Data Bus
Input/
Output
Tristate
DAT[63:0] is a 64-bit bi-directional data bus for read/write of
CAM memory and registers. RWN controls the bus direction.
EDAT[7:0] EXTRA Bit Data
Bus
Input/
Output
Tristate
EDAT[7:0] is a 8-bit bi-directional data bus for read/write of
EXTRA bits of CAM memory and registers. RWN controls the
bus direction.
DATWDT I/O Port Data Bus
Width
Input DATWDT defines DAT[63:0] width. Fix low to employ all
DAT[63:0]; fix high not to employ DAT[63:32] and to employ
DAT[31:0] with SAD as a substitute for DAT[63:0].
CNTL[15:0] Control Bus Input CNTL[15:0] is the 16-bit control bus to control the device. The
search operations, the command assertions, and the register
accesses are invoked corresponding to CNTL[15:0].
SAD Sub Address Input SAD assigns DAT[31:0] to internal 64-bit data bus when
DAT[63:32] is unused (DATWDT=high). When SAD is low,
DAT[31:0] is assigned to lower 32-bit; when high, it is assigned
to upper 32-bit.
CEN Device Enable Input CEN low invokes operations such as read/write, search and
command.
RWN Read/Write Input RWN determines the direction of the I/O Port data bus
DAT[63:0] and that of the EXTRA bit data bus EDAT[7:0]. RWN
low selects a write cycle and RWN high selects a read cycle.
OEDATN I/O Port Data Bus
Output Enable
Input OEDATN is output enable signal for DAT[63:0] and EDAT[7:0].
This signal is also referenced to CLK rising edge.
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Kawasaki LSI
9M Classification CAM PRELIMINARY
Version 1.2.0 5 Confidential
Pin Name Description Attribute Function
OD[23:0] Output Port
Output
Output
Tristate
OD[23:0] is a 24-bit output port. Valid flag, Device ID, Highest
Hit Address (HHA), or Highest Empty Address (HEA) are output.
OEODN Output Port
Output Enable
Input OEODN is output enable signal for OD[23:0]. This signal is also
referenced to CLK rising edge.
ODBYP Output Port
Bypass Control
Input When ODBYP is high, the input data to I/O Port (DAT bus) is
output to Output Port (OD bus).
LMSTN Weighted Search
Status Output
Output LMSTN stays low during the execution of Weighted Search.
SSHON Synchronous Hit
Output
Output SSHON outputs the search results in the device synchronous
with CLK. SSHON low indicates a hit (match) and SSHON high
no entry hit (miss) in the search operation. The SSHON of the
bottom device (Last Device) indicates the hit of a cascaded
system.
SMON Synchronous
Multi-Hit
Output
Output SMON outputs the search results in the device synchronous with
CLK. SMON low indicates a multi-hit (multiple matches) and
SMON high no multi-hit in the search operation.
SMON shows the multiple hit status of the device and does not
show the system's status even in the cascaded system.
PHIDN[6:0] Priority Hit
Down Input
Input PHIDN[6:0] connects devices for cascading operations. Refer to
the data sheet.
PHODN[1:0] Priority Hit
Down Output
Output PHODN[1:0] is used for cascade connection. PHODN[1:0] low
indicates a hit (match) and PHODN[1:0] high no hit entry (miss)
in the search operation.
PHIUN[6:0] Priority Hit Up
Input
Input PHIUN[6:0] connects devices for cascading operations. Refer to
the data sheet.
PHOUN[1:0] Priority Hit Up
Output
Output PHOUN[1:0] is used for cascade connection. PHOUN[1:0] low
indicates a hit (match) and PHOUN[1:0] high no hit entry (miss)
in the search operation.
PMIN Priority Multi-Hit
Input
Input PMIN connects devices for cascading operations. Refer to the
data sheet.
PMON Priority Multi-Hit
Output
Output PMON is a output pin that outputs the search results. PMON low
indicates a multi-hit (multiple matches) and PMON high no multihit in the search operation.
The PMON pin of the lowest priority device (Last Device)
indicates the hit signal of the cascaded system.
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Kawasaki LSI
9M Classification CAM PRELIMINARY
Version 1.2.0 6 Confidential
Pin Name Description Attribute Function
FLIN[6:0] Full Flag input Input FLIN[6:0] is used in the cascaded system. Refer to the data
sheet.
FLON[1:0] Full Flag Output Output FLON[1:0] outputs the full status of the CAM memory.
FLON[1:0] low indicates all entries in the CAM memory are filled
with valid entries (full status) precluding a new registration.
The FLON pin of the lowest priority device (Last Device)
indicates the hit signal of the cascade configuration.
BHIDN Block Priority
Hit Down input
Input BHIDN is used in a cascaded system composed by more than 8
devices.
BHODN Block Priority Hit
Down output
Output BHODN is used in a cascaded system composed by more than
8 devices.
BHIUN Block Priority Hit
Up input
Input BHIUN is used in a cascaded system composed by more than 8
devices.
BHOUN Block Priority Hit
Up output
Output BHOUN is used in a cascaded system composed by more than
8 devices.
BFLIN Block Empty
Priority input
Input BFLIN is used in a cascaded system composed by more than 8
devices.
PLLEN PLL Enable Input PLLEN enables internal PLL. Refer to the data sheet for detail.
VCOSEL VCO Select Input Input VCOSEL selects internal VCO (Voltage Controlled Oscillator).
Refer to the data sheet for detail.
MACROOPSEL Macro Option
Select
Input MACROOPSEL defines parameters of internal circuitry. Refer to
the data sheet for detail.
TESTMODE[1:0] Test Mode Select Input TESTMODE[1:0] select test mode of internal circuitry. Refer to
the data sheet for detail.
IOVDDSEL
(T.B.D.)
I/O VDD Level
Select Input
Input IOVDDSEL defines I/O power supply voltage level as 2.5V or
1.8V. Fix high for 2.5V and low for 1.8V. (T.B.D.)
VDDQ
(T.B.D.)
Power (I/O) Power I/O power supply: 2.5V ± 5% or 1.8V ± 5%
(T.B.D.)
VDD Power (core) Power Power supply: 1.2V ± 5%
GND Ground Ground Ground
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Kawasaki LSI
9M Classification CAM PRELIMINARY
Version 1.2.0 7 Confidential
4. Functional Descriptions
4.1. Overview
Kawasaki’s KE5BCCA9M has a dual-port architecture: I/O port and Output port. The I/O port is for
search key data input and command input. The search results are output through the Output port.
Commands are asserted through the CNTL[15:0] bus. Read/write of stored data and search key
data are provided through DAT[63:0] and EDAT[7:0]. This 72-bit bus (DAT[63:0] and EDAT[7:0]) can
be defined as 72-bit or 40-bit.
The CAM table consists of 8 banks, each of which can be configured as Ternary and Binary and in
table widths of 72-bit, 144-bit, 288-bit, or 576-bit. The search operation can be performed
simultaneously on multiple banks of the same configuration.
The CAM also has the function called Weighted Search without data sorting. Which is regardless of
the order of the data stored, the most weighted entry is output when a search results in multiple hit.
4.2. Segment Structure
4.3. Output Format
Local Data
Empty
Bit
Local Mask Data
Hit
Flag
Data 64bitsExtra 8bits
71 64 63 0
Classification
CAM
HHA/HEA[15:0]
0
Device ID[4:0]
HHA/HEA Flag (0:HHA, 1:HEA)
OEODN
OD[23:0]
SSHON
SMON
15
DEVID
16202123 22
Valid Flag (0:Valid, 1:Invalid)
HHA[16]/HEA[16]
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9M Classification CAM PRELIMINARY
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4.4. CAM Table Example
#0
Logical Bank
#1
#3
#4
#5
#0, #1 and #2
Physical Bank
#0 and #3
#4 and #5
#6
#7
72bits table for Layer 3 classification database #1
Description
72bits table for Layer 3 classification database #2
144bits table for Layer 3 and Layer 4 classification
288bits table for flow based classification
576bits table for policy based classification
#2
#2 and #3 72bits table for Layer 3 classification database #3
CAM table configuration
CAM
Logical Bank0
Logical Bank2
72bits x 16K
Logical Bank1
Logical Bank2
72bits x 16K
Physical Bank #0
Logical Bank4
288bits x 4K
Logical Bank5
576bits x 2K
Logical Bank0
Logical Bank1
72bits x 16K
Logical Bank3
288bits x 4K
Logical Bank3
288bits x 4K
Logical Bank0
72bits x 16K
Physical Bank #1 Physical Bank #2 Physical Bank #3
Physical Bank #4 Physical Bank #5 Physical Bank #6 Physical Bank #7
CAM Table 72bits x 16K entries x 8 banks
Hit/Miss
Multiple Hit
Hit Address
Logical Bank Select Signal Global Mask Select SignalKeydata 72bits/144bits
Global Mask Register
MASK 0
MASK 1
MASK 17
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9M Classification CAM PRELIMINARY
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4.5. CNTL Bus (CNTL[15:0])
The CNTL bus (CNTL[15:0]) defines the operation. The function of the CNTL bus is classified into
four categories as follows:
•
Control of a search operation
•
Control of a Weighted Search operation
•
Control of a command
•
Control of an access to a register
As shown below, CNTL[13:12] defines the operation, and CNTL[11:5] defines the parameters, and
CNTL[4:0] defines the Mask Register number. Also, the most significant 2bits of Segment number
are specified onto CNTL[15:14]. As for the parameters and the Mask Register number, refer to the
data sheet.
0 0 Address Field
15
Global
Mask
Register control
14 13 12 11 5 4 0
10
Extra
Segment
Field
0 0 Operation Field
15
Global
Mask
Command control
14 13 12 11 5 4 0
1 1 Search Operation Field
15
Global
Mask
Weighted Search
control
14 13 12 11 5 4 0
0 0
Extra
Segment
Field
0 1 Search Operation Field
15
Global
Mask
Normal Search control
14 13 12 11 5 4 0
0
0
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9M Classification CAM PRELIMINARY
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4.6. Timing Chart
(1) Timing Chart of 72-bit/144-bit Search
*1: This shows the case that both EXL[1:0] and CSM of the CNTL Register are set to ‘00’ and
‘0’ respectively. Refer to Datasheet for other cases.
*2: This shows the case that EXL[1:0] of the CNTL Register is set to ‘00’. Refer to Datasheet
for other cases.
*3: This shows the case that both EXL[1:0] and ODL of the CNTL Register are set to ‘00’ and
‘0’ respectively. Refer to Datasheet for other cases.
CLK
Internal
CLKX2
CEN
CNTL[15:0]
SAD
RWN
Latency 4 Cycle
(*2)
Latency 3 Cycle (*1)
#0
#n
#n
Tpd
Tpd
Hit #2n & #2n+1
#0
DAT[63:0]
EDAT[7:0]
SRCH
SEG
#n
SEG
#n
72bits Search
AND
SRCH
SRCH
AND
SRCH
SRCH
SEG
#1
SEG
#1
SEG
#2n
SEG
#2n
SEG
#2n+1
SEG
#2n+1
SEG
#0
SEG
#0
144bits Search 144bits Search
SSHON
SMON
OD[23:0]
Multiple
#2n & #2n+1
Latency 4 Cycle (*3)
#n
Tpd
#0
INDEX
#2n & #2n+1
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9M Classification CAM PRELIMINARY
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(2) Timing Chart of 576-bit Search
*1: This shows the case that both EXL[1:0] and CSM of the CNTL Register are set to ‘00’ and
‘0’ respectively. Refer to Datasheet for other cases.
*2: This shows the case that EXL[1:0] of the CNTL Register is set to ‘00’. Refer to Datasheet
for other cases.
*3: This shows the case that both EXL[1:0] and ODL of the CNTL Register are set to ‘00’ and
‘0’ respectively. Refer to Datasheet for other cases.
CLK
Internal
CLKX2
CEN
CNTL[15:0]
SAD
RWN
Latency 4 Cycle (*2)
Latency 3 Cycle (*1)
&2 &3#0
Tpd
Tpd
DAT[63:0]
EDAT[7:0]
AND
SRCH
SEG
#1
AND
SRCH
AND
SRCH
SEG
#3
SEG
#2
576bits Search
SSHON
SMON
OD[23:0]
Latency 4 Cycle (*3) Tpd
SRCH
SEG
#0
AND
SRCH
SEG
#5
AND
SRCH
AND
SRCH
SEG
#7
SEG
#6
AND
SRCH
SEG
#4
#0
#0
&2 &3
&2 &3
&4 &5
&4 &5
&4 &5
HIT &6 &7
Multiple
&6 &7
INDEX
&6 &7
SEG
#1
SEG
#3
SEG
#2
SEG
#0
SEG
#5
SEG
#7
SEG
#6
SEG
#4
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Kawasaki LSI
9M Classification CAM PRELIMINARY
Version 1.2.0 12 Confidential
(3) Timing Chart of Ternary CAM R/W
*1: This shows EXL[1:0] of the CNTL Register is set to ‘00’. Refer to datasheet for other
cases.
Latency 3 Cycle
(*1)
Latency 3 Cycle
(*1)
CLK
Internal
CLKX2
CEN
CNTL[15:0]
SAD
DAT[63:0]
EDAT[7:0]
Local
Data1
RWN
Local
Data1
MEM
INC
MEM
Local
Mask
Data3
Local
Mask
Data3
Local
Data3
Local
Data3
MEM
INC
Local
Data0
Local
Data0
OEDATN
Tpd
Tpd
Local
Mask
Data0
Local
Mask
Data0
MEM
Local
Mask
Data1
Local
Mask
Data1
MEM
Local
Data2
Local
Data2
MEM
INC
MEM
INC
MEM
Local
Mask
Data2
Local
Mask
Data2
1 UNIT (144bits Write) 1 UNIT (72bits Write)
MEM
INC
MEM
Local
Mask
Data4
Local
Mask
Data4
Local
Data4
Local
Data4
1 UNIT (Read) 1 UNIT (Read)
Local Data Local Mask Data Local Data Local Mask Data Local Data Local Mask Data Local Data Local Mask Data
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5. Command Descriptions
Command
Group
Command name
CNTL[15:0]
Cycle
count
Function Description
Reset
SRST
(0000_0000_0000_0000)
2
Software
reset
Execute Device reset as with the RSTN low.
The flag pins are set as follows:
PHOUN[1:0]=High, PHODN[1:0]=High,
PMON=High, FLON[1:0]=High, SSHON=High,
SMON=High, LMSTN=High
Configuration
STR_DEVID
(0000_0001_0000_0000)
1
DEVID
mode start
Enter the DEVID mode for the Device ID
registration in a cascaded system.
END_DEVID
(0000_0010_0000_0000)
1
DEVID
mode end
Exit the DEVID mode.
NXT_PR
(0000_0011_0000_0000)
1
Shift
DEVID
priority
Shift the DEVID priority to the next device in the
DEVID mode.
Search
SRCH
(EE01_QRSS_TTTU_UUUU)
1 Search
Execute normal search.
Refer to the data sheet for E, Q, R, S, T, and U
field.
WT_SRCH
(0011_Q0SS_TTTU_UUUU)
1 Search
Execute Weighted Search.
Refer to the data sheet for Q, S, T, and U field.
CAM table
PRG_AL
(0000_0100_0000_0000)
1 Purge
All entries become empty (inactive).
PRG_HIT
(0000_0101_0000_0000)
1 Purge
All hit Entries become empty (inactive). This
command is effective only for the last searched
Logical Bank.
PRG_HHA
(0000_0110_0000_0000)
1 Purge
The CAM Entry designated by the HHA
Register becomes empty (inactive). In a
cascaded system, the hit priority must be fixed
prior to the command execution. This command
is effective only for the last searched Logical
Bank.
PRG_DA
(0000_0111_0000_0000)
1 Purge
The CAM Entry designated directly through
DAT[31:0] becomes empty (inactive). Refer to
the data sheet.
GEN_FL
(0000_1110_TTT0_0000)
1
Update the
HEA
address
Update empty status of the CAM table, which
means the HEA Register and FLON[1:0] are
updated. T field specifies the Logical Bank.
Refer to the data sheet.
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9M Classification CAM PRELIMINARY
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*1: When the Store command is executed for a Binary CAM Bank, 1-cycle is required; but
when it executed for a Ternary CAM Bank, 2-cycle is required.
Command
Group
Command name
CNTL[15:0]
Cycle
count
Function Description
Store
STR_AR
(EE00_1000_SSTU_UUUU)
1 or 2
*1
Store
Store data of the CMP Register to a CAM Entry
designated by the AR Register. S field specifies
the number of both CMP Register and
Segment. Refer to the data sheet for E, S, T,
and U field.
STR_HHA
(EE00_1001_SS0U_UUUU)
1 or 2
*1
Store
Store data of the CMP Register to a CAM Entry
designated by the HHA Register. S field
specifies the number of both CMP Register and
Segment. Refer to the data sheet for E, S and
STR_HEA
(EE00_1010_SS0U_UUUU)
1 or 2
*1
Store
Store data of the CMP Register to a CAM Entry
designated by the HEA Register. S field
specifies the number of both CMP Register and
Segment. Refer to the data sheet for E, S and
STR_AUT
(EE00_1011_SS0U_UUUU)
1 or 2
*1
Store
When the last search result is hit, do the
STR_HHA operation. When miss, do the
STR_HEA operation with no mask. S field
specifies the number of both CMP Register and
Segment. Refer to the data sheet for E, S and
Other
NOP
(0000_1111_0000_0000)
1
No
operation
Execute no operation.
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9M Classification CAM PRELIMINARY
Version 1.2.0 15 Confidential
6. Register
The followings show the registers.
CNTL Register, LOGICAL BANK CNTL Register
DEVID Register, STAT Register
MASK 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15, 16, 17 Register
CMP 0~7 Register, CMPLM 0~7 Register
AR Register, MEMAR Register, MEMARIN Register
SEG/SEG1 Register,
HHA Register, MEMHHA Register, MEMHHA_SI Register
HEA Register, MEMHEA Register, MEMHEA_SI Register
7. Product Information
7.1. Ordering Information
T.B.D.
7.2. Package Outline
0.15 S
24.13 0.20
0.60 0.10
2.36 0.20
0.750 0.15
INDEX
UNIT: mm
27.00 0.20
24.00 0.10
2019181716151413121110
987654321
Y W V U T R P N M L K J H G F E D C B A
1.27 0.2
View from bottom
View from top
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Kawasaki LSI
9M Classification CAM PRELIMINARY
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8. Electrical Characteristics
8.1. Absolute Maximum Rating
*1: I/O pins are 3.3V tolerant I/O pins. (T.B.D.)
8.2. Operating Range
*1: I/O voltage is selectable from 2.5V or 1.8V. (T.B.D.)
8.3. DC Characteristics
ITEM
SYMBOL
STANDARD CONDITION
UNIT
NOTE
Supply Voltage (I/O)
V
DDQ
T.B.D.
V
Supply Voltage (core)
VDDT.B.D.
V
Input Voltage
VI
-0.3 ~ V
DDQ
+ 0.3
V*1Output Voltage
VO
-0.3 ~ V
DDQ
+ 0.3
V*1I/O Voltage
VIO
-0.3 ~ V
DDQ
+ 0.3
V
*1
Storage Temperature
TSTG
-55 ~ +125
ºC
ITEM
SYMBOL
MIN.
TYP.
MAX.
UNIT
NOTE
Supply Voltage (2.5V I/O) T.B.D.
V
DDQ
2.375
2.5
2.625
V*1Supply Voltage (1.8V I/O) T.B.D.
V
DDQ
1.71
1.8
1.89V*1
Supply Voltage (core)
VDD1.1
1.2
1.3
V
Ambient Operation Temperature
TA0+25
+70
ºC
ITEM
SYMBOL
MIN.
TYP.
MAX.
UNIT
CONDITION
Input Low Voltage
VIL
-0.3
0.35V
DDQ
V
Input High Voltage
VIH
0.65V
DDQ
V
DDQ
+0.3VOutput Low Voltage
VOL
+0.45
V
Output High Voltage
VOH
V
DDQ
-0.45
V
Input Leakage Current
IIL
-10µAVIN=GND
IIH
+10µAVIN=V
DD
Output Leakage Current
IOZ
-10
+10µAOutput is high impedance
Standby Current
IDDS
T.B.D.
µA
Dynamic Operation Current
IDDOP
T.B.D.
mA
Page 19
Kawasaki LSI
9M Classification CAM PRELIMINARY
Version 1.2.0 Confidential
Kawasaki LSI U.S.A., Inc.
Silicon Valley Office Eastern Area Office
2570 North First Street, Suite 301 201 Edgewater Drive, Suite 251
San Jose, CA 95131 Wakefield, MA 01880
Tel: (408)570-0555 Tel: (781)224-4201
Fax: (408)570-0567 Fax: (781)224-2503
URL: www.klsi.com
Kawasaki LSI U.S.A., Inc. (herein after KLSI) reserves the right to make changes
herein at any time without notice. KLSI does not assume any responsibility or liability
arising out o
f application or use of any product described herein, neither does it convey
any license under its patent rights nor the rights of others.
KLSI products are not designed, intended, or authorized for use as components in
systems intended for surgical implan
t into the body, or other applications intended to
support or sustain life, or for any other applications in which the failure of the KLSI
product could create a situation where personal injury or death may occur.
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