Page 1
Final version ( 99.4.30 )
1.1GHZ DUAL PLL KB8825
INTRODUCTION
16−TSSOP−0044
The KB8825 is a high performance dual frequency synthesizer with
two integrated high frequency pre-scalers for RF operation up to 1.1
GHz.
The KB8825 is composed of modulus pre-scalers providing 64 and
66, no dead-zone PFD, selectable charge pump current, selectable
power down mode circuits, lock detector output, and loop filter’s time
constant switch.
It is fabricated using the ASP5HB Bi-CMOS process and is available
16-TSSOP with surface mount plastic packaging. Serial data is transferred into the KB8825 via three-wire interface (CK, DATA, EN).
FEATURES
• Two systems for receiver and transmitter
• Very low operating current consumption: Icc = Typ. 5.5mA @ 3.0V
• Low operating power supply voltage : 2.2 ~ 5.5V ( 200MHz ~ 550MHz Operating )
2.7 ~ 3.6V ( 550MHz ~ 1.1GHz Operating )
• Modulus pre-scaler: 64 / 66
• No dead-zone PFD
• Colpitt type local oscillation
• Selectable charge pump current
• Selectable power down mode
• TSSOP 16-pin package (0.65 mm pitch)
ORDERING INFORMATION
Device Package Operating Temperature
+KB8825 16−TSSOP−0044 −30 °C to + 85 °C
+: New product
APPLICATIONS
• Cordless telephone systems
• Portable wireless communications (PCS)
• Wireless Local Area Networks (WLANs)
• Other wireless communication systems
1
Page 2
Final version ( 99.4.30 )
KB8825 1.1GHZ DUAL PLL
BLOCK DIAGRAM
1
Fin1
2
V
CC
CP1
3
4
GND
5
LD
6
CK
7
DATA
8
EN
PIN CONFIGURATION
Pre_Amp 1/2
Charge
Pump
Phase
Detector
Lock
Detector
Control
Circuit
2
6
Prescaler
1
32, 33
Buffer
Channel 1
Program-
able
Divider
17 12
Prescaler
1
32, 33
Buffer
Channel 2
Program-
able
Divider
Reference
Divider
1/2 Pre_Amp 1615Fin2
V
CC
2
Charge
Pump
Phase
Detector
Switch
Local
OSC
1/2
Buffer
14
CP2
13
12
11
10
9
GND
SW
OSCI
OSCO
BO
Fin1
V
CC
CP1
GND
LD
CK
DATA
EN
1
2
3
4
KB8825
5
6
7
8
16TSSOP
16
15
14
13
12
11
10
Fin2
V
CC
CP2
GND
SW
OSCI
OSCO
9
BO
2
Page 3
Final version ( 99.4.30 )
1.1GHZ DUAL PLL KB8825
PIN DESCRIPTION
Pin No. Symbol I/O Description
1 Fin1 I Input terminal of channel 1 RF signal.
2, 15 Vcc − Power supply voltage input. PIN2 and PIN15 are connected together.
3 CP1 O Output terminal of channel 1 charge pump. Charge pump is constant current output
circuit, and output current is selected by input serial data.
4, 13 GND − Terminal of GND. PIN4 and PIN13 are connected in common.
5 LD O Output terminal of lock detection. It is the open drain output.
6 CK I Input terminal of clock.
7 DATA I Input terminal of data.
8 EN I Input terminal of enable signal.
9 BO O Output terminal of buffer amplifier. The signal of local oscillation is output through the
buffer amplifier.
10 OSCO O Output terminal of local oscillation signal.
11 OSCI I Input terminal of local oscillation signal. In case of external input, connecting it to this
terminal.
12 SW O Switchover terminal for the time constant of loop filter. It is an open drain output. If
you don’t switch the time constant of loop filter, general output is available.
14 CP2 0 Output terminal of channel 2 charge pump. Charge pump is a constant current output
circuit, and the output current is selected by input serial data.
16 Fin2 I Input terminal of channel 2 RF signal.
ABSOLUTE MAXIMUM RATINGS
Characteristic Symbol Value Unit
Power Supply Voltage Vcc 6 V
Power Dissipation P
Operating temperature T
Storage temperature T
Take care ! ESD sensitive device
D
OPR
STG
600 mW
−30 ~ + 85 °C
−55~ +150 °C
3
Page 4
Final version ( 99.4.30 )
KB8825 1.1GHZ DUAL PLL
ELECTRICAL CHARACTERISTICS
(Ta = 25°C, VCC = 3V, unless otherwise specified)
Characteristic Symbol Test Conditions Min. Typ. Max. Unit
Operating Power supply
voltage
Operating current
consumption
Standby current I
V
I
Fin1=Fin2= 200MHz ~ 550MHz 2.2 3.0 5.5 V
CC
Fin1=Fin2= 550MHz ~ 1.1GHz 2.7 3.0 3.6 V
Fin1=Fin2=1.1GHz/ -5dBm input 3.5 5.5 7.5 mA
CC
Standby mode − 0 10 µA
SB
Fin operating frequency Fin Fin1 = Fin2 = − 5dBm 200 − 1100 MHz
Vcc=2.2V − 15 − 0
Fin1 = Fin2
= 200MHz
Vcc=3.0V − 15 − 0
Vcc=5.5V − 10 − 0
Vcc=2.2V −15 − 0
Fin input sensitivity Fin
Fin1 = Fin2
= 550MHz
Vcc=3.0V −15 − 0
dBm
Vcc=5.5V − 10 − 0
Vcc=2.7V − 10 − 0
Fin1 = Fin2
= 1.1GHz
Vcc=3.0V − 10 − 0
Vcc=3.6V − 10 − 0
OSCI operating frequency F
osc
V
= 0dBm, sinewave
Fin
5 - 25 MHz
Vcc=2.2V − 10 0 5
OSCI input voltage
Serial data input high
voltage (CK, DATA, EN)
Serial data input low voltage
(CK, DATA, EN)
Charge pump output
current
Charge pump leakage I
V
V
V
I
CP1
I
CP2
I
CP3
I
CP4
CPL
f
= 10MHz
osc
Vcc=3.0V − 10 0 5
Vcc=5.5V 0 - 5
osc
f
osc
= 20MHz
Vcc=2.2V − 10 0 5
Vcc=3.0V − 10 0 5
Vcc=5.5V − 5 0 5
V
−
V
IH
IL
= 2.2 to 5.5V
CC
V
= 2.2 to 5.5V
CC
CC
0.4
− − V
− − 0.4 V
CP1 = 0, CP2 = 0 VCP = 1.5 V – ± 100 − µA
CP1 = 0, CP2 = 1 VCP = 1.5V – ± 200 − µA
CP1 = 1, CP2 = 0 VCP = 1.5V − ± 400 − µA
CP1 = 1, CP2 = 1 VCP = 1.5V − ± 800 − µA
Standby mode, Vcp = 1.5V −1 − +1 µA
dBm
4
Page 5
Final version ( 99.4.30 )
1.1GHZ DUAL PLL KB8825
FUNCTIONAL DESCRIPTIONS
SERIAL DATA INPUT AND TIMING
CK (Pin6), DATA (Pin7), EN (Pin8) terminals in KB8825 are used for MICOM (MPU) serial data interface (MSB: 1st
input data; LSB: Last input data). Serial data controls the programmable reference divider, programmable divider
(CH1), programmable divider (CH2), and control latch separately by means of group code. Binary serial data is
entered via the DATA pin.
One bit of data is shifted into the internal shift register on the rising edge of the clock. When EN pin is high, stored
data is latched. The three terminals, CK, DATA, and EN, contain Schmitt trigger circuits to keep the data from
errors caused by noise, etc.
< Notice >
1. When power supply of KB8825 is disconnected, CLK, DATA, EN port from MCU should be pulled low.
2. When power goes up first, R counter data should be entered earlier than N1 and N2 counter data.
3. When power goes up first, control data should be entered earlier than N1 and N2 counter data.
≥
≥
≥
0.2us
≥
≥
0.1us
≥
0.2us
LSB MSB
≥ ≥
≥ ≥
0.1us 0.2us
≥
0.2us
≥
DATA
EN
CK
≥
1us 0.2us
MSB
N1 (R1) N2 (R2) N3 (R3) N16 (R11) N17 (R12) GC2 GC1
Figure 1.
NOTE: Start data input with MSB first
SERIAL DATA GROUP AND GROUP CODE
The IC can be controlled through 4 kinds of group selection. Each group is identified by selective a 2-bit group code
given below.
Serial Bits Group Location
GC1 (LSB) GC2 (LSB-1)
0 0 Control Latch
0 1 Ch 1 N Latch
1 0 Ch 2 N Latch
1 1 OSC R Latch
5
Page 6
Final version ( 99.4.30 )
KB8825 1.1GHZ DUAL PLL
CONTROL LATCH
The control register executes the following functions:
• Mode selection (H: test mode, L: normal mode)
• Charge pump’s polarity and output current selection for each channel.
• Output state selection for Lock Detector.
• Standby control of each channel and reference divider.
• ON / OFF control in filter switch.
CH1 CH2MSB
T CP CP1 CP2 CP1SB1 SB2CP2 SBR LD1 LD2 SW
LSB
GC2
"0"
Group Code
GC1
"0"
Figure 2.
Bit Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
Name T CP CP1 CP2 SB1 CP1 CP2
Description test mode charge
pump out
polarity
channel 1
charge
pump
output
current
channel 1
charge
pump
output
current
channel 1
standby
channel 2
charge
pump
output
current
channel 2
charge
pump
output
current
Bit Bit 8 Bit 9 Bit 10 Bit 11 Bit 12 Bit 13 Bit 14
Name SB2 SBR LD1 LD2 SW GC2 GC1
Description channel 2
standby
reference
divider
standby
lock
detector
control 1
lock
detector
control 2
filter switch group code
“0”
group code
“0”
6
Page 7
Final version ( 99.4.30 )
1.1GHZ DUAL PLL KB8825
CHARGE PUMP OUTPUT POLARITY (CP)
In normal operation, the CP should be “0”. In reverse operation, the CP should be
“1”.
Depending upon VCO characteristics, CP should be set accordingly;
When VCO characteristics are like (1), CP should be set low
When VCO characteristics are like (2), CP should be set high.
CHARGE PUMP OUTPUT CURRENT (CP1, CP2)
The KB8825 includes a constant current output type charge pump circuit.
Output current is varied according to control bit “CP1” and “CP2”.
In order to get high speed lock-up, select the best charge pump output current.
Control Bit Charge Pump
CP1 CP2
Output Current
0 0 ±100 µA
0 1 ±200 µA
1 0 ±400 µA
1 1 ±800 µA
VCO
Output
Frequency
VCO Characteristics
(1)
(2)
VCO Input Voltage
7
Page 8
Final version ( 99.4.30 )
KB8825 1.1GHZ DUAL PLL
TEST MODE AND LOCK DETECTOR OUTPUT (T, LD1, LD2)
When T is normal “0”, LD (Pin5)state is varied by controlling “SB1”, “SB2”, “ LD1 ” and “LD2”.
When T is high “1”, LD (Pin5) state is changed to be useful for test
T SB1 SB2 LD1 LD2 LD Output State
0 0 low
0
0 1 channel2
1 0 channel1
1 1 channel1. AND. channel2
0
0 0 low
0 1 high
1
1 0 channel1
1 1 channel1
0
0 0 low
0 1 channel2
0
1 0 high
1 1 channel2
1
0 0 low
0 1 high
1
1 0 high
1 1 high
0 0 low
0 1 pres2
1 0
1 0 fpll2
1 1 fref
0 0 div4
1
0 1 pres1
0 1
1 0 fpll1
1 1 fosc/2
1 1 × × low
0 0 × × low
8
Page 9
Final version ( 99.4.30 )
1.1GHZ DUAL PLL KB8825
LOCK DETECTOR OUTPUT
When the phase comparator detects a phase difference, LD (Pin5) outputs “L”.
When the phase comparator locks, LD outputs “H”. On standby, it outputs “H”.
When T is less than 2/fosc (T<2 /fosc ) for more than three cycles of reference divider output as in the figure below,
the lock detector outputs “H”.
BA
Reference
Divider output
Channel
Divider output
T
Charge pump
output
Lock detector
output
T<2/fosc
Figure 3. Lock Detector Output
fosc: OSCI operating frequency (LOCAL OSC).
T: time difference of the pulse between reference divider output and channel divider output.
A =
B =
Number of divisions by reference divider
fosc
2
(s)
fosc
(s)
PROGRAMMABLE STANDBY MODE (SB1, SB2, SBR)
Standby mode can be controlled by 3-control bits such as SB1, SB2 and SBR. SB1 and SB2 can control standby
mode of channel 1 and channel2. The “SBR” bit can do ON / OFF control of reference divider.
Control Bit Standby Mode State
SB1 SB2 SBR CH1 CH2 REF Mode Status
0 0 × ON ON ON Inter locking Mode
0 1 × ON OFF ON CH1 Locking Mode
1 0 × OFF ON ON CH2 Locking Mode
1 1 0 OFF OFF ON REF On Mode
1 1 1 OFF OFF OFF Standby Mode
9
Page 10
Final version ( 99.4.30 )
KB8825 1.1GHZ DUAL PLL
FILTER SWITCH CONTROL (SW)
The operation mode of the SW terminal is set by bit “SW”.
SW control is useful for switching the time canstant of the loop filter.
Output type of this terminal is an open drain output. High lock mode or normal lock mode can be used, taking
advantage of filter switch control (SW) with the charge pump output current.
When fast lock function can’t be used, normal lock mode is available.
Control Bits Operation Mode (SW and LPF example) The third order LPF
SW CP1 CP2
0 0 0
0 0 1
Normal Lock Mode
0 1 0
0 1 1
1 0 0
CP1
SW
R
R
R
1 0 1
High Lock Mode
1 1 0
GND
1 1 1
CRYSTAL OSCILLATOR CIRCUIT (OSCI, OSCO) AND BUFFER OUT (BO)
External capacitors C1, C2, C3, and C4 are required to set the proper crystal’s load capacitance and oscillation
frequency as shown in figure 4. The value of the capacitors is dependent on the crystal chosen.
The BO (Pin9) outputs local oscillation signal with buffer amplifier.
This terminal (Pin9) can be applied to the 2nd mixer input
C4
1000pF
OSCI
OSCO
C1
C2
C3
C2
OSCI
OSCO
Reference Oscillator
10
BO
1000pF
2'nd MIX
or OPEN
BO
Figure 4.
1000pF
2'nd MIX
or OPEN
Page 11
Final version ( 99.4.30 )
1.1GHZ DUAL PLL KB8825
PROGRAMMABLE REFERENCE COUNTER
This block generates the reference frequency for the PLL.
The reference divider is composed of 12-bit reference divider and a half fixed divider
Sending certain data to the reference divider allows the setting of any of 6 to 8190 divisions (multiple of two).
MSB LSB
R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12
R = R1 × 20 + R2 × 21 + … + R12 × 2
GC2
11
"1"
Group CodeDivision Ratio of the R counter, R
GC1
"1"
Division ratio: 2 × R = 2 × (3~4095) = 6 ~ 8190
Data is shifted in MSB first.
Division
R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1
Ratio
3 0 0 0 0 0 0 0 0 0 0 1 1
4 0 0 0 0 0 0 0 0 0 1 0 0
• • • • • • • • • • • • •
4095 1 1 1 1 1 1 1 1 1 1 1 1
Example) A 21.25MHz X-tal oscillator is connected, and divided into 25kHz steps.
(Reference frequency is 12.5kHz)
21.25 MHz ÷ 12.5 kHz = 1700
1700 = 2 × R
R = (850)
= (1101010010)
10
2
0 1 0 0 1 0 1 0 1 1 0 0 1 1
LSBMSB
11
Page 12
Final version ( 99.4.30 )
KB8825 1.1GHZ DUAL PLL
CHANNEL 1, CHANNEL 2 PROGRAMMABLE N COUNTER
These programmable dividers are composed of a 5-bit swallow counter (5-bit programmable divider),
12-bit programmable main counter, and two-modulus prescalers providing 64 and 66 divisions.
Sending certain data to the swallow counter and the 12-bit programmable main counter allows the setting of any of
2048 to 262142 divisions (multiple of two).
The 12-bit programmable divider and swallow counter are set by each channel;
each channel is identified by a group code.
MSB
Swallow counter
N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 N18 N19
Division Ratio of the N Counter, N
main counter
Figure 5.
5-BIT SWALLOW COUNTER DIVISION RATIO (A COUNTER)
A = N1 × 20 + N2 × 21 … N5 × 2
Division ratio: 0 to 31, B ≥ A
4
Division Ratio
(A)
0 0 0 0 0 0
1 0 0 0 0 1
• • • • • •
31 1 1 1 1 1
LSB
Group Code
CH1 = "10"
CH2 = "01"
N5 N4 N3 N2 N1
12-BIT MAIN COUNTER DIVISION RATIO (B COUNTER)
B = N6 × 20 + N7 × 21 + N7 × 22 … N17× 2
11
Division ratio: 3 to 4095
Data is shifted in MSB first
Division
Ratio (B)
N17 N16 N15 N14 N13 N12 N11 N10 N9 N8 N7 N6
3 0 0 0 0 0 0 0 0 0 0 1 1
4 0 0 0 0 0 0 0 0 0 0 0 0
• • • • • • • • • • • • •
4095 1 1 1 1 1 1 1 1 1 1 1 1
12
Page 13
Final version ( 99.4.30 )
1.1GHZ DUAL PLL KB8825
Channel1 and 2 Programmable Counter Division Ratio, N
N = 2 × (32 × B + A), B ≥ A
Division ratio: 192 ~ 262142
Example) A Signal of 453 MHz is entered into Fin1, and divided into 25 kHz steps.
(Reference frequency is 12.5 kHz)
453 MHz ÷ 12.5 kHz = 36240
36240 = 2 × (32 × B + A)
∴ B = (1132)
= (10001101100)2, A = (16)
10
= (10000)
10
2
MSB
0
0 0 0 1 0 0 1 1 0 1 1 0 0 0 1 0 1 0
Example) A Signal of 462.9 MHz is entered into Fin2, and divided into 25 kHz step.
(Reference frequency is 12.5 kHz)
462.9 MHz ÷ 12.5 kHz = 37032
37032 = 2 × (32 × B + A)
∴ B = (1157)
= (10010000101)2, A = (8)
10
MSB
0
0 0 1 0 1 0 1 0 0 0 0 1 0 0 1 0 0 1
= (01000)
10
2
PHASE DETECTOR AND CHARGE PUMP CHARACTERISTICS
Phase difference detection Range: -2 π ~ +2 π
When SW = Low
LSB
LSB
CP
LD
f
r
f
p
O
fr > f
fr = f
p
fr < f
p
fr < f
p
fr < f
p
p
Figure 6.
13
Page 14
Final version ( 99.4.30 )
RX_VCC
RX_VCC
TX_VCC
RX_VCC
RX_VCC
RX_VCC
TX_VCC
RX_VCC
TX_VCC
RX_VCO
AF_OUT
AF_OUT
RX_VCO
GND
GND9GND10AF_OUT
SGM2016M
KB8825 1.1GHZ DUAL PLL
APPLICATION CIRCUIT ( HANDSET )
C22
C76
5p
C20
C19
C21
220p
100p
1.2N
TP2
1
1
3
2
Q4
KSC2223Y
1
TP5
CP1
1
1
R21
1 2
C38
8.2N
12
C61
12
1p
L9
0.5X1.0X1.5t
1.5N
12
IF
C18
12
10N
U1
C30
4.7N
12
2.2K
C37
8.2N
12
12
12
TX VCO
C58
3p
1 2
C59
2p
12
C60
2p
12
1 2
R8
C17
330
10N
12
1 2
R5
1 2
R3
C2
220
220N
12
C3
1 2
1 2
10N
1 2
L2
R2
1 2L31 2
4.7K
R1
4.7K
3
2
Q1
1 2
C4228
1
C1
6p
12
1 2
ANT1
1
L1
902~905MHz
L14
L15
3.9nH
8.2nH
12
12
F2
6
C75
12
1 2
4p
1
2 5
3
4
1 2
SF X033H
L13
925~927MHz
1 2
C74
1N
1 2
C73
N.A
C6
220
220N
12
C8
1 2
1 2
1 2
10N
L4
R4
C9
47K
1 2
C4
5p
3
6p
2
Q2
1 2
1 2
C5
6p
TP4
C10
C4228
6p
1
12
C7
2p
1 2
R28
C50
680
7p
12
C49
1
1 2
1
6p
1 2
C51
C48
15p
3p
1 2
C71
R45
220N
220
12
TX_VCO1
1 2
1 2
C72
L12
100N
Q11
C4228
R44
5.6K
12
3
2
1
1 2
C13
L5
C11
3.3uH
4
12
R27
1 2
220
C47
100N
R26
18K
12
C68
100p
12
1 2
C45
2p
C66
100N
R7
560
12
Q7
C4228
12
1 2
1 2
C67
3p
150p
12
C14
F1
1N
1 2
1 2
C15
10.7MHz
N.A
12
C46
220N
1 2
R24
L7
5.6K
12
3
C42
2
12
1 2
2p
1
1 2
R25
220
1 2
C43
3p
C44
1p
12
1 2
L11
12
3
2
Q10
1
C4228
1 2
R42
220
R43
18K
R23
10K
L6
0.5X1.0X1.5t
12
1 2
C64
220N
Q9
C4228
C65
12
2p
C40
2p
12
C41
2p
12
1 2
L10
3
1
R41
220
12
220N
12
Q3
123
1 2
R6
C12
10K
10N
12
1 2
L8
3
2
Q8
1 2
C4228
1
1
1
C70
12
47p
C16
10N
1 2
RX VCO
C39
R22
12
1 2
10K
3p
D1
1SV239
12
C69
12
15p
R40
5.6K
12
2
1 2
C62
3p
1 2
C63
1p
12
1 2
R9
22K
R39
10K
12
R17
10K
16
AFLT1
DEMO
1
12
R20
51K
C36
220N
12
TP1
1
R10
6.8K
15
TMC
2
12
1 2
12
12
12
12
1
1 2
KA8532
GND
OSC
VCC
3
4
5
C28
12
15N
1 2
C29
100N
R16
470
R19
100
12
R33
51
R36
12
10K
D2
1SV239
1 2
R38
C57
15K
1N
DECPL
TP6
CP2
1
1
1 2
6
12
R37
560
C23
6.8N
C27
100N
12
C56
10N
R35
7.5K
12
12
RSSI9IIFLT210IFLT111RFIN+12RFIN-13AFO14AFLT2
IFLT47IFLT3
8
12
C26
1.5N
16
FIN11VCC
2
1 2
R32
100
C53
220N
12
12
12
1 3
2
R11
100K
C24
100N
C25
560p
1 2
C33
2~6p
12
OSCI11S/W12GND13CP214VCC15FIN2
KB8825
GND
CP1
CLK
3
4LD5
6
1 2
1 2
R34
C54
30K
10N
12
1 2
C55
220N
KSC1623Y
1 2
Y1
10.63MHz
C35
1 2
47p
10
DATA
7EN8
1 2
R31
R30
1K
1 2
R12
2.7K
3
2
Q5
1
C32
C31
1 2
39p
100p
BO9OSCO
1 2
1 2
R29
1K
1K
1 2
R18
1K
C34
1N
C52
100p
12
R13
6.8K
KSC1623Y
1 2
R15
100
12
11
2
Q6
CNT1
RSSI7LDT
TX VCC5CLK
3
AF IN
1
1 2
R14
2.2K
3
1
RX VCC
DATA
RSSI
EN
TP3
1
1
RSSI
12
8
6
4
2
14
Page 15
Final version ( 99.4.30 )
RX_VCC
RX_VCC
TX_VCC
RX_VCC
RX_VCC
RX_VCC
TX_VCC
TX_VCC
RX_VCC
RX_VCO
AF_OUT
AF_OUT
RX_VCO
GND
GND9GND10AF_OUT
SGM2016M
1.1GHZ DUAL PLL KB8825
APPLICATION CIRCUIT ( BASESET )
C22
C20
C21
C76
5p
C19
TP2
1
IF
1
3
2
Q4
KSC2223Y
1
TP5
CP1
1
1
R21
1 2
2.2K
C38
8.2N
12
C61
12
1p
L16
0.5X1.0X1.5t
1.5N
12
12
C18
12
10N
U1
C30
R17
4.7N
10K
12
C37
R20
8.2N
51K
12
12
220N
12
TX VCO
C58
3.5p
1 2
C59
2p
12
C60
2p
12
C36
12
1 2
R8
C17
330
10N
12
1 2
R5
1 2
R3
C2
220
220N
ANT1
1
R1
4.7K
12
R2
4.7K
1 2
C3
1 2
1 2
10N
1 2
L3
C4
1 2L41 2
3
5p
2
Q1
C4228
1
C1
6p
12
1 2
L6
902~905MHz
L7
L8
3.9nH
8.2nH
12
12
12
1 2
C75
4p
F2
6
SF X034B
1
2 5
4
3
1 2
L11
925~927MHz
1 2
C74
1N
1 2
C73
N.A
C6
220
220N
12
C8
1 2
1 2
1 2
10N
L2
R4
C9
47K
1 2
3
6p
2
Q2
1 2
1 2
C5
6p
1 2
C72
220N
C4228
TP4
Q11
C10
C4228
6p
12
1
C7
2p
1 2
R28
C50
680
7p
12
C49
1
1 2
1
6p
1 2
C51
C48
15p
3p
1 2
C71
R45
220N
220
12
1 2
L13
R44
5.6K
12
3
2
1
123
1 2
R6
10K
Q8
1 2
C4228
TX_VCO1
1
C70
12
47p
1 2
C13
L1
C11
3.3uH
4
12
R27
1 2
220
C47
100N
R26
18K
12
C68
100p
150p
12
C14
F1
1N
1 2
12
1 2
12
L14
Q10
C4228
R24
5.6K
C43
3p
C44
1p
2
1 2
R42
220
R43
12
12
C42
2p
R23
10K
0.5X1.0X1.5t
12
C64
220N
18K
C65
2p
12
L12
C15
N.A
1 2
12
1 2
C4228
1 2
10.7MHz
12
12
1 2
3
Q9
1
12
C40
C41
L15
R41
220
2p
1p
1 2
R7
560
C46
220N
12
1 2
L10
3
Q7
2
C4228
1
C45
12
1 2
2p
R25
220
1 2
C66
100N
1 2
12
3
1 2
C67
2p
1
220N
12
Q3
C12
10N
12
1 2
L9
3
2
1
1
C16
10N
1 2
RX VCO
C39
R22
12
1 2
10K
3p
D1
1SV239
12
C69
12
15p
R40
5.6K
12
2
1 2
C62
3p
1 2
C63
2p
12
1 2
R9
22K
R39
10K
100p
TP1
1
15
16
AFLT1
DEMO
TMC2GND3VCC
1
12
12
1 2
12
1.2N
12
12
1
1 2
R10
6.8K
RFIN-13AFO14AFLT2
KA8532
4
C28
12
15N
C29
100N
R19
100
12
R33
51
R36
12
10K
D2
1SV239
220p
OSC
R11
100K
C54
10N
OSCI11S/W12GND13CP214VCC15FIN2
CLK
1 2
12
1 2
6
1 2
R31
1K
2
KSC1623Y
C32
1 2
39p
Y1
10.63MHz
C35
47p
10
DATA
7EN8
1 2
R30
1K
1 2
R12
2.7K
R13
12
6.8K
3
KSC1623Y
Q5
1
1 2
R15
100
C31
1 2
1 2
100p
R18
1.8K
C34
12
1N
BO9OSCO
1 2
R29
1K
11
1 2
C52
100p
1 3
12
12
10
RSSI9IIFLT2
IFLT47IFLT3
8
12
C26
1.5N
16
FIN11VCC
2
1 2
R32
100
C53
220N
R35
12
7.5K
2
C24
100N
12
C25
560p
C33
1~10p
KB8825
GND
CP1
3
4LD5
1 2
R34
30K
12
1 2
C55
220N
C23
6.8N
12
IFLT111RFIN+
DECPL
5
6
1 2
R16
470
12
C27
100N
12
TP6
CP2
1
1
1 2
C56
10N
2
Q6
CNT1
RSSI7LDT
TX VCC5CLK
3
AF IN
1
1 2
R14
2.2K
3
1
RX VCC
DATA
EN
RSSI
TP3
1
1
RSSI
12
8
6
4
2
R37
12
560
1 2
R38
C57
15K
1N
12
15
Page 16
Final version ( 99.4.30 )
KB8825 1.1GHZ DUAL PLL
CHARACTERISTIC GRAPH
800§Ë
400§Ë
200§Ë
100§Ë
16
100§Ë
200§Ë
400§Ë
800§Ë
Page 17
Final version ( 99.4.30 )
1.1GHZ DUAL PLL KB8825
100§Ë
200§Ë
400 §Ë
800 §Ë
800 §Ë
400 §Ë
200 §Ë
100§Ë
17
Page 18
Final version ( 99.4.30 )
INPUT SENSITIVITY Vin1 (dBm)
INPUT SENSITIVITY Vin1 (dBm)
1100M_min
KB8825 1.1GHZ DUAL PLL
INPUT SENSITIVITY -INPUT FREQUENCY (Fin1)
30
20
10
0
-10
-20
-30
.
30
20
10
-10
-20
-40
0 100 200 300 400 500 600 700 800 900 1000 1100
INPUT FREQUENCY Fin1 (MHz)
INPUT SENSITIVITY - POWER SUPPLY VOLTAGE (Fin1)
0
500M_min
500M_Max
1100M_Max
-30
-40
2.2 2.5 3 3.5 4 4.5 5 5.5 6
INPUT FREQUENCY Fin1 (MHz)
18
Page 19
Final version ( 99.4.30 )
INPUT SENSITIVITY Vin2 (dBm)
INPUT SENSITIVITY Vin2 (dBm)
1.1GHZ DUAL PLL KB8825
INPUT SENSITIVITY -INPUT FREQUENCY (Fin2)
30
20
10
0
-10
-20
30
20
10
-10
-20
-30
-30
0 100 200 300 400 500 600 700 800 900 1000 1100
INPUT FREQUENCY Fin2 (MHz)
INPUT SENSITIVITY - POWER SUPPLY VOLTAGE (Fin2)
0
500_min
500_Max
1100_min
1100_Max
-40
2.2 2.5 3 3.5 4 4.5 5 5.5 6
INPUT FREQUENCY Fin2 (MHz)
19
Page 20
Final version ( 99.4.30 )
Vxin (dBm)
CURRENT CONSUMPTION Icc (mA)
KB8825 1.1GHZ DUAL PLL
XIN INPUT SENSITIVITY
30
20
10
0
-10
-20
-30
-40
5 10 15 20 25
Fxin (MHz)
CURRENT CONSUMPTION- POWER SUPPLY VOLTAGE
7
6
5
4
3
2
20
1
0
0 1 2 3 4 5 6
POWER SUPPLY VOLTAGE VCC (V)
Page 21
Final version ( 99.4.30 )
1.1GHZ DUAL PLL KB8825
NOTES
21
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