Datasheet KB8823, KB8822, KB8821 Datasheet (Samsung)

PRELIMINARY SPECIFICATION (V1.5)

FREQUENCY SYNTHESIZER

INTRODUCTION

The KB8821/22/23 are high performance dual frequency syn­thesizers with integrated prescalers designed for RF operation
up to 1.2GHz/2.0GHz/2.5GHz and IF operation up to 520MHz.
The KB8821/22/23 contain dual-modulus prescalers. The RF
synthesizer adopts a 64/65 or an 128/129 prescaler(32/33 or
64/65 for the KB8823) and the IF synthesizer adopts an 8/9 or
a 16/17 prescaler.
Using a proprietary digital phase-locked-loop technique, the
KB8821/22/23 have linear phase detector characteristic and
can be used for very stable, low noise local oscillator signal.
Supply voltage can range from 2.7V to 4.0V. The KB8821/22/
23 are now available in a 20-TSSOP/24-QFN package.

FEATURES

• Very low current consumption(8821:3.5mA, 22:4.5mA, 23:5.5mA)

• Operating voltage range : 2.7 ~ 4.0V

• Selectable power saving mode(Icc=1uA typical @3V)

• Dual modulus prescaler :
KB8821/22 (RF) 64/65 or 128/129

KB8823 (RF) 32/33 or 64/65
KB8821/22/23 (IF) 8/9 or 16/17

• Programmability via serial bus interface

• No dead-zone PFD

• Variable charge pump output current

• High speed lock mode

KB8821/22/23

20-TSSOP-225

ORDERING INFORMATION

Device Package Tem. Range

KB8821/22/23 20-TSSOP-225 -40 ~ +85°C
KB8821/22/23 24-QFN* -40 ~ +85°C

* QFN : Quad Flat Non-leaded(see Addendum).

APPLICATIONS

• Cellular telephone systems : KB8821

• Portable wireless communications : KB8822
(PCS/PCN, cordless)

• Wireless Local Area Networks (W-LANs)
: KB8823

• Other wireless communication systems

BLOCK DIAGRAM

finRF

finRF

CLOCK

LE

DATA

OSCin

finIF

finIF

+

-

+

-

RF
Prescaler

Serial Data Control

IF
Prescaler

RF
N Counter

RF
R Counter

IF
R Counter

IF
N Counter

Figure 1. BLOCK DIAGRAM

RF

Phase

Detector

IF

Phase

Detector

Charge

Pump

RF
LD

foLD

Data Out

Multiplexer

IF
LD

IF

Charge

Pump

RF

CPoRF

foLD

CPoIF

199-06-15

PRELIMINARY SPECIFICATION (V1.5)

CLOCK

FREQUENCY SYNTHESIZER

BLOCK DIAGRAM- Continued

KB8821/22/23

VDD1

VP1

CPoRF

GND

finRF

finRF

GND

OSCin

GND

1

2

3

4

5

6

7

8

9

RF

Charge

Pump

+ –

Prescaler

Control

RF
LD

RF

Phase

Detector

RF Prescaler

RF

Programmable

Counter

RF N-Latch

RF R-Latch

RF Reference

Counter

foLD

Data Out

Multiplexer

IF
LD

IF

Phase

Detector

IF Prescaler

IF

Programmable

Counter

IF N-Latch

20-bit Shift Register

IF R-Latch

IF Reference

Counter

Prescaler

Control

IF

Charge

Pump

– +

2-bit

Control

20

19

18

17

16

15

14

13

12

VDD2

VP2

CPoIF

GND

finIF

finIF

GND

LE

DATA

foLD

10

11

Figure 2. Detailed block diagram

299-06-15

PRELIMINARY SPECIFICATION (V1.5)

FREQUENCY SYNTHESIZER

PIN CONFIGURATION

VDD1

1

Vp1

2

20

19

KB8821/22/23

VDD2

Vp2

CPoRF

(Digital)

finRF

finRF

GND

3

4

KB8821

5

KB8822

6

18

17

(Digital)

16

15

KB8823

GND

GND

foLD

7

Top View

8

9

10

20-TSSOP

(Analog)

OSCin

(Digital)

20-Lead(0.173 Wide) Thin Shrink Small
Outline Package(20-TSSOP)

14

(Analog)

13

12

11

CPoIF

GND

finIF

finIF

GND

LE

DATA

CLOCK

1. pin #9 = pin #17(internally connected).

2. Do not tie up Vp and VDD

: Vp is the source of digital noises. The power

for analog part is supplied by VDD. If Vp and
VDD are tied together, noisy Vp corrupts the
power source for the analog part.

399-06-15

PRELIMINARY SPECIFICATION (V1.5)

FREQUENCY SYNTHESIZER

KB8821/22/23

PIN DESCRIPTION

Pin No Symbol I / O Description

1 VDD1 - Power supply voltage input for the RF PLL part. VDD1 must equal VDD2. In

order to reject supply noise, bypass capacitors must be placed as close as

possible to this pin and be connected directly to the ground plane.
2 Vp1 - Power supply voltage input for RF charge pump( ≥ VDD1).
3 CPoRF O Internal RF charge pump output for connection to an external loop filter whose

filtered output drives an external VCO.
4 GND - Ground for RF digital blocks.
5 finRF I RF prescaler input. The signal comes from the external VCO.
6 finRF I The complementary input of the RF prescaler. A bypass capacitor must be

placed as close as possible to this pin and be connected directly to the ground

plane. The bypass capacitor is optional with some loss of sensitivity.
7 GND - Ground for RF analog blocks.
8 OSCin I Reference counter input. TCXO is connected via a coupling capacitor.
9 GND - Ground for IF digital blocks.

10

11 CLOCK I CMOS clock input. Serial data for the various counters is transfered into the

12 DATA I Binary serial data input. The MSB of CMOS input data is entered first. The

13 LE I Load enable CMOS input. When LE becomes high, the data in the shift

14 GND - Ground for IF analog blocks.
15 finIF I The complementary input of the IF prescaler. A bypass capacitor must be

16 finIF I IF prescaler input. The signal comes from the external VCO.
17 GND - Ground for IF digital blocks.
18 CPoIF O Internal IF charge pump output for connection to an external loop filter whose

foLD

O Multiplexed output of the RF/IF programmable counters, the reference

counters, the lock detect signals and the shift registers. The output level is

CMOS level. (see fout Programmable Truth Table)

22-bit shift register on the rising edge of the clock signal.

control bits are on the last two bits. CMOS input.

register is loaded into one of the four latches(by the control bits).

placed as close as possible to this pin and be connected directly to the ground

plane. The bypass capacitor is optional with some loss of sensitivity.

filtered output drives an external VCO.

19 Vp2 - Power supply voltage input for IF charge pump( ≥ VDD2)
20 VDD2 - Power supply voltage input for the IF PLL part. VDD1 must equal VDD2. In

order to reject supply noise, bypass capacitors must be placed as close as

possible to this pin and be connected directly to the ground plane.

499-06-15

PRELIMINARY SPECIFICATION (V1.5)

FREQUENCY SYNTHESIZER

EQUIVALENT CIRCUIT DIAGRAM

♦ CLOCK, DATA, LE ♦ foLD

♦ OSCin ♦ CPoRF, CPoIF

KB8821/22/23

♦ finRF, finRF, finIF, finIF

finRF,
finIF

finRF,
finIF

Vbias

599-06-15

PRELIMINARY SPECIFICATION (V1.5)

FREQUENCY SYNTHESIZER

ABSOLUTE MAXIMUM RATINGS

Characteristic Symbol Value Unit

KB8821/22/23

Power Supply Voltage V

Power Dissipation P

Operating Temperature T

Storage Temperature T

DD

D

a

STG

5.5 V

600 mW

-40°C ~ +85oC

-65°C ~ +150oC

°C
°C

ELECTROSTATIC CHARACTERISTICS

Characteristic Pin No. ESD level Unit

Human Body Model All < ±2000 V

Machine Model All < ±300 V

Charged Device Model All < ±800 V

** These devices are ESD sensitive. These devices must be handled in the ESD protected environment.

699-06-15

PRELIMINARY SPECIFICATION (V1.5)

FREQUENCY SYNTHESIZER

KB8821/22/23

ELECTRICAL CHARACTERISTICS (V

Characteristic Symbol Test Conditions Min. Typ. Max. Unit

V

Power Supply Voltage

KB8823 RF + IF
KB8823 RF Only 4.0

Power Supply
Current

KB8822 RF + IF 4.5
KB8822 RF Only 3.0
KB8821 RF + IF 3.5
KB8821 RF Only 2.0
KB882x IF Only 1.5

Power down Current I

Digital inputs : CLOCK, DATA and LE

High-Level Input Voltage V

DD

V

P

I

DD

PWDN

IH

=3.0V, VP=3.0V, -40οC≤Ta≤85οC Unless otherwise specified)

DD

2.7 3.0 4.0

V

DD

3.0 4.0

5.5

VDD=2.7V to 4.0V

VDD=3.0V 1.0 10 µA

VDD=2.7V to 4.0V 0.7V

DD

V

mA

V
Low-Level Input Voltage V
High-Level Input Current I
Low-Level Input Current I

Reference Divider Input : OSCin

Input Current

Digital Output : foLD

High Level Output Voltage V
Low Level Output Voltage V

I

IHR

I

IH

IL

ILR

OH

OL

VDD=2.7V to 4.0V 0.3V

IL

DD

V

VIH= VDD=4.0V -1.0 +1.0 µA
VIL=0V, VDD=4.0V -1.0 +1.0 µA

VIH= VDD=4.0V +100 µA
VIL=0V, VDD=4.0V -100 µA

Iout = -500µA

VDD-0.4

V

Iout = +500µA 0.4 V

799-06-15

PRELIMINARY SPECIFICATION (V1.5)

FREQUENCY SYNTHESIZER

KB8821/22/23

ELECTRICAL CHARACTERISTICS (V

Characteristic Symbol Test Conditions Min. Typ. Max. Unit

Charge Pump Outputs : CPoRF, CPoIF

I

CP-SRCVCP=VP

I

CP-SINKVCP=VP

Charge Pump Output Current

Charge Pump Leakage Current I

Output Current Sink vs. Source
Mismatch*

Output Current Magnitude Variation
vs. Temperature**

Output Current Magnitude Variation
vs. Voltage***

Programmable Divider

I

CP-SRCVCP=VP

I

CP-SINKVCP=VP

CPL

I

CP-SINK

vs

I

CP-SRC

I

vs T

CP

I

CP

V

CP

=3.0V, VP=3.0V, -40οC≤Ta≤85οC Unless otherwise specified)- Continued

DD

/2, I
/2, I
/2, I
/2, I

=Low -1.125

CPo

=Low +1.125

CPo

=High -4.5

CPo

=High +4.5

CPo

0.5V ≤ VCP ≤ VP-0.5V -2.5 +2.5 nA
VCP=VP/2

Ta=25oC

3 10 %

VCP=VP/2 10 %

vs

0.5V ≤ VCP ≤ VP-0.5V
Ta=25oC

10 15 %

mA

Operating
Frequency

KB8823
KB8822 0.2 2.0

finRF VDD=2.7V to 4.0V

0.5 2.5
GHz

KB8821 0.1 1.2

Operating Frequency finIF VDD=3.0V 45 520 MHz

VDD=3.0V -15 0

RF Input Sensitivity P

IF Input Sensitivity P
Phase Detector Frequency f

RF

fin

fin

PD

VDD=4.0V -10 0

IF VDD=2.7V to 4.0V -10 0 dBm

10 MHz

dBm

Reference Divider

Operating Frequency OSCin 5 40 MHz
Input Sensitivity V

OSCin

0.5 V

PP

899-06-15

PRELIMINARY SPECIFICATION (V1.5)

FREQUENCY SYNTHESIZER

KB8821/22/23

ELECTRICAL CHARACTERISTICS (V

Characteristic Symbol Test Conditions Min. Typ. Max. Unit

Serial Data Control

CLOCK Frequency f
CLOCK Pulse Width High t
CLOCK Pulse Width Low t
DATA Set Up Time to CLOCK

Risng Edge
DATA Hold Time after CLOCK

Rising Edge
LE Pulse Width t

CLOCK Rising Edge to LE Rising
Edge

CLOCK

CWH

CWL

t

DS

t

DH

LEW

t

CLE

=3.0V, VP=3.0V, -40οC≤Ta≤85οC Unless otherwise specified)- Continued

DD

10 MHz
50 ns
50 ns
50 ns

10 ns

50 ns
50 ns

<For Charge Pump items>

Ia=Charge pump sink current at Vcp=Vp-∆V, Ib=Charge pump sink current at Vcp=Vp/2, Ic=Charge pump sink current at Vcp=∆V
Id=Charge pump source current at Vcp=Vp-∆V, Ie=Charge pump source current at Vcp=Vp/2, If=Charge pump source current at Vcp=∆V
∆V=Voltage offset from positive(for sink current) and negative(for source current) points from which the charge pump currents become flat.

* Output Current Sink vs. Source Mismatch = [| Ib|-|Ie|] / [0.5 * {| Ib|+|Ie|}] * 100 (%)
** Output Current Magnitude Variation vs. Temperature =
[| Ib @any temp.| - |Ib @ 25οC|] / | Ib @ 25οC| * 100 (%) and [|Ie @any temp.| - |Ie @ 25οC|] / |Ie @ 25οC| * 100 (%)
*** Output Current Magnitude Variation vs. Voltage =

[0.5 * {|Ia|-|Ic|}] / [0.5 * {|Ia|+|Ic|}] * 100 (%) and [0.5 * {|Id|-|If|}] / [0.5 * {|Id|+|If|}] * 100 (%)

999-06-15

PRELIMINARY SPECIFICATION (V1.5)

FREQUENCY SYNTHESIZER

KB8821/22/23

FUNCTIONAL DESCRIPTION

The Samsung KB882x are dual PLL frequency synthesizer ICs. KB882x combined with external LPFs and exter­nal VCOs form PLL frequency synthesizers. They include serial data control, R counter, N counter, prescaler,
phase detector, charge pump, and etc.(Figure 1).
Serial data is moved into 20-bit shift register on the rising edge of the clock(Figure 2). These data enters MSB
first. When LE becomes HIGH, data in the shift register is moved into one of the 4 latches(by the 2-bit control).
The divide ratios of the prescaler and the counters are determined by the data stored in the latches. The external
VCO output signal is divided by the prescaler and the N counter. External reference signal is divided by the R
counter. These two signals are the two input signals to the phase detector. The phase detector drives the charge
pump by comparing frequencies and phases of the above two signals. The charge pump and the external LPF
make the control voltage for the external VCO and finally the VCO generates the appropriate frequency signal.

Serial Data Input Timing

MSB LSB

DATA

CLOCK

LE

N20(R20) N19(R19) N10(R10) N9(R9) C2 C1

t

DS

t

DH

t

CWL

t

CWH

t

CLE

t

LEW

1099-06-15

PRELIMINARY SPECIFICATION (V1.5)

FREQUENCY SYNTHESIZER

KB8821/22/23

FUNCTIONAL DESCRIPTION- Continued

Control Bits

Control Bits

C1 C2

0 0 IF R Counter
0 1 RF R Counter
1 0 IF N Counter
1 1 RF N Counter

Programmable Reference Counter(IF / RF R Counter)

If the Control Bits are 00(IF) or 01(RF), data is moved from the 20-bit shift register into the R-latch which sets
the reference counter. Serial data format is shown in the table below.

DATA Location

R
3

MSB

R

2

C1 C2

Division Ratio of the R Counter, R Program Modes

♦ 15-Bit Programmable Reference Counter Ratio

Division

Division ratio : 3 to 32767
Data are shifted in MSB first

LSB

R1R2R3R4R5R6R7R8R9R10R11R12R13R14R15R16R17R18R19R

Control Bits

R

Ratio

3 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
4 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0

• • • • • • • • • • • • • • • •

32767 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

15R14R13R12R11R10R9

R

R

R

R

R

8

7

6

5

4

20

R
1

1199-06-15

PRELIMINARY SPECIFICATION (V1.5)

FREQUENCY SYNTHESIZER

KB8821/22/23

FUNCTIONAL DESCRIPTION- Continued

Programmable Counter(N Counter)

If the Control Bits are 10(IF) or 11(RF), data is transferred from the 20-bit shift register into the N-latch. N Counter
consists of 7-bit swallow counter(A counter) and 11-bit main counter(B counter). Serial data format is shown
below.

LSB MSB

C1 C2

♦ 7-Bit Swallow Counter Division Ratio(A Counter)

RF IF

Division

Ratio(A)N7N6N5N4N3N2N1

127 1 1 1 1 1 1 1

Division ratio : 0 to 127 Division ratio : 0 to 15
B ≥ A B ≥ A

N1N2N3N4N5N6N7N8N9N10N11N12N13N14N15N16N17N18N19N

Division Ratio of the N Counter, N

Control Bits

Division

Ratio(A)N7N6N5N4N3N2N1

0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 1

• • • • • • • •

0 X X X 0 0 0 0
1 X X X 0 0 0 1

• • • • • • • •

15 X X X 1 1 1 1

20

Program
Modes

X = DON’T CARE condition
♦ 11-Bit Main Counter Division Ratio(B Counter)

Division

Ratio

3 0 0 0 0 0 0 0 0 0 1 1
4 0 0 0 0 0 0 0 0 1 0 0

• • • • • • • • • • • •

2047 1 1 1 1 1 1 1 1 1 1 1

Division ratio : 3 to 2047

N

18N17N16N15N14N13N12N11N10N9

N

8

1299-06-15

PRELIMINARY SPECIFICATION (V1.5)

FREQUENCY SYNTHESIZER

FUNCTIONAL DESCRIPTION- Continued

Pulse Swallow Function

KB8821/22/23

f
f

=[ ( P X B ) + A ] x f

VCO

: External VCO output frequency

VCO

OSCin

/ R

P : Preset modulus of dual modulus prescaler
(for KB8821/22 RF:P=64 or 128, for KB8823 RF:P=32 or 64, for IF: P=8 or 16)
B : 11-bit main counter division ratio (3 ≤ B ≤ 2047)
A : 7-bit swallow counter division ratio
(for RF: 0 ≤ Α ≤ 127, for IF: 0 ≤ Α ≤ 15, Α ≤ B)
fOSCin : External reference frequency(from external oscillator)
R : 15-bit reference counter division ratio (3 ≤ R ≤ 32767)

Program Mode

C1 C2 R16 R17 R18 R19 R20

0 0 IF Phase

Detector Polarity

0 1 RF Phase

Detector Polarity

IF I

RF I

CPo

CPo

IF CPoIF

High Impedance

RF CPoIF

High Impedance

IF

LD
RF

LD

IF

Fo

RF

Fo

C1 C2 N19 N20

1 0 IF Prescaler Pwdn IF
1 1 RF Prescaler Pwdn RF

♦ Mode Select Truth Table

Phase Detector Polarity CPoIF High Impedance I

CPo

IF Prescaler

0 Negative Normal Operation Low 8/9 64/65

1 Positive High Impedance High 16/17 128/129

* The charge pump output current of I

LOW = 1/4 × I

CPo

CPo

HIGH.

RF Prescaler

KB8821/22

(KB8823)

(32/33)

(64/65)

Pwdn

Pwr Up

Pwr Dn

1399-06-15

PRELIMINARY SPECIFICATION (V1.5)

FREQUENCY SYNTHESIZER

FUNCTIONAL DESCRIPTION- Continued

♦ Phase Detector Polarity
Depending on VCO characteristics, R16 bit should be set

as follows :
VCO characteristics are positive like (1) : R16 HIGH
VCO characteristics are negative like (2) : R16 LOW

KB8821/22/23

VCO Characteristics

(1)

♦ foLD (Pin10) Output Truth Table

RF R19

(RF LD)

0 0 0 0 Disabled (default LOW)
0 1 0 0 IF Lock Detect
1 0 0 0 RF Lock Detect
1 1 0 0 RF and IF Lock Detect
0 0 0 1 IF Reference Divider Output
0 0 1 0 RF Reference Divider Output
0 1 0 1 IF Programmable Divider Output
0 1 1 0 RF Programmable Divider Output
0 0 1 1 High Speed Lock mode

IF R19
(IF LD)

RF R20

(RF fo)

IF R20

(IF fo)

VCO Output Frequency

VCO Input Voltage

foLD Output State

(2)

0 1 1 1 IF Counter Reset
1 0 1 1 RF Counter Reset
1 1 1 1 RF and IF Counter Reset

- When the PLL is locked and a lock detect mode is selected, the foLD output is HIGH, with narrow pulses

LOW.

- Counter Reset mode resets R & N counters.

- The high speed lock mode sets the foLD output pin to be connected to ground with a low impedance
(≤110Ω).

1499-06-15

PRELIMINARY SPECIFICATION (V1.5)

FREQUENCY SYNTHESIZER

KB8821/22/23

FUNCTIONAL DESCRIPTION- Continued

♦ Powerdown mode operation
There are synchronous and asynchronous powerdown modes for KB8821/22/23.
Synchronous powerdown mode occurs if R18 bit is LOW, N20 bit is HIGH and charge pump output is in high
impedance state. In the synchronous power down mode, the powerdown function is activated by the charge
pump to diminish unwanted frequency jumps. Asynchronous powerdown mode occurs if R18 bit is HIGH and
N20 bit is HIGH.
When the PLL goes to either synchronous or asynchronous powerdown mode, preamp becomes debiased, R &
N counters keeps their load conditions and the charge pump becomes high impedance state. The oscillator cir­cuitry function becomes disabled only when both IF and RF powerdown bits are activated, i.e. N20 HIGH.
The PLL returns to an active powerup mode when N20 bit becomes LOW(either in synchronous or asynchronous
modes).

R18 N20 Powerdown mode status

0 0 PLL active
1 0 PLL active, only charge pump high impedance
0 1 Synchronous powerdown
1 1 Asynchronous powerdown

Phase Detector and Charge pump Characteristics

Phase difference detection range : -2π ~ +2π
When R16 = HIGH

fr

fp

LD

CPo

fr>fp fr=fp fr<fp fr<fp fr<fp

1599-06-15

PRELIMINARY SPECIFICATION (V1.5)

FREQUENCY SYNTHESIZER

RF SENSITIVITY MEASUREMENT CIRCUIT

RF

Signal

Generator

Frequency

Counter

50Ω
Microstrip

10dB ATTN

51Ω

12kΩ

39kΩ

100pF

100pF

OSC

foLD

f

in

f

in

in

2.7V ~ 4.0V

V

DD

V

P

100pF

LE
DATA
CLOCK

KB8821/22/23

2.2µF

100pF

PC

Parallel

Port

2.2µF

** N=10,000 R=50 P=64
** Sensitivity limit is determined when the error of the divided RF output( foLD) becomes

≥1 Hz.

1699-06-15

PRELIMINARY SPECIFICATION (V1.5)

FREQUENCY SYNTHESIZER

TYPICAL APPLICATION CIRCUIT

Reference
Input

51Ω

foLD

1000pF

RF out

100pF

100pF

10pF

KB8821/22/23

V

P

VCO

R1

C2

C1

R

in

100pF

18Ω

0.01µF

100pF

V

DD

0.01µF

10 9 8 7 6 5 4 3 2 1

foLD GND OSCin GND finRF finRF GND CPoRF VP1 VDD1

KB882x 20-TSSOP

CLOCK DATA LE GND finIF finIF GND CPoIF VP2 VDD2

11 12 13 14 15 16 17 18 19 20

From
Controller

IF out

** The role of Rin : Rin makes VCO output power go to the load rather than the PLL.
The value of Rin depends on the VCO power level.

10pF

100pF

100pF

R

in

VCO

R2

C3

C4

100pF

Vp

18Ω

100pF

0.01µF

V

DD

0.01µF

0.01µF

0.01µF

1799-06-15

PRELIMINARY SPECIFICATION (V1.5)

FREQUENCY SYNTHESIZER

PACKAGE DIMENSIONS

#20 #11

KB8821/22/23

4.40 ¡¾ 0.20

0.006 x

0.15 x

+0.10

+0.004

-0.05

-0.002

0.173 ¡¾ 0.008

#1 #10

6.90

0.272

6.40 ¡¾ 0.20

0.252 ¡¾ 0.008

0.30

0.012

0.22 ¡¾ 0.10

0.009 ¡¾ 0.004

MAX

6.40 ± 0.30

0.252 ± 0.012

MAX

1.10

0.073

0.059 ± 0.008

MIN

0.002

0.65

0.026

0.90 ± 0.20

0.05

20-Lead TSSOP Package
(Samsung 20-TSSOP-225)

0.020 ¡¾ 0.008

0.10MAX

0.004MAX

0.50 ¡¾ 0.20

5.72

0.225

0 ~ 8

o

1899-06-15

PRELIMINARY SPECIFICATION (V1.5)

FREQUENCY SYNTHESIZER

Addendum(for 24-QFN package)

PIN CONFIGURATION(24-QFN, not to scale)

KB8821/22/23

N/C

Vp1

CPoRF

GND

(Digital)

finRF

finRF

GND

(Analog)

OSCin

N/C

1

2

3

4

5

6

7

8

9

VDD1

24

KB8821
KB8822

KB8823

Top View

10

GND

(Digital)

VDD2

23

11

foLD

Vp2

22

12

CLOCK

N/C

21

20

CPoIF

19

GND

(Digital)

18

finIF

17

finIF

GND

16

(Analog)

LE

15

DATA

14

N/C

13

* N/C pins must be connected
to GND(to Analog GND if
possible).

24-QFN

24 PIN Quad Flat Non-leaded

(24-QFN) Package

1. pin #10 = pin #19(internally connected).

2. Do not tie up Vp and VDD

: Vp is the source of digital noises. The power

for analog part is supplied by VDD. If Vp and
VDD are tied together, noisy Vp corrupts the
power source for the analog part.

19TEL-97-D003

99-06-15

PRELIMINARY SPECIFICATION (V1.5)

FREQUENCY SYNTHESIZER

PIN DESCRIPTION(24-QFN)

KB8821/22/23

Pin No

( 20-

TSSOP)

1 24 VDD1

- 1 - N/C No connection.
2 2 Vp1 - Power supply voltage input for RF charge pump( ≥ VDD1).
3 3 CPoRF O Internal RF charge pump output for connection to an external loop

4 4 GND - Ground for RF digital blocks.
5 5 finRF I RF prescaler input. The signal comes from the external VCO.

6 6 finRF I

7 7 GND - Ground for RF analog blocks.
8 8 OSCin I Reference counter input. TCXO is connected via a coupling

- 9 - N/C No connection.
9 10 GND - Ground for IF digital blocks.

10 11

11 12 CLOCK I CMOS clock input. Serial data for the various counters is transfered

- 13 - N/C No connection.

12 14 DATA I Binary serial data input. The MSB of CMOS input data is entered

13 15 LE I

14 16 GND - Ground for IF analog blocks.

15 17 finIF I

16 18 finIF I IF prescaler input. The signal comes from the external VCO.
17 19 GND - Ground for IF digital blocks.
18 20 CPoIF O Internal IF charge pump output for connection to an external loop

- 21 - N/C No connection.

19 22 Vp2 - Power supply voltage input for IF charge pump( ≥ VDD2)

Pin No

(24QFN)

Symbol I / O Description

- Power supply voltage input for the RF PLL part. VDD1 must equal
VDD2. In order to reject supply noise, bypass capacitors must be
placed as close as possible to this pin and be connected directly to
the ground plane.

filter whose filtered output drives an external VCO.

The complementary input of the RF prescaler. A bypass capacitor
must be placed as close as possible to this pin and be connected
directly to the ground plane. The bypass capacitor is optional with
some loss of sensitivity.

capacitor.

Multiplexed output of the RF/IF programmable counters, the

foLD

O

reference counters, the lock detect signals and the shift registers.
The output level is CMOS level. (see fout Programmable Truth
Table)

into the 22-bit shift register on the rising edge of the clock signal.

first. The control bits are on the last two bits. CMOS input.
Load enable CMOS input. When LE becomes high, the data in the

shift register is loaded into one of the four latches(by the control
bits).

The complementary input of the IF prescaler. A bypass capacitor
must be placed as close as possible to this pin and be connected
directly to the ground plane. The bypass capacitor is optional with
some loss of sensitivity.

filter whose filtered output drives an external VCO.

99-06-15

20TEL-97-D003

PRELIMINARY SPECIFICATION (V1.5)

FREQUENCY SYNTHESIZER

20 23 VDD2 -

KB8821/22/23

Power supply voltage input for the IF PLL part. VDD1 must equal
VDD2. In order to reject supply noise, bypass capacitors must be
placed as close as possible to this pin and be connected directly to
the ground plane.

2199-06-15