Page 1
KB8527B 1 CHIP CLP SUBSYSTEM IC
INTRODUCTION
KB8527B is a monolithic circuit which can be used in high
performance 60MHz MCA type CLP System.
The KB8527B is a subsystem IC for FM / FSK receiving systems and a complete one chip FM / FSK receiver IC for 60MHz
system. It`s feature includes receiving functions for FM / FSK
systems, a compandor to remove external noise, and PLL ( Phase Lock Loop ) of channel selection which blocks surrounding
frequency interference.
The KB8527B can be used with a wide range of FM / FSK VHF
bandwidth systems, including cordless phone, and the narrow
band voice and data sending / receiving systems.
To make applications easily and simply, pheripheral parts are
minimized.
ORDERING INFORMATION
Device Package Operating Temperature
48 -QFP- 1010E
+ : New product
FEATURES
¡Ü Operating voltage range : 2.0V ~ 5.5V
¡Ü Typical supply current : 13.5mA at 3.6V
¡Ü Built - in low battery detection function ( selectable 3.45V, 3.3V, 3.0V, 2.2V, 2.1V )
¡Ü Built - in speaker amplifier
• Built - in splatter filter
• Built - in dual conversion receiver, compandor and universal PLL
¡Ü FM Receiver
- Complete dual coversion circuit
- Excellent input sensitivity (0.7µVrms at 20dB SINAD)
¡Ü Compandor
- Easy gain control to use external component
- Included ALC (Automatic Level Control) circuit
- Included Mute logic
¡Ü Universal PLL
- RX (TX) divided counter range : 1/16 ~ 1/16383
- Reference frequency divided counter range : 1/16 ~ 1/4095
- Lock detector signal output
- Serial interface with MICOM for controlling each block
-20oC ~ + 70oC+ KB8527BQ 48 - QFP - 1010E
Page 2
KB8527B 1 CHIP CLP SUBSYSTEM IC
BLOCK DIAGRAM
2MI
1MO
1LOI
1LOI
VCO
RX
1MI
1MI
GND
(PLL)
PDR
V
REF
(PLL)
V
(PLL)
TIF
LD
(RX)
GND
30
Meter
Driver
Carrier
Detector
Low
Battery
Detector
QCI
RAO
29 28 27
Limiter
Gain Cell
Rectifier
DSCI
FSK
COMP
DSCO
26
Rectifier
Gain Cell
25
SUM
AMP
MDO
Regulator
(1V)
PRI
+
-
SUM
AMP
SPK
AMP
SPK
AMP
+
-
PRI
ALC
VREF
V
REF
24
(COMP)
23
ALC
22
EPI
21
ERC
EO
20
SAI
19
SAO1
18
SAO2
17
VCC
16
(COMP)
GND
15
(COMP)
CPI+
14
13
CPI -
(RX)
VCC
LI
32 31
Limiting
IF AMP
37
2LOI
36
X-tal
OSC
2`nd
MIX
35
2LOI
2MO
34 33
IF AMP
(455KHz)
38
39
40
RX
VCO
Quad
Detector
AMP
41
42
1`st
MIX
IF AMP
(10.7MHz)
Regulator
43
44
( 2.15 V )
Buffer
Programmable Counter
45
46
CC
47
48
( RX )
Programmable Counter
( TX )
Programmable Counter
( REF )
4_25 CNT
RX Phase
Detector
TX Phase
Detector
CO
PDT
SFI
Splatter
Filter
SFO
fMCU
CDO/LDT
CONTROL
6
(PLL)
GND
CLK
DATA
EN
LBD
AGIC
Compandor
mute
121110 9 8 754 3 1 2
CRC
Page 3
KB8527B 1 CHIP CLP SUBSYSTEM IC
PIN CONFIGURATION
VCO
GND
V
REF(PLL)
V
CC(PLL)
2MI
1MO
1LOI
1LOI
RX
1MI
1MI
(PLL)
PDR
37
38
39
40
41
42
43
44
45
46
47
36
2LOI
35
2LOI
34 33
2MO
LD
(RX)
GND
30
(RX)
VCC
LI
32 31
KB8527B
29
QCI
RAO
28
27
DSCI
26
DSCO
MDO
25
24
23
22
21
20
19
18
17
16
15
14
V
REF(COMP)
ALC
EPI
ERC
EO
SAI
SAO1
SAO2
VCC
(COMP)
GND
(COMP)
CPI+
TIF
48
1
PDT
2
CO
3
SFI
4 5 6
SFO
CDO/LDT
(PLL)
GND
7
CLK
8
DATA
9
EN
10 11
LBD
12
AGIC
13
CRC
CPI -
Page 4
KB8527B 1 CHIP CLP SUBSYSTEM IC
PIN DESCRIPTION
Pin No Symbol Description
Phase detector output terminal of the transmitter at PLL.
1
PDT
If fTX > f
If fTX < f
if fTX = f
or fTX is leading the output is negative pulse
REF
or fTX is lagging the output is positive Pulse
REF
and the same phase the output is High Impedance
REF
2
CO
Compressor output terminal of compandor ; connected to the splatter filter amp
input terminal.
3
4
SFI
SFO Output terminal of Splatter filter amp.
Input terminal of Splatter filter amp.
LDT : Output terminal of transmitter lock detector in PLL block. Output is low
if PLL is in lock state and is high if PLL is in unlock state.
5
LDT/
CDO
CDO : As an output terminal of the carrier detector buffer, connected to (RSSI )
terminal of MICOM. This pin outputs the contents of Meter Driver buffer
which is turned on / off, according to the signal level detected by Meter
Driver.
Ground.
6
GND
PLL
Ground of logic section at PLL.
CLK7
8
9
10
DATA
EN
LBD
11 AGIC
These pins are serial interface terminals for programming reference counter,
auxiliary reference counter, TX channel counter, RX channel counter and control
block that controls internal each block with test mode and power saving mode.
Low Battery Detecting output. ( Selectable 3.45V, 3.3V, 3.0V, 2.2V, 2.0V ).
During the normal operation, output level is low, but it is high at low battery
detection. As this pin is an open collector type, it requires a pull - up resister.
This pin bypasses AC elements at the feedback loop which come from the SUM
amp block of COMPRESSOR. A capacitor should be connected between this terminal and GND. ( C = 2.2 uF )
Page 5
KB8527B 1 CHIP CLP SUBSYSTEM IC
Pin No Symbol Description
12 CRC
13
CPI -
14 CPI +
15
16
17
GND
(COMP)
Vcc
(COMP)
SAO 2
Converts waveform from the full wave rectifier to DC element at the rectifier block
of Compressor. ( RC = 33 msec )
Pre - amp inverting input terminal of Compressor.
Adjusts the negative feedback loop gain. ( in application, gain is 5 )
Pre - amp non - inverting input terminal of Compressor.
Used as an input terminal for voice signals.
Ground.
Ground of Compandor.
Supply voltage.
Power supply terminal of Compandor.
Output terminal of speaker amp 2.
This signal is the same as SAO1 output, but phase difference is 180o for SAO1.
DC voltage level is ( Vcc - 0.7V ) / 2.
18 SAO 1
Output terminal of Speaker amp 1.
DC voltage level is ( Vcc - 0.7V ) / 2.
19 SAI
Speaker Amp 1 input terminal.
Between this terminal and Expander output terminal, uses a AC coupled.
20 EO Output terminal of Expander, from which a regenerated voice signals are emitted.
Converts waveform from the full wave rectifier to DC element at the rectifier block
21
22
ERC
EPI -
of Expander. ( RC = 33 msec )
Pre - amp inverting input terminal of Expander.
Adjusts the negative feedback loop gain. ( in application, gain is 5 )
Reference current input terminal of Automatic Level Control ( ALC) ; Adjusts THD
of compressor output voltage to less than 3 % or limites the frequency deviation
23 ALC
of TX if the input is higher than a certain level. The ALC circuit may be turned
off depending on the ALC reference current or the magnitude of output voltage
may be limited if it is higher than a certain level. ( Iref = 8uA, Ralc = 120KΩ )
Page 6
KB8527B 1 CHIP CLP SUBSYSTEM IC
Pin No Symbol Description
24
25
26
27
V
REF(COMP)
MDO
DSCO
DSCI
28 RAO
29 QCI
Reference voltage ( V
= 1V ). Supplies a regulator voltage to the Compressor and
REF
Expander of COMPANDER.
Output terminal of the Meter Driver.
Amplitude of RF input signal for useful frequency is detected by Meter Driver
circuit. The Meter Driver circuit has perfect linear characteristic of 60 dB range
for input signal level. ( 0.1µV / dB )
Output terminal of Data Slicing comparator.
Seperates Frequency Shift Keying ( FSK ) serial data and executes data shapping
and limiting.
Input terminal of Data slicing comparator.
Non - inverting type with the negative input terminal biased to 1/2 Vcc.
Recovered Audio Output terminal. Voice signals detected by the Quadrature
Detector are amplified and then output through this terminal.
Quadrature coil input terminal.
The 455 KHz oscillator circuit is an Lp=680uH, Cp=180pF valued LC tank circuit.
Voice signals are detected by mixture of 455 KHz ( by phase difference ) which
is converted from mixer 2.
30 GND
31
32
LD
LI
RX
Ground .
Ground for Receiver.
Limiter input and decoupling terminal.
Removes amplitude modulation elements caused by fading or FM signal noise.
Limiting IF amplifies and limits the second intermediate frequency, 455 KHz.
The input impedance of the limiting IF amplifier is set to 1.5 KΩ.
While FM waves are transmitted with constant magnitude, their magnitudes are
slightly modulated due to reflection from obstacles, fading phenomenon, noise
wave, and mixing with AM wave elements before entering the receiver`s antenna.
The limiter makes amplitude uniform by removing these AM wave elements.
Page 7
KB8527B 1 CHIP CLP SUBSYSTEM IC
Pin No Symbol Description
33 V
CC(RX)
2MO34
2LOI35
2LOI36
37 2MI
38 1MO
Supply voltage.
Supplies power to the Receiver.
Output terminal of Mixer 2. Second intermediate frequency ( 455 KHz ), generated
by mixing first intermediate frequency ( 10.7 MHz ) and Second Local Oscillator is
output.
Input terminal of second local oscillator. Generates second local oscillator
frequency to convert output from mixer 1 ( 10.7 MHz ) into second intermediate
frequency. It is an oscillator with crystal of 10.24 MHz and 10.245 MHz.
Input terminal of mixer 2. Output from mixer 1 is entered to mixer 2 input terminal
via 10.7 MHz ceramic filter. Second mixer converts frequency to second intermediate frequency ( 455 KHz : AM IF ).
Output terminal of mixer 1.
The signal from mixer 1 and the frequency of the first local oscillator are mixed
to produce the first intermediate frequency, which is the output through this
terminal. The output terminal is an emitter follower with an output impedance of
330Ω to match the 330Ω input / output impedance of the 10.7 MHz ceramic filter.
39
40
41
1LOI
1LOI
VCORX
42 1MI
43 1MI
44
GND
(PLL)
Input terminal of the first local oscillator.
The local oscillator is a voltage controlled oscillator. local oscillation frequency
and received frequency are mixed at mixer 1 and then conerted to the first
intermediate frequency of 10.7 MHz or 10.695 MHz.
The terminal which variable capacitor is included in the chip. Used as an input
terminal where 1`st local oscillation frequency is changed by varying the capacitor
connected between 1`st local oscillator terminals.
The internal variable capacitor has the value of 18.73 ~ 15.86 pF depending on the
applied voltage. ( 1.0 ~ 2.0 V )
Input terminal of Mixer 1. This mixer is made of double balanced multiplier.
The received signal amplied at RF AMP is input to this teminal.
Ground.
Ground for analog at PLL.
Page 8
KB8527B 1 CHIP CLP SUBSYSTEM IC
Pin No Symbol Description
Phase detector output terminal of the receiver at PLL.
45
46
47
48
PDR
V
REF(PLL)
V
CC(PLL)
TIF
If fRX > f
If fRX < f
If fRX = f
or fRX is Leading The output is negative pulse
REF
or fRX is Lagging The output is positive pulse
REF
and the same phase The output is high impedance
REF
PLL voltage reference output pin.
An internal voltage regulator provides a stable power supply voltage for the RX
and TX PLLs.
Power supply terminal of PLL.
Input terminal of TX channel counter.
AC coupling with TX VCO.
Minimum input level is 300 mVp-p ( at 60MHz ).
Page 9
KB8527B 1 CHIP CLP SUBSYSTEM IC
ABSOLUTE MAXIMUM RATINGS
Characteristic Symbol Unit
Maximum Supply Voltage
Power Dissipation
Operating Temperature
Storage Temperature
V
P
T
T
CC
D
OPR
STG
- 55 ~ + 150
CURRENT CONSUMPTION AT EACH MODE ( Vcc = 3.6V )
Modes Min. Max.
Inactive mode
RX mode
Communication mode
( Active mode )
-
-
-
Value
5.5
600
-20 ~ + 70
Typ.
350uA
6.6mA
13.5mA
V
mW
o
C
o
C
600uA
-
-
CURRENT CONSUMPTION IN EACH BLOCK ( Vcc = 3.6V )
Modes Min. Max.
Receiver part
Expander part
Speaker part
compressor part
PLL
RX part
TX part
-
-
-
-
-
-
Typ.
5.0mA
1.4mA
1.7mA
3.0mA
1.6mA
0.8mA
7.5mA
2.1mA
2.5mA
4.5mA
2.4mA
1.2mA
Page 10
KB8527B 1 CHIP CLP SUBSYSTEM IC
ELECTRICAL CHARACTERISTICS
Characteristic Min Typ Max UnitSymbol Test Conditions
Vcc V -
2.0 5.5Operating Voltage
RECEIVER
( VCC = 3.6V, fC = 49.7MHz, f
Characteristic Min Typ Max UnitSymbol Test Conditions
Input for -3dB Sensitivity 0.7 2.0 µVrms
Input for 20dB Sensitivity 0.7 2.0 µVrms
S/N Ratio 48 55 dB
Recovered Audio Output 145 185 225 mVrms
Recovered Audio Output
Voltage Drop
=+ 3KHz, f
DEV
V
LIM
V
I(SEN)
S/N
V
O(RA)
O(RAD)
NO
= 1KHz,Ta = 25oC, unless otherwise specified )
MOD
-3dB Point
Modulation Input
-
-
Modulation Input
No Modulation Input
RFin = 1mVrms
RFin = No Input
Vcc = 5V 2V
RFin = 1mVrms
-
-8
130 205 Noise Output Level V
-3.3 dB
-
mVrms
-V
Detect Output Voltage 1.0 1.5 2.0 VV
Carrier Detector
Threshold
Comparator Threshold
Voltage Difference
Comparator Output
Voltage 1
Comparator Output
Voltage 2
First Mixer Conversion
Voltage Gain
Second Mixer Conversion
Voltage Gain
O(DET)
V
TH(DET)
∆ V
∆ G
∆ G
V
OH
VOL
V(1M)
V(2M)
TH
RFin = 1mVrms
RFin = No Input
V
= 150mVp-p
COMP
RL = 180KΩ
V
= 150mVp-p
COMP
RL = 180KΩ
V
= 150mVp-p
COMP
RL = 180KΩ
V
= 1mVrms
I(43)
R
= 330Ω
L(38)
V
= 1mVrms
I(37)
R
= 1.5KΩ
L(34)
0.49 V
70
2.7 V
0.60 0.73
110 150
3.0
-
mV
0.25 0.5
14 18 22
17 21 25
dB
dB
V-
Page 11
KB8527B 1 CHIP CLP SUBSYSTEM IC
ELECTRICAL CHARACTERISTICS (Continued)
Characteristic Min Typ Max UnitSymbol Test Conditions
Detector Output
Distortion
Detector Output
Resistance
Detector Output DC
Voltage Change Ratio
THD
R
∆ V
DET
O(DET)
O(DET)
Meter Drive Slope MDS
First Mixer Input
Resistance
First Mixer Input
Capacitance
Second Mixer
Input Sensitivity
First Mixer 3rd Order
Sensitivity
R
I(1M)
C
I(1M)
I(LIM)
S
V(2M)
3RD dBm
RFin = 1mVrms
RFin = 1mVrms
fc = 50MHz
fc = 50MHz
fc = 455KHz, 20dB SINAD
fc = 10.7MHz, 20dB SINAD
-
-
-
1.5 2.5 %RFin = 1mVrms
1.2 - KΩ
0.15 0.23 V/KHz
70 100 135 nA/dB
25
-
Ω
µV rms
µV rms
-
500 690
-
-
-
-
7.2 10 pF
100 250Limiter Input Sensitivity V
10
-22
3.45
3.3
3.0
2.2
2.1
0.1
0.075
V Low Battery Detector LBD
AM Rejection Ratio AMRR
LBD0 ~ LBD3 = 0 ( Default )
Only LBD2 = 0
Only LBD1 = 0
Only LBD3 = 0
LBD0 ~ LBD3 = 1
RFin = 1mVrms ~ 10mVrms
-0.15
- 0.1
25 35 - dB
AM MOD = 30%
Compressor
( Vcc = 3.6V, fc = 1KHz, Ta = 25oC, unless otherwise specified )
Characteristic Min Typ Max UnitSymbol Test Conditions
REF
Standard Output Voltage Vo(com) 255 300 345 mVrms
Compressor Gain
Difference
∆ G
∆ G
V1(COM)
V2(COM)
No Signal
Vinc = 13mVrms 0dB
Vinc = -20dB
Vinc = -40dB
0.9 1.0 1.1
-1.0 -0.5 0
-2.0 dB
-1.0
0
VReference Voltage V
dB
Page 12
KB8527B 1 CHIP CLP SUBSYSTEM IC
ELECTRICAL CHARACTERISTICS (Continued)
Characteristic Min Typ Max UnitSymbol Test Conditions
Compressor Output
Distortion
Mute Attenuation Ratio
Compressor Limiting
Voltage
ALC V
THD
ATT
V
LIM(COM)
ALC
COM
MUTE
Vinc = 0dB
Vinc = 0dB
Vinc = Variable
IALC = 8uA ( RALC = 120KΩ )
Splatter filter Vo(SF) VINC = 13mVrms = 0 dB 255 300 345 mVrms
Expander
(Vcc = 3.6V, fc = 1KHz, Ta = 25oC, unless otherwise specified)
Characteristic Min Typ Max UnitSymbol Test Conditions
Standard Output Voltage V
O(EXP)
VinE = 30mVrms 0dB mVrms
-
60 dB
0.5
80
1.0
%
1.41 1.65 1.83 Vp-p
280 330
380 mVrms
104 130 156
∆ G
Expander Gain
Difference
Expander Output
Distortion
∆ G
∆ G
THD
V3(EXP)
Mute Attenuation Ratio ATT
Expander Maximum
Output Voltage
Speaker amp output 1
Speaker amp output 2
V
OEXP(MAX)
Vo( SA1)
Vo( SA1)
V1(EXP)
V2(EXP)
EXP
MUTE
VinE = -10dB
VinE = -20dB
VinE = -30dB
VinE = 0dB 1.00.5 %
0
0
0
-
VinE = 0dB
VinE = Variable
THD = 10%
VINE = 30mVrms = 0 dB
VINE = 30mVrms = 0 dB
500 600
104
104
0.5
1.0
1.5
8060 dB
130
130 156
1.0
2.0
3.0
dB
dB
dB
-
-
mVrms
156 mVrms
mVrms
Page 13
KB8527B 1 CHIP CLP SUBSYSTEM IC
PLL
( Vcc = 3.6V, Ta = 25oC, unless otherwise specified )
Characteristic Min Typ Max UnitSymbol Test Conditions
Operating Current I
Input Current
Input Voltage
Output Current
Output Voltage
CCPLL
I
IH
I
IL
V
IH
V
IL
I
OH
I
OL
V
OH1
V
OL1
V
OH2
Vcc = 3.6V 2.0 3.5 mA
Vin = Vcc
Vin = 0V
Vout = Vcc
Vout = 0V
PDT,PDR : Io = -0.3mA
( Sourcing )
PDT,PDR : Io = 0.3mA
( Sinking )
LD,f
: Io = -0.1mA
MCU
( Sourcing )
-
-
-5
Vcc-
0.3
-
0.3
0.3
Vcc-
0.4
-
Vcc-
0.5
-
-
-
-
-
-
-
-
-
5
-
-
0.3
-
-
-
0.4
-
µA
µA
V
V
mA
mA
V
V
V
PLL regulator voltage
V
OL2
V
PLLREG
LD,f
: Io = 0.1mA
MCU
( Sinking )
- 2.151.95 2.25
- -
0.5
V
V
Page 14
KB8527B 1 CHIP CLP SUBSYSTEM IC
PLL Program summary
• MCU ( MICOM ) Serial Interface ( MSB : 1’st INPUT )
Use CLK (Pin 7 ), DATA (Pin 8 ) , EN (Pin 9 ) terminals for program.
DATA and CLK terminals are used for loading data to internal Shift - Register. When EN terminal is
` Low `, It is possible to program TX-Channel Counter, RX - Channel Counter and various control
functions of PLL. When EN terminal is ` High` , Program 1`st Local Oscillator Capacitor Selection in
receiver for U.S.A - 25 CH function.
- TX - Register, RX-Register, Control Register
MSB LSB
DATA
EN
CLK
- Reference - Register
EN
CLK
- RECEIVER -1`st local oscillator internal capacitor selection register
& low battery detector voltage register [ CLO _ LBD - Register ]
PMC0 PMC1 14 Bit DATA
MSB LSB
PMC0 PMC1 UK_S1 UK_S0 12 Bit DATADATA
DATA
EN
CLK
MSB
PMC LBD3 LBD2 LBD1 LBD0 CLO5 CLO4 CLO3 CLO2 CLO1 CLO0
<1>
LSB
Page 15
KB8527B 1 CHIP CLP SUBSYSTEM IC
• Programmable Counter
- RX - counter : Setting frequency for RX.VCO ( 14 Bits --> 1/16 ~ 1/16383 )
[ Default_CH. = USA_#21 ( REMOTE ) : 36.075MHz ( Div._NO = 7215 )]
< RX. Register (16bits) >
Bit
Name
Default
value
7215
Bit
Name
Default
value
7215
- TX - counter : Setting frequency for TX.VCO ( 14 Bits --> 1/16 ~ 1/16383 )
[ Default_CH. = USA_#21 ( REMOTE ) : 49.830MHz ( Div._NO = 9966 )]
< TX. Register (16 bits) >
Bit
Name
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
PMC0 PMC1 D13 D12 D11 D10 D9 D8
* 0 1 1 1 0 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
D7 D6 D5 D4 D3 D2 D1 D0
1 0 1 1 1 10 0
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
PMC0 PMC1 D13 D12 D11 D10 D9 D8
Default
value
9966
Bit
Name
Default
value
9966
* Program mode control
PMC0 PMC0PMC1 PMC1
0
D7 D6 D5 D4 D3 D2 D1 D0
0
01
* 1 0 0 1 1 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
1 0 1 1 1 01 1
Program mode Program mode
Control Block UPLL_RX. Block
UPLL_Ref. Block UPLL_TX. Block
0 1
1 1
Page 16
KB8527B 1 CHIP CLP SUBSYSTEM IC
- Ref - counter : Setting reference frequency for phase detector ( 12 Bits --> 1/16 ~ 1/4095 )
[ Default_Divider = 2048, X-tal_OSC = 10.240 MHz -->Fref = 5KHz ]
< Ref. Register (16bits) >
Bit
Name
Default
value
2048
Bit
Name
Default
value
2048
-UK_Selection
UK_S0 UK_S1
0
1
0 1
1
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
PMC0 PMC1 UK_S1 UK_S0 D11 D10 D9 D8
* 1 0 0 0
Ref.freq. selection
for United Kingdom
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 0 00 0
FR1 FR2 FrefTX FrefRX
0
0
1
fREF (A)
fREF (A)
fREF/4 (B)
fREF/4 (B)
-
fREF/4 (B)
fREF/25 (C)
fREF/25 (C)
fREF (A)
fREF/4 (B)
fREF/4 (B)
fREF/25 (C)
fREF (A)
fREF/4 (B)
fREF/25 (C)
fREF/4 (B)
12 Bits Reference
program divider.
fREF
(A)
.
fREF 4
.
4
.
.
25
.
.
(B)
.
fREF 25
.
(C)
FR1
FR2
< Reference frequency selection >
LD
PD_TX
PDT
PDR
PD_RX
Page 17
KB8527B 1 CHIP CLP SUBSYSTEM IC
• Control program
Control register (16 Bits)
Bit Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Name
Description
Function
PMC0 PMC1
Program
Mode
Control_0
Program Latch Assign
Program
Mode
Control_1
*
-
Don`t
Care
Don`t
Care
PLLTX-BS
PLL_Tx
Battery
Save
0:Normal
(PLL_TX-On)
1:PLL_TX
Power-Off
CO_M
Compressor
Mute
Selection
0:Normal
1:Mute
CO_BS EX_M EX_BS
Compressor
Battery
Save
0: CO-On
1: Normal
( CO-part
Power-Off )
Expander
Mute
Selection
0:Normal
1:Mute
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name
Description
Function
LDT_CDO LBD-BS
LDT or
CDO
Select
0:Normal
(CDO)
1:LDT
Low
Battery
Detector
Battery
Save
0:Normal
(LBD-ON)
1:LBD-Part
Power-Off
Rx-BS
RX
Battery
Save
0:Normal
(RX-ON)
1:RX-Part
Power-Off
- - -
Don`t
care
Don`t
care
-
Don`t
care
TEST2 TEST1
TEST
Mode 2
* * *
Function Test On
each block of UPLL
Expander
Battery
Save
0: EX-On
1: Normal
( EX-part
Power-Off )
TEST
Mode 1
*** TEST Mode & LDT-CDO Mode
LDT/CDO TEST1 TEST2 LDT / CDO Remark
0
0
1
0
1
0
1
1
0
1
0
0
1
1
0
0
1
1
Rx block CDO
Rx block CDO
4_25cnt block FR2
4_25cnt block FR2
PLL block LDT
PLL block LDT
Test PLL_RX
Test PLL_TX
Default
Page 18
KB8527B 1 CHIP CLP SUBSYSTEM IC
• Operating internal circuit blocks in each mode
Operating circuit blocksMode ( state )
Active state
( Communication mode )
PLL regulator / MICOM I/F ( Data, CLK, EN ) / 2`nd local oscillator / Receiver
/ 1`st local oscillator / RX PLL / Carrier detector / FSK comparator / Low
battery detector / TX PLL / Expander & speaker amp / Compressor /
Splatter filter amp
PLL regulator / MICOM I/F ( Data, CLK, EN ) / 2`nd local oscillator / Receiver
Receiving mode
/ 1`st local oscillator / RX PLL / Carrier detector / FSK comparator / Low
battery detector.
Inactive state
PLL regulator / MICOM I/F ( Data, CLK, EN )
• CLO_LBD - Register Program
[ Rx - 1`st local oscillation internal cap. for U.S.A - 25CH & Low battery detect voltage ]
- CLO register ( 6 bits ) : Receiver 1`st local oscillator internal capacitor selection
Bit Bit10 (MSB) Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name
Default Value
0
Function
PMC CLO5 CLO4 CLO3 CLO2 CLO1 CLO0
1
0 0 0 0 0 0
* * * * *
-
0:Normal
1:Internal
Cap. for
USA 25
Channel
=4.4pF
0:Normal
1:Internal
Cap. for
USA 25
Channel
=1.0pF
0:Normal
1:Internal
Cap. for
USA 25
Channel
=3.6pF
0:Normal
1:Internal
Cap. for
USA 25
Channel
=2.4pF
0:Normal
1:Internal
Cap. for
USA 25
Channel
=1.2pF
*****
PMC ( Program Mode Control )
PMC = `HIGH` & EN = `HIGH` ---> CLO_LBD Register Program Mode
0:Normal
1:Internal
Cap. for
USA 25
Channel
=0.6pF
Page 19
KB8527B 1 CHIP CLP SUBSYSTEM IC
- Rx - Low Battery Detect Voltage
Bit
Name PMC LBD3 LBD2 LBD1 LBD0
Default
Value
Function 1
***** PMC ( Program Mode Control )
PMC = `HIGH` & EN = `HIGH` ---> CLO - LBD Register Program Mode
Bit 10
(MSB)
1
* * * * *
Bit 9 Bit 8 Bit 7 Bit 6
0 0 0 0 - Default
0
1
1
0
1
0
0
1
1
1
0
1
0
1
1
0
1
1
1
1
Low
Battery
Detector
Voltage
3.45V
3.3V
3.0V
2.2V
2.1V
Remark
-
-
-
-
-
* Example 1 >
Low battery detector voltage : 2.1V
U.S.A _CH-#1 ( REMOTE ) ---> 1`st local osc. varicap value =15.86pF, Internal cap = 7.0pF
( Ext_L = 0.45uH, EXT_C = 30pF )
- 12 bit data format
MSB LSB
DATA
EN
CLK
In case the 12 bits programming, insert 1 don`t care bit ( Dummy bit ) between PMC and LBD3.
Dummy
PMC LBD3 LBD2 LBD1 LBD0 CLO5 CLO4 CLO3 CLO2 CLO1 CLO0
1 1 1 1 1 0 1 1 1 0 01( 0 )
bit
Page 20
KB8527B 1 CHIP CLP SUBSYSTEM IC
- In case of setting 16 bit data format
DATA
MSB LSB
PMC LBD3 LBD2 LBD1 LBD0 CLO5 CLO4 CLO3 CLO2 CLO1 CLO0
1 1 1 1 1 0 1 1 1 0 0
1(0)
Dummy
bit
1(0) 1(0) 1(0) 1(0)
EN
CLK
In case of 16 bits programming, insert 5 don`t care bits between the PMC and LBD3
* EXAMPLE DATA FOR U.S.A 25_CHANNEL SELECTION
1`st Local Osc. Internal Capacitor Select
Bit5
(CLO5)
0
0
0
0
0
0
0
Bit4
(CLO4)
0
0
1
0
0
1
1
Bit3
(CLO3)
0
0
0
0
0
1
1
Bit2
(CLO2)
0
0
0
0
0
1
0
Bit1
(CLO1)
0
0
0
1
0
0
1
Bit0
(CLO0)
0
1
1
0
1
0
0
Base
Channels
1 ~ 25CH. 1 ~ 25CH.
16 ~ 25CH.
-
01 ~ 04CH.
05 ~ 10CH.
11 ~ 15CH
-
-
Hand
Channels
-
16 ~ 25CH.
-
-
-
01 ~ 06CH.
07 ~ 15CH.
Varicap
Value
1.0V ~ 2.0V
TYP 1.5V
18.73
~ 15.86pF
18.73
~ 15.86pF
18.73
~ 15.86pF
18.73
~ 15.86pF
18.73
~ 15.86pF
18.73
~ 15.86pF
18.73
~ 15.86pF
ExternalCExternalLInternal
C
27pF
( 30pF )
27pF
30pF
27pF
27pF
27pF
30pF
30pF
0.45uH pF
0.45uH
0.45uH
0.45uH
0.45uH
0.45uH
0.45uH
0.45uH
-
0.6
1.6
1.2
0.6
7.0
5.8
Page 21
KB8527B 1 CHIP CLP SUBSYSTEM IC
• Phase detector / Lock Detector Output Waveforms
2LOI
TIF
REF.Freq.
.
.
TIF N
PDT
12 Bits Reference
program divider.
14 Bits TX.
program divider.
fREF
(A)
fREF 4
.
4
.
.
.
25
(B)
fREF 25
(C)
FR1
.
.
FR2
.
.
REF.Freq
.
.
TIF N
LD
PD_TX
PDT
LD
( Phase Detector / Lock Detector Output Waveform )
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