Datasheet KB3930QF Datasheet (Ene)

KB3930 for OLPC

Keyboard Controller

Data Sheet

V 0.2

May. 2010

ENE RESERVES THE RIGHT TO AMEND THIS DOCUMENT WITHOUT NOTICE AT ANY TIME. ENE ASSUMES NO RESPONSIBILITY FOR ANY ERRORS APPEAR IN THE DOCUMENT, AND ENE DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF ENE PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, OR INFRINGEMENT OF ANY PATENTS, COPYRIGHTS OR OTHER INTELLECTUAL PROPERTY RIGHTS.

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t

KB3930 Keyboard Controller Datasheet

Revision

Revision Description Date

0.1 1. 1

0.2 1. Remove Watermark 2010/5

s

release as KB3930 OLPC datasheet 2010/04 (0.7)

i

KB3930 Keyboard Controller Datasheet

1. GENERAL DESCRIPTION .................................................................................. 0

1.1 OVERVIEW ........................................................................................................ 0

1.2 FEATURES ........................................................................................................ 1

1.3 COMPARISON (KB3926D VS. KB3930).............................................................. 6

1.4 BLOCK DIAGRAM .............................................................................................. 7

2. PIN ASSIGNMENT AND DESCRIPTION ............................................................ 8

2.1 KB3930 128-PIN LQFP DIAGRAM TOP VIEW ..................................................... 8

2.2 KB3930 128 LFBGA BALL MAP ...................................................................... 9

KB3930 PIN ASSIGNMENT SIDE A ................................................................... 10

2.3

2.4 KB3930 PIN ASSIGNMENT SIDE B ................................................................... 11

2.5

KB3930 PIN ASSIGNMENT SIDE C ................................................................... 12

2.6 KB3930 PIN ASSIGNMENT SIDE D ................................................................... 13

2.7 I/O CELL DESCRIPTIONS .................................................................................. 14

2.7.1 I/O Buffer Table ..................................................................................... 14

2.7.2 I/O Buffer Characteristic Table ............................................................ 14

3. PIN DESCRIPTIONS ......................................................................................... 15

3.1 HARDWARE TRAP ........................................................................................... 15

3.2 PIN DESCRIPTIONS BY FUNCTIONS ................................................................... 16

3.2.1 Low Pin Count I/F Descriptions. ......................................................... 16

3.2.2 SPI Flash I/F Descriptions ................................................................... 16

3.2.3 PS/2 I/F Descriptions ............................................................................ 16

3.2.4 Internal Keyboard Encoder (IKB) Descriptions ................................. 17

3.2.5 SMBus Descriptions ............................................................................ 17

3.2.6 FAN Descriptions ................................................................................. 17

3.2.7 Pulse Width Modulation (PWM) Descriptions .................................... 17

3.2.8 Analog-to-Digital Converter Descriptions .......................................... 17

3.2.9 Digital-to-Analog Converter Descriptions .......................................... 18

3.2.10 8051 External I/F Descriptions .......................................................... 18

3.2.11 External Clock Descriptions .............................................................. 18

3.2.12 Miscellaneous Signals Descriptions ................................................ 18

3.2.13 Voltage Comparator Pins Descriptions ............................................ 19

3.2.14 Power Pins Descriptions ................................................................... 19

4. MODULE DESCRIPTIONS ................................................................................ 20

4.1 CHIP ARCHITECTURE ....................................................................................... 20

4.1.1 Power Planes ........................................................................................ 20

4.1.2 Clock Domains ..................................................................................... 21

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KB3930 Keyboard Controller Datasheet

4.1.4 Internal Memory Map ........................................................................... 24

4.2 GPIO ............................................................................................................. 25

4.2.1 GPIO Function Description ................................................................. 25

4.2.2 GPIO Structures ................................................................................... 28

4.2.3 GPIO Attribution Table ......................................................................... 29

4.2.3 GPIO Registers Descriptions .............................................................. 32

4.2.4 GPIO Programming Sample ................................................................ 43

4.3 KEYBOARD AND MOUSE CONTROL INTERFACE (KBC) ....................................... 44

4.3.1 KBC I/F Function Description ............................................................. 44

ENE SERIAL BUS CONTROLLER (ESB) ............................................................ 49

4.4

4.4.1 ESB Function Description ................................................................... 49

4.4.2 ESB Registers Description .................................................................. 50

4.5

RESERVED ...................................................................................................... 56

4.6 PECI ............................................................................................................. 57

4.6.1 PECI Functional Description ............................................................... 57

4.6.2 PECI Register Description (Base address = FCD0h, 16 bytes) ........ 58

4.7 OWM ............................................................................................................ 61

4.7.1 OWM Functional Description .............................................................. 61

4.8 PULSE WIDTH MODULATION (PWM) ................................................................. 65

4.8.1 PWM Function Description .................................................................. 65

4.8.2 PWM Registers Description ................................................................ 66

4.8.3 PWM Programming Sample ................................................................ 68

FAN CONTROLLER ........................................................................................... 69

4.9

4.9.1 Fan Function Description .................................................................... 69

4.9.2 Fan Registers Description ................................................................... 70

4.9.3 Fan Programming Sample ................................................................... 76

4.10

GENERAL PURPOSE TIMER (GPT) .................................................................. 77

4.10.1 GPT Function Description ................................................................. 77

4.10.2 GPT Registers Description ................................................................ 77

4.10.3 GPT Programming Sample ................................................................ 79

4.11 SDI HOST/DEVICE INTERFACE CONTROLLER ................................................... 80

4.11.1 SDI Host/Device Interface Description ............................................. 80

4.11.2 SDI Host Interface Description .......................................................... 80

4.11.2 SDI Device Interface Description ...................................................... 81

4.11.3 SDI Programming Sample ................................................................. 84

4.12 WATCHDOG TIMER (WDT) ............................................................................. 85

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KB3930 Keyboard Controller Datasheet

4.12.1 WDT Function Description ................................................................ 85

4.12.2 WDT Registers Description ............................................................... 85

4.12.3 WDT Programming Sample ............................................................... 88

4.13 LOW PIN COUNT INTERFACE (LPC) ................................................................ 89

4.13.1 LPC Function Description ................................................................. 89

4.13.2 LPC I/O Decode Range ...................................................................... 89

4.13.3 LPC Memory Decode Range ............................................................. 89

4.13.4 FWH Memory Decode Range ............................................................ 90

4.13.5 Index-I/O Port ...................................................................................... 90

4.13.6 Extended I/O Port (Debug Port, Port80) ........................................... 91

4.13.7 LPC Registers Description ................................................................ 92

X-BUS INTERFACE (XBI) ............................................................................. 100

4.14

4.14.1 XBI Function Description ................................................................ 100

4.14.2 XBI SPI Enhancement ...................................................................... 100

4.14.3 XBI Registers Description ............................................................... 103

4.15

CONSUMER IR CONTROLLER (CIR) .............................................................. 109

4.15.1 CIR Function Description ................................................................ 109

4.15.2 CIR Block Diagram ........................................................................... 111

4.15.3 CIR Remote Protocol ....................................................................... 112

4.15.3.1 Philips RC5 Protocol ............................................................................................ 11 2 

4.15.3.2 Philips RC6 Protocol ............................................................................................ 11 3 

4.15.3.3 NEC Protocol ........................................................................................................ 11 3 

4.15.4 CIR Automatic Carrier Frequency Detection and Modulation ...... 114

4.15.5 CIR Registers Description ............................................................... 116

4.15.3 CIR Programming Sample ............................................................... 120

PS/2 INTERFACE (PS/2) .............................................................................. 121

4.16

4.17

EMBEDDED CONTROLLER (EC) .................................................................... 122

4.17.1 EC Function Description ................................................................. 122

4.17.2 EC Command Program Sequence .................................................. 123

4.17.3 EC SCI Generation ........................................................................... 124

4.17.4 EC/KBC Clock Configuration .......................................................... 125

4.17.5 A/D Converter Control ...................................................................... 125

4.17.6 D/A Converter Control ...................................................................... 127

4.17.7 Power Management Control ............................................................ 128

4.17.8 EC Registers Description ................................................................ 129

4.18 GENERAL PURPOSE WAKE-UP CONTROLLER (GPWU) .................................. 140

4.18.1 GPWU Function Description ........................................................... 140

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KB3930 Keyboard Controller Datasheet

4.18.2 GPWU Registers Description .......................................................... 141

4.18.3 GPWU Programming Sample .......................................................... 146

4.19 SYSTEM MANAGEMENT BUS CONTROLLER (SMBUS) .................................... 147

4.19.1 SMBus Function Description .......................................................... 147

4.19.2 SMBus Register Description ........................................................... 149

4.20 8051 MICROPROCESSOR ............................................................................. 154

4.20.1 8051 Microprocessor Function Description ................................... 154

4.20.2 8051 Microprocessor Instruction .................................................... 155

4.20.3 8051 Interrupt Controller ................................................................. 159

4.20.4 Interrupt Enable/Flag Table ............................................................. 160

4.20.5 8051 Special Function Register (SFR) ............................................ 162

4.20.6 8051 Microprocessor Register Description ................................... 163

5. ELECTRICAL CHARACTERISTICS ............................................................... 170

5.1 ABSOLUTE MAXIMUM RATI NG ........................................................................ 170

5.2 DC ELECTRICAL CHARACTERISTICS ............................................................... 170

BQCZ16HIV .................................................................................................. 170

BQC04HIV .................................................................................................... 170

BQCW16HIV ................................................................................................. 171

BCC16HI ....................................................................................................... 171

BQC04HI ....................................................................................................... 172

IQTHI (ADC cell) .......................................................................................... 172

OCT04H (DAC cell) ...................................................................................... 172

BQC08HIV .................................................................................................... 173

BQC04HIVPECI ............................................................................................ 173

A/D & D/A CHARACTERISTICS ....................................................................... 174

5.3

5.5 OPERATING CURRENT ................................................................................... 175

5.6

PACKAGE THERMAL INFORMATION.................................................................. 175

5.7 AC ELECTRICAL CHARACTERISTICS ............................................................... 176

5.7.1 SPI Flash Timing ................................................................................ 176

5.7.2 LPC interface Timing ......................................................................... 177

5.7.3 PS/2 interface Timing ......................................................................... 179

5.7.4 SMBus interface Timing .................................................................... 180

2. SMBUS frequencry dependant ........................................................... 180

5.7.5 PECI interface Timing ........................................................................ 181

5.7.6 OWM interface Timing ....................................................................... 182

6. PACKAGE INFORMATION ............................................................................. 183

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KB3930 Keyboard Controller Datasheet

6.1 LQFP 128-PIN OUTLINE DIAGRAM ................................................................ 183

6.1.1 Top View .............................................................................................. 183

6.1.2 Side View ............................................................................................ 184

6.1.3 Lead View ............................................................................................ 185

6.1.4 LQFP Outline Dimensions ................................................................. 186

6.2 LFBGA 128-PIN OUTLINE DIAGRAM .............................................................. 187

6.2.1 Top View .............................................................................................. 187

6.2.2 Side View ............................................................................................ 188

6.2.3 Bottom View........................................................................................ 189

6.2.4 LFBGA Outline Dimensions .............................................................. 190

PART NUMBER DESCRIPTION ......................................................................... 191

6.3

vi

1. General Description

1.1 Overview

The ENE KB3930 is a highly customized embedded controller (EC) for notebook platforms.

The embedded controller contains industrial standard 8051 microprocessor and provides function of

i8042 keyboard controller basically. KB3930 is embedded LPC interface used to communicate with

Host. KB3930 is designed with Shared-ROM architecture. The EC firmware and system BIOS will

co-exist in single SPI flash. The embedded controller also features rich interfaces for general

applications, such as PS/2 interface, Keyboard matrix encoder, PWM controller, A/D converter, D/A

converter, Fan controller, SMBus controller, GPIO controller, PECI controller, one wire master, SPI

controller, voltage comparator and extended interface (ENE Serial Bus) for more applications, like

capacitive touch button application and GPIO extender.

Compared with last generation of KB3926 series, KB3930 added PECI/OWM, another 2

SMBus, another 2 Fan tachometers, enhanced SPI host/slave controller, voltage comparator,

internal oscillator for newest application. KB3930 also improves structure of other modules including

8051, XBI, LPC, IKB, FAN, WDT, GPIO, ESB, EDI. For detail improvement, please refer the related

section.

1.2 Features

LPC Low Pin Count Interface

SIRQ supporting IRQ1, IRQ12, SCI or SMI# interrupt and one programmable

I/O Address Decoding:

Memory Decoding:

Compatible with LPC specification v1.1

Support LPC interface re-direction to IKB for debugging

KB3930 Keyboard Controller Datasheet

IRQ provided.

 Legacy KBC I/O port 60h/64h

 Programmable EC I/O port, 62h/66h(recommend)

 I/O port 68h/6Ch (sideband)

 2 Programmable 4-byte Index-I/O ports to access internal EC registers.

 1 Programmable extended (debug) port I/O.

 Firmware Hub decode

 LPC memory decode

X-bus Bus Interface (XBI) : Flash Interface

SPI flash is supported, size up to 4MB.

SPI frequency supports 33/45/66MHz.

New SPI command (dual read) to enhance the performance.

The 64KB code memory can be mapped into system memory by one 16KB and

one 48KB programmable pages independently.

Support SPI flash in-system-programming via IKB pins.

Enhanced pre-fetch mechanism.

8051 Microprocessor

Compatible with industrial 8051 instructions with 3 cycles.

8051 runs at 8/16/22 MHz, programmable.

256 bytes internal RAM and 4KB tight-coupled SRAM.

24 extended interrupt sources.

Two 16-bit timers.

Full duplex UART integrated.

Supports idle and stop mode.

Enhanced ENE debug interface.

Support Tx/Rx re-direction to IKB for debugging

1

8042 Keyboard Controller

8 standard 8042 commands processed by hardware.

Each hardware command can be optionally processed by firmware.

Pointing device multiplex mode support.

Fast GA20 and KB reset support.

PS/2 Controller

Support at most 3 external PS/2 devices.

External PS/2 device operation in firmware mode.

Internal Keyboard Matrix (IKB)

18x8 keyboard scan matrix.

Support W2K Internet and multimedia keys.

Support hotkey events defined.

Ghost key cancellation mechanism provided.

KB3930 Keyboard Controller Datasheet

Enhanced de-bounce feature added

Embedded Controller (EC)

ACPI Spec 2.0 compliant.

5 standard EC command supported directly by hardware.

Each hardware command can be processed by firmware optionally.

Programmable EC I/O ports, 62h/66h by default.

SMBus Host Controller

4 SMBus interfaces with 2 SMBus controllers

SMBus Spec 2.0 compliant.

Byte mode support.

Slave function support.

Digital-to-Analog Converter (DAC)

4 DAC channels with 8-bit resolution.

All DAC pins can be alternatively configured as GPO (general purpose output)

function.

2

Analog-to-Digital Converter (ADC)

6 ADC channels with 10-bit resolution.

All ADC pins can be alternatively configured as GPI (general purpose input)

function.

Pulse Width Modulator (PWM)

6 PWM channels are provided. (8-bit *2, 14-bit *2 and FANPWM(12-bit) *2)

Clock source selectable:.

 1MHz/64KHz/4KHz/256Hz (for 8-bit PWM)

 Peripheral clock or 1MHz (for 14-bit PWM)

 Peripheral clock (for FANPWM)

Duty cycle programmable and cycle time up to 1 sec(for 8-bit PWM)

Watch Dog Timer (WDT)

32.768KHz input clock.

KB3930 Keyboard Controller Datasheet

10-bit counter with 32ms unit for watchdog reset.

Three watchdog reset mechanisms.

 Reset 8051 only

 Reset whole chip, except GPIO module.

 Reset whole chip including GPIO module.

Real Time Clock

32.768KHz input clock.

24-bit timer support.

General Purpose Timer (GPT)

Two 16-bit and two 8-bit general purpose timer with 32.768KHz clock source.

General Purpose Wakeup (GPWU)

Those I/O with GPI (general purpose input) configuration can generate

interrupts or wakeup events, except those pins named in GPXIOAxx.

3

General Purpose Input/Output (GPIO)

All general purpose I/O can be programmed as input or output.

All output pins can be configured to be tri-state optionally.

All input pins are equipped with pull-up, high/low active and edge/level trigger

selection.

For the pins of DAC can be configured as GPO function only.

For the pins of ADC can be configured as GPI function only.

A specific pair of GPIO pins with signal pass-through feature.

FAN Controller

Two fan controllers with tachometer inputs.

Automatic fan control support.

12-bit FANPWM support.

Enhanced FAN tracking resolution added

KB3930 Keyboard Controller Datasheet

Consumer IR (CIR)

Several protocols decoded/encoded by hardware.

Interrupt for CIR application.

Support wide/narrow band receiver.

Transmit/Receive simultaneously.

Remote power-on support.

ENE Serial Bus Interface (ESB)

A proprietary and flexible interface for extension with ENE KBC.

Firmware accesses ESB devices via internal memory address directly.

Interrupt capability.

ENE Debug Interface (EDI)

Flexible debug interface with SPI pins.

Keil-C development tool compatible

SPI Device Interface (SDI)

An enhanced SPI host/device controller is embedded.

Flexible design for SPI applications.

4

One Wire Master Interface

Embedded One Wire controller used to control one wire devices.

KB3930 Keyboard Controller Datasheet

PECI

Support Intel PECI

Support wide speed range from 2Kbps to 2Mbps.

Power Management

Sleep mode: 8051 program counter (PC) stops and enters idle mode.

Deep sleep mode: All clocks stop except external 32.768KHz OSC. 8051 enters

stop mode.

Misc.

Support two hardware voltage comparator (initialed by F/W, operated by H/W),

two voltage input sources and one digital output, used to detect abnormal

situation (like over temperature).

Support two output pins to report KB3930 power fail status.

Package

128-pin LQFP package, Lead Free (RoHS).

5

KB3930 Keyboard Controller Datasheet

1.3 Comparison (KB3926D vs. KB3930)

Microprocessor 8051 8051 Built-in SRAM 2KB 4KB LPC 2 index-I/O sets 2 index I/O sets X-Bus SPI ROM: 4MB

Enhanced pre-fetch mechanism. Real Time Clock Support Support ADC Six 10-bit ADC channels Six 10-bit ADC channels DAC Four 8-bit DAC channels Four 8-bit DAC channels WDT 128ms timer unit with 8bits control 32ms timer unit with 10bits control PWM 6 sets

PWM0/1 – 8 bit

PWM2/3 – 14 bit

FANPWM0/1 – 12 bit External PS/2 I/F 3 3 GPIO Programmable Bi-direction I/O

GPIO pass through : 1 pair

Max GPIO: 100 IKB Matrix 18x8 18x8 FAN controller 2 2 (Enhanced precision and 2

GPT 4 4 SMBus 2

Byte mode support CIR Hardware encode/decode

IRQ and I/O port support

Carrier frequency calculation

TX with carrier modulation

Learning mode support

TX/RX simultaneously EDI Enhanced Enhanced (Support break point) ESB Support Support SDI Support Support both SPI host/device Package 128 LQFP 128 LQFP Dimension 14mmx14mm 14mm x 14 mm New-added

PECI Function

KB3926D KB3930

SPI ROM: 4MB Enhanced pre-fetch mechanism.

6 sets PWM0/1 – 8 bit PWM2/3 – 14 bit FANPWM0/1 – 12 bit

Enhanced Bi-direction I/O cell

GPIO pass through : 1 pair Max GPIO: 100

additional Tachometer Monitors)

4

Byte mode support Hardware encode/decode IRQ and I/O port support Carrier frequency calculation TX with carrier modulation Learning mode support TX/RX simultaneously

One Wire Master POFR signals Voltage Comparator

6

1.4 Block Diagram

KB3930 Keyboard Controller Datasheet

7

2. Pin Assignment and Description

2.1 KB3930 128-pin LQFP Diagram Top View

KB3930 Keyboard Controller Datasheet

8

KB3930 Keyboard Controller Datasheet

2.2 KB3930 128 LFBGA Ball Map

This page is leaved blank intentionally.

9

2.3 KB3930 Pin Assignment Side A

KB3930

Pin No.

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

KB3930

BGA

1

2

3

4

5

6

7

8

9

Name GPIO Alt

GA20 GPIO00 GA20 GPIO00 HiZ / HiZ BQC04HIV

KBRST# GPIO01 KBRST# GPIO01 HiZ / HiZ BQC04HIV

SERIRQ HiZ / HiZ BCC16HI

LFRAME# HiZ / HiZ BCC16HI

LAD3 HiZ / HiZ BCC16HI

GPIO04 GPIO04 GPIO04 HiZ / HiZ BQC04HIV

LAD2 HiZ / HiZ BCC16HI

LAD1 HiZ / HiZ BCC16HI

VCC VCC

LAD0 HiZ / HiZ BCC16HI

GND GND

PCICLK IE/IE BCC16HI

PCIRST# GPIO05 PCIRST# GPIO05 HiZ / IE BCC16HI

GPIO07 GPIO07 i_clk_8051 GPIO07 HiZ / HiZ BQC04HIV

GPIO08 GPIO08 i_clk_peri GPIO08 HiZ / HiZ BQC04HIV

GPIO0A GPIO0A OWM RLC_RX2

GPIO0B GPIO0B ESB_CLK GPIO0B PU / PU BQCW16HIV

GPIO0C GPIO0C ESB_DAT ESB_DAT GPIO0C HiZ / HiZ BQC08HIV

GPIO0D GPIO0D RLC_TX2 GPIO0D HiZ / HiZ BQC04HIV

SCI# GPIO0E SCI# GPIO0E HiZ / HiZ BQC04HIV

PWM0 GPIO0F PWM0 GPIO0F HiZ / HiZ BQC16HIV

VCC VCC VCC

PWM1 GPIO10 PWM1 GPIO10 HiZ / HiZ BQC04HIV

GND GND GND

GPIO11 GPIO11 PWM2 GPIO11 HiZ / HiZ BQC04HIV

FANPWM0 GPIO12 FANPWM0 GPIO12 HiZ / HiZ BQC04HIV

FANPWM1 GPIO13 FANPWM1 GPIO13 HiZ / HiZ BQC04HIV

FANFB0 GPIO14 FANFB0 GPIO14 HiZ / HiZ BQC04HIV

FANFB1 GPIO15 FANFB1 GPIO15 HiZ / HiZ BQC04HIV

GPIO16 GPIO16 E51TXD GPIO16 HiZ / HiZ BQC04HIV

GPIO17 GPIO17 E51CLK E51RXD GPIO17 HiZ / HiZ BQC04HIV

GPIO18 GPIO18 GPIO18 HiZ / HiZ BQC04HIV

Output

KB3930 Keyboard Controller Datasheet

Alt.

Input

OWM

Default ECRST#

L/H

GPIO0A HiZ / HiZ BQC04HIV

IO CELL

10

2.4 KB3930 Pin Assignment Side B

KB3930

Pin No.

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

KB3930

BGA

Name GPIO Alt

VCC VCC

GPIO19 GPIO19 PWM3 GPIO19 HiZ / HiZ BCC16HI

GND GND

GPIO1A GPIO1A NUMLED# GPIO1A HiZ / HiZ BCC16HI

ECRST# IE / IE BQC04HIV

CLKRUN# GPIO1D CLKRUN# CLKRUN# GPIO1D HiZ / HiZ BCC16HI

KSO0 GPIO20 KSO0 TP_TEST GPIO20 IE(PU)/IE(PU) BQC04HIV

KSO1 GPIO21 KSO1 TP_PLL GPIO21 IE(PU)/IE(PU) BQC04HIV

KSO2 GPIO22 KSO2 TP_TMUX GPIO22 IE(PU)/IE(PU) BQC04HIV

KSO3 GPIO23 KSO3 TP_ISP GPIO23 IE(PU)/IE(PU) BQC04HIV

KSO4 GPIO24 KSO4 GPIO24 HiZ / HiZ BQC04HIV

KSO5 GPIO25 KSO5 PCICLK

KSO6 GPIO26 KSO6 PCIRST#

KSO7 GPIO27 KSO7

SERIRQ(LPC) SERIRQ(LPC)

KSO8 GPIO28 KSO8 LFRAME#

KSO9 GPIO29 KSO9 GPIO29 HiZ / HiZ BQCZ16HIV

KSO10 GPIO2A KSO10 GPIO2A HiZ / HiZ BQCZ16HIV

KSO11 GPIO2B KSO11

KSO12 GPIO2C KSO12

KSO13 GPIO2D KSO13

KSO14 GPIO2E KSO14

KSO15 GPIO2F KSO15 E51_RXD GPIO2F HiZ / HiZ BQC04HIV

KSI0 GPIO30 E51_TXD KSI0 GPIO30 IE(PU)/IE(PU) BQC04HIV

KSI1 GPIO31 KSI1 GPIO31 IE(PU)/IE(PU) BQC04HIV

KSI2 GPIO32 KSI2 GPIO32 IE(PU)/IE(PU) BQC04HIV

KSI3 GPIO33 KSI3 GPIO33 IE(PU)/IE(PU) BQC04HIV

KSI4 GPIO34 KSI4/EDI_CS GPIO34 IE(PU)/IE(PU) BQC04HIV

KSI5 GPIO35 KSI5/EDI_CLK GPIO35 IE(PU)/IE(PU) BQC04HIV

KSI6 GPIO36 KSI6/EDI_DIN GPIO36 IE(PU)/IE(PU) BQC04HIV

KSI7 GPIO37 EDI_DO KSI7 GPIO37 IE(PU)/IE(PU) BQC04HIV

AD0 GPI38 AD0 GPI38 HiZ / HiZ IQTHI

AD1 GPI39 AD1 GPI39 HiZ / HiZ IQTHI

Output

LAD3(LPC)

LAD2(LPC)

LAD1(LPC)

LAD0(LPC)

KB3930 Keyboard Controller Datasheet

Alt.

Input

(LPC)

LAD3(LPC)

LAD2(LPC)

LAD1(LPC)

LAD0(LPC)

Default ECRST#

L/H

GPIO25 HiZ / HiZ BQCZ16HIV

GPIO26 HiZ / HiZ BQC04HIV

GPIO27 HiZ / HiZ BQC04HIV

GPIO28 HiZ / HiZ BQC04HIV

GPIO2B HiZ / HiZ BQC04HIV

GPIO2C HiZ / HiZ BQC04HIV

GPIO2D HiZ / HiZ BQC04HIV

GPIO2E HiZ / HiZ BQC04HIV

IO CELL

11

2.5 KB3930 Pin Assignment Side C

KB3930

Pin No.

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

KB3930

BGA

Name GPIO Alt

AD2 GPI3A AD2 GPI3A HiZ / HiZ IQTHI

AD3 GPI3B AD3 GPI3B HiZ / HiZ IQTHI

AVCC AVCC

DA0 GPO3C DA0 GPO3C HiZ / HiZ OCT04H

AGND AGND

DA1 GPO3D DA1 GPO3D HiZ / HiZ OCT04H

DA2 GPO3E DA2 GPO3E HiZ / HiZ OCT04H

DA3 GPO3F DA3 GPO3F HiZ / HiZ OCT04H

GPIO40 GPIO40 CIR_RX GPIO40 HiZ / HiZ BQC04HI

GPIO41 GPIO41 CIR_RLC_TX

AD4 GPI42 AD4 GPI42 HiZ / HiZ IQTHI

AD5 GPI43 AD5 GPI43 HiZ / HiZ IQTHI

SCL0 GPIO44 SCL0 GPIO44 HiZ / HiZ BQC04HI

SDA0 GPIO45 SDA0 GPIO45 HiZ / HiZ BQC04HI

SCL1 GPIO46 SCL1 GPIO46 HiZ / HiZ BQC04HI

SDA1 GPIO47 SDA1 GPIO47 HiZ / HiZ BQC04HI

KSO16 GPIO48 KSO16 GPIO48 HiZ / HiZ BQC04HIV

KSO17 GPIO49 KSO17 GPIO49 HiZ / HiZ BQC04HIV

PSCLK1 GPIO4A

PSDAT1 GPIO4B

PSCLK2 GPIO4C

PSDAT2 GPIO4D PSDAT2

PSCLK3 GPIO4E PSCLK3 GPIO4E HiZ / HiZ BQC04HI

PSDAT3 GPIO4F PSDAT3 GPIO4F HiZ / HiZ BQC04HI

GPIO50 GPIO50 GPIO50 HiZ / HiZ BQC04HI

GPIO52 GPIO52 E51CS# GPIO52 HiZ / HiZ BCC16HI

GPIO53 GPIO53 CAPSLED# E51TMR1 GPIO53 HiZ / HiZ BCC16HI

GPIO54 GPIO54 WDT_LED# E51TMR0 GPIO54 HiZ / HiZ BCC16HI

GPIO55 GPIO55 SCROLED# E51INT0 GPIO55 HiZ / HiZ BCC16HI

GND GND

GPIO56 GPIO56 E51INT1 GPIO56 HiZ / HiZ BQC04HIV

VCC VCC

PSCLK1 / SCL2

PSDAT1 / SDA2

Output

/ PECI

PSCLK2

/ SCL3

/ SDA3

KB3930 Keyboard Controller Datasheet

Alt.

Input

PECI

GPIO4A HiZ / HiZ BQC04HI

GPIO4B HiZ / HiZ BQC04HI

GPIO4C HiZ / HiZ BCC16HI

GPIO4D HiZ / HiZ BCC16HI

Default ECRST#

L/H

GPIO41 HiZ / HiZ BQC04HIVPECI

IO CELL

12

2.6 KB3930 Pin Assignment Side D

KB3930

Pin No.

97

98

99

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

KB3930

BGA

Name GPIO Alt

GPXIOA00 GPXIOA00 SDICS# HiZ / HiZ BQC04HIV

GPXIOA01 GPXIOA01 SDICLK HiZ / HiZ BQC04HIV

GPXIOA02 GPXIOA02 SDIMOSI HiZ / HiZ BQC04HIV

GPXIOA03 GPXIOA03 FANFB2 HiZ / HiZ BQC04HIV

GPXIOA04 GPXIOA04 FANFB3 HiZ / HiZ BQC04HIV

GPXIOA05 GPXIOA05 HiZ / HiZ BQC04HIV

GPXIOA06 GPXIOA06 VCOUT HiZ / HiZ BQC04HIV

GPXIOA07 GPXIOA07 HiZ / HiZ BQC04HIV

GPXIOA08 GPXIOA08 HiZ / HiZ BQCZ16HIV

GPXIOA09 GPXIOA09 HiZ / HiZ BQCZ16HIV

GPXIOA10 GPXIOA10 HiZ / HiZ BQCZ16HIV

GPXIOA11 GPXIOA11 HiZ / HiZ BQCZ16HIV

GPXIOD00 GPXIOD00 SDIMISO

GPXIOD01 GPXIOD01 HiZ / HiZ BQC04HIV

VCC

GPXIOD02 GPXIOD02

GND HiZ / HiZ GND

GPXIOD03 GPXIOD03 VCIN1 HiZ / HiZ BQC04HIV

GPXIOD04 GPXIOD04 HiZ / HiZ BQC04HIV

GPXIOD05 GPXIOD05 HiZ / HiZ BQC04HIV

GPXIOD06 GPXIOD06 HiZ / HiZ BQC04HIV

GPXIOD07 GPXIOD07

MISO

MOSI MOSI MOSI HiZ / Ox BQCZ16HIV

GPIO57 GPIO57 XCLK32K GPIO57 HiZ / HiZ BQC04HIV

XCLKI

XCLKO

V18R

VCC VCC

SPICLK GPIO58 SPICLK SPICLK HiZ / Ox BQCW16HIV

GPIO59 GPIO59 TEST_CLK

SPICS# SPICS# SPICS# HiZ / Ox BQCZ16HIV

Output

KB3930 Keyboard Controller Datasheet

Alt.

Input

VCIN0

HiZ / HiZ VCC

HiZ / HiZ BQC04HIV

MISO MISO HiZ / IE BQCZ16HIV

SPICLKI

Default ECRST#

L/H

HiZ / HiZ BQC04HIV

GPIO59 IE / IE BQC04HIV

IO CELL

13

KB3930 Keyboard Controller Datasheet

2.7 I/O Cell Descriptions

2.7.1 I/O Buffer Table

Cell Description Application

BQCZ16HIV Schmitt trigger, 16mA Output / Sink Current, Input / Output / Pull Up

Enable(40K

BQC04HIV Schmitt trigger, 4mA Output / Sink Current, Input / Output / Pull Up Enable(40K

Ω), 5 V Tolerance

BQCW16HIV Schmitt trigger, 16mA Output / Sink Current, 5 V Tolerance, Input / Output / Pull

Up Enable

BCC16HI 16mA Output / Sink Current , 5 V Tolerance, Input / Output Enable LPC I/F

BQC04HI Schmitt trigger, 4mA Output / Sink Current, 5 V Tolerance, Input / Output

Enable

IQTHI Mixed mode IO, ADC Enable, with GPI, Input Enable ADC, GPI

OCT04H Mixed mode IO, DAC Enable, with GPO, 4mA Output Current, Output Enable

(For GPO function, it is not recommended to control the device powered before KBC chip.)

BQC08HIV Schmitt trigger, 8mA Output / Sink Current, 5V Tolerance, Input / Output / Pull

Up Enable

BQC04HIVPECI

Mixed Mode IO, PECI enable, with GPIO

GPIO: Schmitt trigger, 4mA Output / Sink Current,

PECI: 0.9V~1.2V

** Please note, the total current in each side on VCC or VSS of chip can not exceed over 48mA.

Ω), 5 V Tolerance.

* 5V Tolerance, only if pull-high disable and output disable.

GPIO

ESB_CLK/

SPI_CLK

GPIO

DAC, GPO

ESB_DAT

PECI, GPIO

2.7.2 I/O Buffer Characteristic Table

Cell Output Input

BQCZ16HIV

Analog

Signal

ˇ ˇ ˇ ˇ

Pull-High

Enable(40k)

5V

Tolerance

Current

(mA)

8~16

Application

GPIO

BQC04HIV

BQCW16HIV

BCC16HI

BQC04HI

IQTHI

OCT04H

BQC08HIV

BQC04HIVPECI

ˇ ˇ ˇ ˇ

ˇ ˇ ˇ

ˇ ˇ

ˇ ˇ ˇ ˇ

2~4

8~16

2~4

4~8

2~4

GPIO

ESB_CLK/

SPI_CLK

LPC I/F

GPIO

ADC, GPI

DAC, GPO

ESB_DAT

PECI, GPIO

Application Notice: The Pads with I/O cells of IQTHI, OCT04H should be designed carefully. Under specific environment when: KBC is power-off, external application circuit is power-on. Signals must not be connected with pads of IQTHI/OCT04H (ADCs/DACs). It would cause unexpected voltage level on these pad if KBC is still power-off.

14

KB3930 Keyboard Controller Datasheet

3. Pin Descriptions

3.1 Hardware Trap

Hardware trap pins are used to latch external signal at rising edge of ECRST#. The hardware

trap pins are for some special purpose which should be defined while boot-up. The following table

gives the collection of hardware trap pins. Please note, all the following hardware trap pins are

pull-high internally after reset.

Trap Name Pin No. Description

TP_TEST

(GPIO20,KSO0)

TP_PLL

(GPIO21,KSO1)

TP_TMUX

(GPIO22,KSO2)

TP_ISP

(GPIO23,KSO3)

＊ Please note while TP_TMUX and TP_ISP keep low at the same time, a mechanism called FlashDirectAccess will

enable. That is, users can flush and program a SPI flash via specific IKB pins with external tool.

FlashDirectAccess:

The KBC provides a new interface to program SPI flash via IKB interface. With this feature, users can easily utilize 4 pins from keyboard matrix (IKB) without disassembly whole machine. These 4 pins are connected directly to external SPI-Flash interface. The following table shows the mapped pins while entering FlashDirectAccess mode.

Pin No. Normal Mode FlashDirectAccess Mode

59 KSI4 (I) (Input) EDI_CS, Transfer signal from terminal into KBC and though SPICS# to SPI_Flash

60 KSI5 (I) (Input) EDI_CLK, Transfer signal from terminal into KBC and though SPICLK to SPI_Flash

61 KSI6 (I) (Input) EDI_DIN, Transfer signal from terminal into KBC and though MOSI to SPI_Flash

62 KSI7 (I) (Output) EDI_DO, Transfer signal from terminal into KBC and though MISO to SPI_Flash

39

40

41

42

While this trap is asserted to be low, the internal DPLL circuit uses other clock source for reference, instead of 32KHz oscillator.

Low: test clock mode enable High: normal mode using 32KHz oscillator.

While this trap is asserted to be low, some DPLL related signals can be output for test.

Low: DPLL test mode enable. High: DPLL test mode disable

TestMux Mode Trap

Low: Test mode High: Normal operation

While this trap is asserted to be low, SPI Flash can be programmed with ISP mode

Low: SPI flash programming in ISP mode enable ＊ High: SPI flash programming in ISP mode disable

15

KB3930 Keyboard Controller Datasheet

3.2 Pin Descriptions by Functions

3.2.1 Low Pin Count I/F Descriptions.

Pin Name Pin No. Direction Description

LAD[3:0] 5, 7,8,10 I/O LPC address bus.

LFARAME# 4 I LPC frame control signal.

PCIRST# 13 I LPC module reset by this signal.

PCICLK 12 I 33MHz PCI clock input.

SERIRQ 3 I/O Serial IRQ

CLKRUN# 38 I/OD Clock run control

3.2.2 SPI Flash I/F Descriptions

Pin Name Pin No. Direction Description

MISO 119 I SPI read control signal

MOSI 120 O SPI write control signal

SPICLK 126 O SPI clock output

SPICS# 128 O SPI chip select signal

These pins are input/output disable during reset phase.

3.2.3 PS/2 I/F Descriptions

Pin Name Pin No. Direction Description

PSCLK1 83 I/OD PS/2 port 1 clock

Muxed with SMBus port 2 clock

PSDAT1 84 I/OD PS/2 port 1 data

Muxed with SMBus port 2 data

PSCLK2 85 I/OD PS/2 port 2 clock

Muxed with SMBus port 3 clock

PSDAT2 86 I/OD PS/2 port 2 data

Muxed with SMBus port 3 data

PSCLK3 87 I/OD PS/2 port 3 clock

PSDAT3 88 I/OD PS/2 port 3 data

16

KB3930 Keyboard Controller Datasheet

3.2.4 Internal Keyboard Encoder (IKB) Descriptions

Pin Name Pin No. Direction Description

KSO[17:0] 82,81,54-39 O Keyboard Scan Out

KSI[7:0] 62-55 I Keyboard Scan In

3.2.5 SMBus Descriptions

Pin Name Pin No. Direction Description

SCL0 77 I/OD SMBus clock (interface 0)

SDA0 78 I/OD SMBus data (interface 0)

SCL1 79 I/OD SMBus clock (interface 1)

SDA1 80 I/OD SMBus data (i`nterface 1)

SCL2 83 I/OD SMBus clock (interface 2)

Muxed with PS/2 port 1 clock

SDA2 84 I/OD SMBus data (interface 2)

Muxed with PS/2 port 1 data

SCL3 85 I/OD SMBus clock (interface 3)

Muxed with PS/2 port 2 clock

SDA3 86 I/OD SMBus data (interface 3)

Muxed with PS/2 port 2 data

3.2.6 FAN Descriptions

Pin Name Pin No. Direction Description

FANPWM0 26 O FANPWM0 output

FANPWM1 27 O FANPWM1 output

FANFB0 28 I FAN0 tachometer input

FANFB1 29 I FAN1 tachometer input

FANFB2 100 I FAN2 tachometer input

FANFB3 101 I FAN3 tachometer input

3.2.7 Pulse Width Modulation (PWM) Descriptions

Pin Name Pin No. Direction Description

PWM0 21 O PWM pulse output

PWM1 23 O PWM pulse output

PWM2 25 O PWM pulse output

PWM3 34 O PWM pulse output

3.2.8 Analog-to-Digital Converter Descriptions

Pin Name Pin No. Direction Description

AD[3:0] 66-63 I 10bit A/D converter input

AD[5:4] 76,75 I 10bit A/D converter input

17

KB3930 Keyboard Controller Datasheet

3.2.9 Digital-to-Analog Converter Descriptions

Pin Name Pin No. Direction Description

DA[3:0] 72-70,68 O 8bit D/A converter output

3.2.10 8051 External I/F Descriptions

Pin Name Pin No. Direction Description

E51TXD 30 O 8051 serial port, transmit port.

E51RXD 31 I 8051 serial port, receive port.

E51CLK 31 O For different serial scheme, E51CLK will shift out clock.

E51CS# 90 O

E51TMR0 92 I

E51INT0 93 I

E51TMR1 91 I

E51INT1 95 I

3.2.11 External Clock Descriptions

Pin Name Pin No. Direction Description

XCLKI 122 I 32.768KHz input

XCLKO 123 O 32.768KHz output

3.2.12 Miscellaneous Signals Descriptions

Pin Name Pin No. Direction Description

GA20 1 O KBC will gate A20 address line

KBRST# 2 O KBRST# is used to generate system reset.

SCI# 20 O SCI# asserts to the system for requesting service while

related events occur.

ECRST# 37 I While ECRST# asserted, the KBC will reset globally.

OWM 16 I/O One Wire Master input and output signal

PECI 74 I/O PECI input and output signal

18

KB3930 Keyboard Controller Datasheet

3.2.13 Voltage Comparator Pins Descriptions

Pin Name Pin No. Direction Description

VCIN0 109 I Voltage comparator input port0

VCIN1 114 I Voltage comparator input port1

VCOUT 103 O Voltage comparator output

3.2.14 Power Pins Descriptions

Pin Name Pin No. Direction Description

VCC 9,22,33,96,111,125 Power supply for digital plane.

GND 11,24,35,94,113 Power ground for digital plane.

AVCC 67 Power supply for analog plane.

AGND 69 Power ground for analog plane.

V18R 124 Connected to external Capacitor for internal 1.8V

19

KB3930 Keyboard Controller Datasheet

4. Module Descriptions

4.1 Chip Architecture

4.1.1 Power Planes Two power planes are in the KBC. One is for digital logic and the other is for analog

circuit. Both power planes are ±10% tolerance for recommend operation condition, The KBC

provides V1.8 power plane for different generation.

Power Plane Description Power Ground

Digital Plane This power provides power for all digital logic no matter what

power mode is.

Analog Plane This power provides power for all analog logic, such as A/D

and D/A converter.

Digital V1.8 The system inputs 3.3V power and the internal regulator

outputs 1.8V voltage. The 1.8V output should connect a capacitor for stable purpose.

VCC GND

AVCC AGND

V1.8 GND

20

KB3930 Keyboard Controller Datasheet

4.1.2 Clock Domains

Three clock sources, PCICLK, DPLL_CLK and XCLKI will be discussed in this section. A

summary is list in the following table.

Clock Description

PCICLK PCI clock 33MHz for LPC I/F.

DPLL_CLK Main clock for 8051/peripheral. DPLL clock can be generated with or without XCLK for

reference. DPLL clock can be divided for different applications. Fig. 4-1 gives an example for illustration.

XCLKI External 32.768KHz for reference.

The following figure shows more detail about the operation in the KBC. The external

32.768KHz is provided for two purposes. One is to provide an accurate reference for internal DPLL

module, and the other one is to provide another clock source for watchdog timer.

The possible (X,Y,Z) combination with exact clock value is summarized as the following table.

CLKCFG[3:2]=0

(default)

CLKCFG[3:2]=1

CLKCFG[3:2]=2

CLKCFG[3:2]=3

* While power on default, no matter what value CLKCFG[3:2], CLKCFG[6] are, the dividend (X,Y,Z) is always (4,

8, 16). The PCI clock is 66MHz, X= 66/4 = 16MHz, Y= 66/8 = 8Mhz , Z= 66/16 = 4MHz

Be noted that, these clock frequency is only valid after KBC correctly referring clock.

CLKCFG[6]=0

SPI Clock (X) Main Clock (Y) Peripheral Clock (Z)

CLKCFG[6]=1 CLKCFG[6]=0

(default)

16* 66 8* 8 4* 4

32 66 16 16 8 8

32 66 22 22 11 11

32 66 32 32 16 16

(default)

CLKCFG[6]=1 CLKCFG[6]=0

(default)

CLKCFG[6]=1

21

KB3930 Keyboard Controller Datasheet

Note: Internal OSC of KBx930 application

Since KBx930 provide internal OSC, the clock source selection are different

from KBx926D series. Developer could chose clock source from internal-OSC,

external crystal, or host LPCLCK depending on different application and system

status. As following is simplified clocking distribution tree for setting.

22

KB3930 Keyboard Controller Datasheet

4.1.3 PCICLK and CLKRUN#

While system power-on, the host starts to drive CLKRUN# low for a while to inform the slaves

that a 33MHz PCICLK will be given. At this moment, CLKRUN# of KBC is in input mode. If the host

tries to stop the PCICLK for some purpose, the CLKRUN# will be de-asserted. In the current design,

the KBC needs PCICLK for normal operation. Therefore the KBC keeps CLKRUN# for 2 clock

cycles and releases it. This forces the host to start driving PCICLK. The following figure gives the

explanation. For more detail please refer to PCI Mobile Design Guide version 1.1.

23

KB3930 Keyboard Controller Datasheet

4.1.4 Internal Memory Map

No Module Descriptions Address Range Size (Byte)

1 Flash Space mapped to system BIOS 0x0000~0xEBFF 59K

2 XRAM Embedded SRAM 0xEC00~0xFBFF 4K

3 GPIO General purpose I/O 0xFC00~0xFC7F 128

4 KBC Keyboard controller 0xFC80~0xFC8F 16

5 ESB ENE serial bus controller 0xFC90~0xFC9F 16

6 IKB Internal keyboard matrix 0xFCA0~0xFCAF 16

7 RSV Reserved 0xFCB0~0xFCBF 16

8 RSV Reserved 0xFCC0~0xFCCF 16

9 PECI PECI controller 0xFCD0~0xFCDF 16

10 RSV Reserved 0xFCE0~0xFCEF 16

11 OWM One Wire Master 0xFCF0~0xFCFF 16

12 RSV Reserved 0xFD00~0xFDFF 256

13 PWM Pulse width modulation 0xFE00~0xFE1F 32

14 FAN Fan controller 0xFE20~0xFE4F 48

15 GPT General purpose timer 0xFE50~0xFE6F 32

16 SDIH/

SDID

17 WDT Watchdog timer 0xFE80~0xFE8F 16

18 LPC Low pin count interface 0xFE90~0xFE9F 16

19 XBI X-bus interface 0xFEA0~0xFEBF 32

20 CIR Consumer IR controller 0xFEC0~0xFECF 16

21 RSV Reserved 0xFED0~0xFEDFh 16

22 PS2 PS/2 interface 0xFEE0~0xFEFF 32

23 EC Embedded controller 0xFF00~0xFF2F 48

24 GPWU General purpose wakeup event 0xFF30~0xFF7F 80

25 SMBus System management bus controller 0xFF80~0xFFBF 64

26 RSV Reserved 0xFFC0~0xFFCF 16

27 RSV Reserved 0xFFD0~0xFFFF 48

SPI host interface/

SPI device interface

0xFE70~0xFE7F 16

1K

24

KB3930 Keyboard Controller Datasheet

4.2 GPIO

GPIOFSx is only for Output Function Selection, not for Input Function. Example1 – GPIO14 is used as FANFB1, then GPIO(GPIOFS10) 0xFC02 b’4 must be 0, GPIO(GPIOIE10) 0xFC62 b’4 must be 1. Example2 – PS/2 clock/data lines and SMBus clock/data are bi-directional. They must be programmed as Output Function Selection = 1 and Input Enable = 1. For other specific GPIO initialization, please refer the SW programming guide of KBx930.

4.2.1 GPIO Function Description

The GPIO module is flexible for different applications. Each GPIO pin can be configured

as alternative input or alternative output mode. The alternative function can be selected by register

setting. A summary table is given as below for more detail.

GPIO Alt. Output Alt. Input Default Alt. Output Alt. Selection Reg.

GPIO00 GA20 GPIO00 GPIOFS00.[0]

GPIO01 KBRST# GPIO01 GPIOFS00.[1]

GPIO02＊

GPIO03＊

GPIO04 GPIO04 GPIOFS00.[4]

GPIO05 PCIRST# GPIO05 GPIOFS00.[5]

GPIO06＊

GPIO07 i_clk_8051 GPIO07 GPIOFS00.[7]

GPIO08 i_clk_peri GPIO08 GPIOFS08.[0]

GPIO09＊

GPIO0A

GPIO0B ESB_CLK GPIO0B GPIOFS08.[3]

GPIO0C ESB_DAT ESB_DAT GPIO0C GPIOFS08.[4]

GPIO0D RLC_TX2 GPIO0D GPIOFS08.[5]

GPIO0E SCI# GPIO0E GPIOFS08.[6]

GPIO0F PWM0 GPIO0F GPIOFS08.[7]

GPIO10 PWM1 GPIO10 GPIOFS10.[0]

GPIO11 PWM2 GPIO11 GPIOFS10.[1]

GPIO12 FANPWM0 GPIO12 GPIOFS10.[2]

GPIO13 FANPWM1 GPIO13 GPIOFS10.[3]

GPIO14 FANFB0 GPIO14 GPIOFS10.[4]

GPIO15 FANFB1 GPIO15 GPIOFS10.[5]

GPIO16 E51TXD GPIO16 GPIOFS10.[6]

GPIO17 E51CLK E51RXD GPIO17 GPIOFS10.[7]

GPIO18 GPIO18 GPIOFS18.[0]

GPIO19 PWM3 GPIO19 GPIOFS18.[1]

GPIO1A NUMLED# GPIO1A GPIOFS18.[2]

GPIO1B＊

GPIO1C＊

GPIO02 GPIOFS00.[2]

GPIO03 GPIOFS00.[3]

GPIO06 GPIOFS00.[6]

GPIO09 GPIOFS08.[1]

RLC_RX2

OWM

GPIO1B GPIOFS18.[3]

GPIO1C GPIOFS18.[4]

/ OWM

GPIO0A GPIOFS08.[2]

OWMCFG[7]

25

GPIO Alt. Output Alt. Input Default Alt. Output Alt. Selection Reg.

GPIO1D CLKRUN# CLKRUN# GPIO1D GPIOFS18.[5]

GPIO1E＊

GPIO1F＊

GPIO20 KSO00 TP_TEST GPIO20 GPIOFS20.[0]

GPIO21 KSO01 TP_PLL GPIO21 GPIOFS20.[1]

GPIO22 KSO02 TP_TMUX GPIO22 GPIOFS20.[2]

GPIO23 KSO03 TP_ISP GPIO23 GPIOFS20.[3]

GPIO24 KSO04 GPIO24 GPIOFS20.[4]

GPIO25 KSO05 PCICLK (LPC) GPIO25 GPIOFS20.[5]

GPIO26 KSO06 PCIRST# (LPC) GPIO26 GPIOFS20.[6]

GPIO27 KSO07

GPIO28 KSO08 LFRAME# (LPC) GPIO28 GPIOFS28.[0]

GPIO29 KSO09 GPIO29 GPIOFS28.[1]

GPIO2A KSO10 GPIO2A GPIOFS28.[2]

GPIO2B KSO11

GPIO2C KSO12

GPIO2D KSO13

GPIO2E KSO14

GPIO2F KSO15 GPIO2F GPIOFS28.[7]

GPIO30 KSI0 GPIO30 GPIOFS30.[0]

GPIO31 KSI1 GPIO31 GPIOFS30.[1]

GPIO32 KSI2 GPIO32 GPIOFS30.[2]

GPIO33 KSI3 GPIO33 GPIOFS30.[3]

GPIO34 KSI4

GPIO35 KSI5

GPIO36 KSI6

GPIO37 EDI_DO KSI7 GPIO37 GPIOFS30.[7]

GPI38 AD0 GPI38 GPIOFS38.[0]

GPI39 AD1 GPI39 GPIOFS38.[1]

GPI3A AD2 GPI3A GPIOFS38.[2]

GPI3B AD3 GPI3B GPIOFS38.[3]

GPO3C DA0 GPO3C

GPO3D DA1 GPO3D

GPO3E DA2 GPO3E

GPIO1E GPIOFS18.[6]

GPIO1F GPIOFS18.[7]

SERIRQ (LPC)

LAD0 (LPC)

LAD1 (LPC)

LAD2 (LPC)

LAD3 (LPC)

SERIRQ (LPC)

LAD0 (LPC)

LAD1 (LPC)

LAD2 (LPC)

LAD3 (LPC)

/ EDI_CS

/ EDI_CLK

/ EDI_DIN

KB3930 Keyboard Controller Datasheet

GPIO_MISC2[7]

GPIO27 GPIOFS20.[7]

GPIO_MISC2[7]

GPIO2B GPIOFS28.[3]

GPIO_MISC2[7]

GPIO2C GPIOFS28.[4]

GPIO_MISC2[7]

GPIO2D GPIOFS28.[5]

GPIO_MISC2[7]

GPIO2E GPIOFS28.[6]

GPIO_MISC2[7]

GPIO34 GPIOFS30.[4]

GPIO35 GPIOFS30.[5]

GPIO36 GPIOFS30.[6]

GPIOFS38.[4] ★

GPIOFS38.[5] ★

GPIOFS38.[6] ★

26

GPIO Alt. Output Alt. Input Default Alt. Output Alt. Selection Reg.

GPO3F DA3 GPO3F

GPIO40 CIR_RX GPIO40 GPIOFS40.[0]

GPIO41 CIR_RLC_TX

/ PECI

GPI42 AD4 GPI42 GPIOFS40.[2]

GPI43 AD5 GPI43 GPIOFS40.[3]

GPIO44 SCL0 GPIO44 GPIOFS40.[4]

GPIO45 SDA0 GPIO45 GPIOFS40.[5]

GPIO46 SCL1 GPIO46 GPIOFS40.[6]

GPIO47 SDA1 GPIO47 GPIOFS40.[7]

GPIO48 KSO16 GPIO48 GPIOFS48.[0]

GPIO49 KSO17 GPIO49 GPIOFS48.[1]

GPIO4A PSCLK1 / SCL2 GPIO4A GPIOFS48.[2]

GPIO4B PSDAT1

/ SDA2

GPIO4C PSCLK2

/ SCL3

GPIO4D PSDAT2

/ SDA3

GPIO4E PSCLK3 GPIO4E GPIOFS48.[6]

GPIO4F PSDAT3 GPIO4F GPIOFS48.[7]

GPIO50 GPIO50 GPIOFS50.[0]

GPIO51＊

GPIO52 E51CS# GPIO52 GPIOFS50.[2]

GPIO53 CAPSLED# E51TMR1 GPIO53 GPIOFS50.[3]

GPIO54 WDT_LED# E51TMR0 GPIO54 GPIOFS50.[4]

GPIO55 SCORLED# E51INT0 GPIO55 GPIOFS50.[5]

GPIO56 E51INT1 GPIO56 GPIOFS50.[6]

GPIO57 XCLK32K GPIO57 GPIOFS50.[7]

GPIO58 SPICLK GPIO58 GPIOFS58.[0]

GPIO59 TEST_CLK/SPICLK GPIO59 GPIOFS58.[1]

GPXIOA00 SDICS# GPIO_MISC.[2]

GPXIOA01 SDICLK GPIO_MISC.[2]

GPXIOA02 SDIMOSI GPIO_MISC.[2]

GPXIOA03 FANFB2 FANTMCFG0[0]

GPXIOA04 FANFB3 FANTMCFG1[0]

GPXIOA05

GPXIOA06 VOUT GPX_MISC[0]

GPXIOA07

GPXIOA08

GPXIOA09

GPXIOA10

GPXIOA11

GPIO51 GPIOFS50.[1]

PECI

GPIO4B GPIOFS48.[3]

GPIO4C GPIOFS48.[4]

GPIO4D GPIOFS48.[5]

KB3930 Keyboard Controller Datasheet

GPIOFS38.[7] ★

GPIO41 GPIOFS40.[1]

GPIO_MISC2[0]

GPIO_MISC2[4]

GPIO_MISC2[5]

27

GPIO Alt. Output Alt. Input Default Alt. Output Alt. Selection Reg.

GPXIOD00 SDIMISO / VCIN0 VCCSR[0]

GPXIOD01

GPXIOD02

GPXIOD03 VCIN1 VCCSR[1]

GPXIOD04

GPXIOD05

GPXIOD06

GPXIOD07

＊ In KBx930, these GPIO pins no more exist. The corresponding register bits do not work.

★ If DAC function selected, please do not

KB3930 Keyboard Controller Datasheet

set this register bit.

4.2.2 GPIO Structures

In this section, the GPIO structure is illustrated as following diagram. The upper part is

alternative output circuit and the lower part is alternative input circuit. In the figure, GPIOFS is used

to enable alternative output. GPIOOD is for open-drain setting with output function. GPIOOE is the

switch for data output. As shown in the figure, the alternative input embedded with pull-high and

interrupt feature.

28

KB3930 Keyboard Controller Datasheet

4.2.3 GPIO Attribution Table

GPIO Alt.

Output

GPIO00 GA20 GPIO00 GPIOFS00.[0] V V V V 2-4mA

GPIO01 KBRST# GPIO01 GPIOFS00.[1] V V V V 2-4mA

GPIO02＊

GPIO03＊

GPIO04 GPIO04 GPIOFS00.[4] V V V V 2-4mA

GPIO05 PCIRST# GPIO05 GPIOFS00.[5] V V V 8-16mA

GPIO06＊

GPIO07 i_clk_805) GPIO07 GPIOFS00.[7] V V V V 2-4mA

GPIO08 i_clk_peri GPIO08 GPIOFS08.[0] V V V V 2-4mA

GPIO09＊

GPIO0A

GPIO0B ESB_CLK GPIO0B GPIOFS08.[3] V V V V 8-16mA

GPIO0C ESB_DAT ESB_DAT GPIO0C GPIOFS08.[4] V V V V 4~8mA

GPIO0D RLC_TX2 GPIO0D GPIOFS08.[5] V V V V 2-4mA

GPIO0E SCI# GPIO0E GPIOFS08.[6] V V V V 2-4mA

GPIO0F PWM0 GPIO0F GPIOFS08.[7] V V V V 8-16mA

GPIO10 PWM1 GPIO10 GPIOFS10.[0] V V V V 2-4mA

GPIO11 PWM2 GPIO11 GPIOFS10.[1] V V V V 2-4mA

GPIO12 FANPWM0 GPIO12 GPIOFS10.[2] V V V V 2-4mA

GPIO13 FANPWM1 GPIO13 GPIOFS10.[3] V V V V 2-4mA

GPIO14 FANFB0 GPIO14 GPIOFS10.[4] V V V V 2-4mA

GPIO15 FANFB1 GPIO15 GPIOFS10.[5] V V V V 2-4mA

GPIO16 E51TXD GPIO16 GPIOFS10.[6] V V V V 2-4mA

GPIO17 E51CLK E51RXD GPIO17 GPIOFS10.[7] V V V V 2-4mA

GPIO18 GPIO18 GPIOFS18.[0] V V V V 2-4mA

GPIO19 PWM3 GPIO19 GPIOFS18.[1] V V V 8-16mA

GPIO1A NUMLED# GPIO1A GPIOFS18.[2] V V V 8-16mA

GPIO1B＊

GPIO1C＊

GPIO1D CLKRUN# CLKRUN# GPIO1D GPIOFS18.[5] V V V 8-16mA

GPIO1E＊

GPIO1F＊

GPIO20 KSO00 TP_TEST GPIO20 GPIOFS20.[0] V V V V 2-4mA

GPIO21 KSO01 TP_PLL GPIO21 GPIOFS20.[1] V V V V 2-4mA

GPIO22 KSO02 TP_TMUX GPIO22 GPIOFS20.[2] V V V V 2-4mA

GPIO23 KSO03 TP_ISP GPIO23 GPIOFS20.[3] V V V V 2-4mA

GPIO24 KSO04 GPIO24 GPIOFS20.[4] V V V V 2-4mA

GPIO25 KSO05 PCICLK(LPC) GPIO25 GPIOFS20.[5]

GPIO26 KSO06 PCIRST#(LPC) GPIO26 GPIOFS20.[6]

GPIO27 KSO07 /

GPIO28 KSO08 LFRAME#(LPC) GPIO28 GPIOFS28.[0]

GPIO29 KSO09 GPIO29 GPIOFS28.[1] V V V V 8-16mA

GPIO2A KSO10 GPIO2A GPIOFS28.[2] V V V V 8-16mA

GPIO02 GPIOFS00.[2]

GPIO03 GPIOFS00.[3]

GPIO06 GPIOFS00.[6]

GPIO09 GPIOFS08.[1]

OWM

GPIO1B GPIOFS18.[3]

GPIO1C GPIOFS18.[4]

GPIO1E GPIOFS18.[6]

GPIO1F GPIOFS18.[7]

SERIRQ(LPC) SERIRQ(LPC)

Alt.

Input

RLC_RX2

OWM

Default

Alt. Output

GPIO0A GPIOFS08.[2]

GPIO27 GPIOFS20.[7]

Alt. Selection

Reg.

OWMCFG[7]

GPIO_MISC2[7]

Input

Enable

Output

Enable

V V V V 2-4mA

V V V V 8-16mA

V V V V 2-4mA

Pull Up

(40KΩ)

Open

Drain

Output

Current

29

GPIO Alt.

Output

GPIO2B KSO11 /

GPIO2C KSO12 /

GPIO2D KSO13 /

GPIO2E KSO14 /

GPIO2F KSO15 GPIO2F GPIOFS28.[7] V V V V 2-4mA

GPIO30 KSI0 GPIO30 GPIOFS30.[0] V V V V 2-4mA

GPIO31 KSI1 GPIO31 GPIOFS30.[1] V V V V 2-4mA

GPIO32 KSI2 GPIO32 GPIOFS30.[2] V V V V 2-4mA

GPIO33 KSI3 GPIO33 GPIOFS30.[3] V V V V 2-4mA

GPIO34 KSI4 /

GPIO35 KSI5 /

GPIO36 KSI6 /

GPIO37 EDI_DO KSI7 GPIO37 GPIOFS30.[7] V V V V 2-4mA

GPI38 AD0 GPIOFS38.[0] V

GPI39 AD1 GPIOFS38.[1] V

GPI3A AD2 GPIOFS38.[2] V

GPI3B AD3 GPIOFS38.[3] V

GPO3C DA0 GPO3C GPIOFS38.[4] V 2-4mA

GPO3D DA1 GPO3D GPIOFS38.[5] V 2-4mA

GPO3E DA2 GPO3E GPIOFS38.[6] V 2-4mA

GPO3F DA3 GPO3F GPIOFS38.[7] V 2-4mA

GPIO40 CIR_RX GPIO40 GPIOFS40.[0] V V V 2-4mA

GPIO41 CIR_RLC_TX /

GPI42 AD4 GPIOFS40.[2] V 2-4mA

GPI43 AD5 GPIOFS40.[3] V 2-4mA

GPIO44 SCL0 GPIO44 GPIOFS40.[4] V V V 2-4mA

GPIO45 SDA0 GPIO45 GPIOFS40.[5] V V V 2-4mA

GPIO46 SCL1 GPIO46 GPIOFS40.[6] V V V 2-4mA

GPIO47 SDA1 GPIO47 GPIOFS40.[7] V V V 2-4mA

GPIO48 KSO16 / GPIO48 GPIOFS48.[0] V V V V 2-4mA

GPIO49 KSO17 GPIO49 GPIOFS48.[1] V V V V 2-4mA

GPIO4A PSCLK1

GPIO4B PSDAT1

GPIO4C PSCLK2

GPIO4D PSDAT2

GPIO4E PSCLK3 GPIO4E GPIOFS48.[6] V V V 2-4mA

GPIO4F PSDAT3 GPIO4F GPIOFS48.[7] V V V 2-4mA

GPIO50 GPIO50 GPIOFS50.[0] V V V 2-4mA

GPIO51＊

GPIO52 E51CS# GPIO52 GPIOFS50.[2] V V V 8-16mA

LAD0(LPC)

LAD1(LPC)

LAD2(LPC)

LAD3(LPC)

PECI

/ SCL2

/ SDA2

/ SCL3

/ SDA3

GPIO51 GPIOFS50.[1]

Alt.

Input

LAD0(LPC)

LAD1(LPC)

LAD2(LPC)

LAD3(LPC)

EDI_CS

EDI_CLK

EDI_DIN

PECI

GPIO4A GPIOFS48.[2]

GPIO4B GPIOFS48.[3]

GPIO4C GPIOFS48.[4]

GPIO4D GPIOFS48.[5]

Default

Alt. Output

GPIO2B GPIOFS28.[3]

GPIO2C GPIOFS28.[4]

GPIO2D GPIOFS28.[5]

GPIO2E GPIOFS28.[6]

GPIO34 GPIOFS30.[4] V V V V 2-4mA

GPIO35 GPIOFS30.[5] V V V V 2-4mA

GPIO36 GPIOFS30.[6] V V V V 2-4mA

GPIO41 GPIOFS40.[1]

Alt. Selection

Reg.

GPIO_MISC2[7]

GPIO_MISC2[0]

GPIO_MISC2[4]

GPIO_MISC2[5]

KB3930 Keyboard Controller Datasheet

Input

Enable

Output

Enable

V V V V 2-4mA

V V V 2-4mA

V V V 8-16mA

Pull Up

(40KΩ)

Open

Drain

Output

Current

30

GPIO Alt.

Output

GPIO53 CAPSLED# E51TMR1 GPIO53 GPIOFS50.[3] V V V 8-16mA

GPIO54 WDT_LED# E51TMR0 GPIO54 GPIOFS50.[4] V V V 8-16mA

GPIO55 SCORLED# E51INT0 GPIO55 GPIOFS50.[5] V V V 8-16mA

GPIO56 E51INT1 GPIO56 GPIOFS50.[6] V V V V 2-4mA

GPIO57 XCLK32K GPIO57 GPIOFS50.[7] V V V V 2-4mA

GPIO58 SPICLK GPIO58 GPIOFS58.[0] V V V V 8-16mA

GPIO59 TEST_CLK/

GPXIOA00 SDICS# GPIO_MISC.[2] V V V 2-4mA

GPXIOA01 SDICLK GPIO_MISC.[2] V V V 2-4mA

GPXIOA02 SDIMOSI GPIO_MISC.[2] V V V 2-4mA

GPXIOA03 FANFB2 FANTMCFG0[0] V V V 2-4mA

GPXIOA04 FANFB3 FANTMCFG1[0] V V V 2-4mA

GPXIOA05 VCOUT GPX_MISC[0] V V V 2-4mA

GPXIOA06 V V V 2-4mA

GPXIOA07 V V V 2-4mA

GPXIOA08 V V V 8-16mA

GPXIOA09 V V V 8-16mA

GPXIOA10 V V V 8-16mA

GPXIOA11 V V V 8-16mA

GPXIOD00 SDIMISO

GPXIOD01 V V V 2-4mA

GPXIOD02 V V V 2-4mA

GPXIOD03 / VCIN1 VCCSR[1] V V V 2-4mA

GPXIOD04 V V V 2-4mA

GPXIOD05 V V V 2-4mA

GPXIOD06 V V V 2-4mA

GPXIOD07 V V V 2-4mA

Alt.

Input

SPICLK

/ VCIN0

Default

Alt. Output

GPIO59 GPIOFS58.[1] V V V V 2-4mA

Alt. Selection

Reg.

VCCSR[0] V V V 2-4mA

KB3930 Keyboard Controller Datasheet

Input

Enable

Output

Enable

Pull Up

(40KΩ)

Open

Drain

Output

Current

＊ Denotes that these pins do not exist in KBx930

31

KB3930 Keyboard Controller Datasheet

4.2.3 GPIO Registers Descriptions

Function Selection Register

Offset Name Type. Description Default Bank

0x00 GPIOFS00 R/W GPIO00~GPIO07 Function Selection

bit[0]~bit[7] stand for GPIO00~GPIO07 separately

0: General purpose output function selected

1: Alternative output function selected.

0x01 GPIOFS08 R/W GPIO08~GPIO0F Function Selection

bit[0]~bit[7] stand for GPIO08~GPIO0F separately

0: General purpose output function selected

1: Alternative output function selected.

0x02 GPIOFS10 R/W GPIO10~GPIO17 Function Selection

bit[0]~bit[7] stand for GPIO10~GPIO17 separately

0: General purpose output function selected

1: Alternative output function selected.

0x03 GPIOFS18 R/W GPIO18~GPIO1F Function Selection

bit[0]~bit[7] stand for GPIO18~GPIO1F separately

0: General purpose output function selected

1: Alternative output function selected.

0x04 GPIOFS20 R/W GPIO20~GPIO27 Function Selection

bit[0]~bit[7] stand for GPIO20~GPIO27 separately

0: General purpose output function selected

1: Alternative output function selected.

0x05 GPIOFS28 R/W GPIO28~GPIO2F Function Selection

bit[0]~bit[7] stand for GPIO28~GPIO2F separately

0: General purpose output function selected

1: Alternative output function selected.

0x06 GPIOFS30 R/W GPIO30~GPIO37 Function Selection

bit[0]~bit[7] stand for GPIO30~GPIO37 separately

0: General purpose output function selected

1: Alternative output function selected.

0x07 GPIOFS38 R/W GPIO3C~GPIO3F Function Selection

bit[4]~bit[7] stand for GPIO3C~GPIO3F separately

0: General purpose output function selected 1: Alternative output function selected.

＊

GPI38~GPI3Bwithoutalternativeoutputfunction.

0x08 GPIOFS40 R/W GPIO40~41, 44~47 Function Selection

bit[0:1], bit[4:7] stand for GPIO40~41, 44~47 separately

0: General purpose output function selected

1: Alternative output function selected.

＊

GPI42~GPI43withoutalternativeoutputfunction.

0x09 GPIOFS48 R/W GPIO48~GPIO4F Function Selection

bit[0]~bit[7] stand for GPIO48~GPIO4F separately

0: General purpose output function selected

1: Alternative output function selected.

0x0A GPIOFS50 R/W GPIO50~GPIO57 Function Selection

bit[0]~bit[7] stand for GPIO50~GPIO57 separately

0: General purpose output function selected

1: Alternative output function selected.

0x0B GPIOFS58 R/W GPIO58~GPIO59 Function Selection

bit[0]~bit[1] stand for GPIO58~GPIO59 separately

0: General purpose output function selected

1: Alternative output function selected.

0x00 0xFC

0x02 0xFC

0x00 0xFC

32

KB3930 Keyboard Controller Datasheet

Output Enable Register

Offset Name Type. Description Default Bank

0x10 GPIOOE00 R/W

0x11 GPIOOE08 R/W

0x12 GPIOOE10 R/W

0x13 GPIOOE18 R/W

0x14 GPIOOE20 R/W

0x15 GPIOOE28 R/W

0x16 GPIOOE30 R/W

0x17 GPIOOE38 R/W

0x18 GPIOOE40 R/W

0x19 GPIOOE48 R/W

0x1A GPIOOE50 R/W

0x1B GPIOOE58 R/W

0x1C GPXAOE00 R/W

GPIO00~GPIO07 Output Enable bit[0]~bit[7] stand for GPIO00~GPIO07 separately

0: Output Disable 1: Output Enable

GPIO08~GPIO0F Output Enable bit[0]~bit[7] stand for GPIO08~GPIO0F separately

0: Output Disable 1: Output Enable

GPIO10~GPIO17 Output Enable bit[0]~bit[7] stand for GPIO10~GPIO17 separately

0: Output Disable 1: Output Enable

GPIO18~GPIO1F Output Enable bit[0]~bit[7] stand for GPIO18~GPIO1F separately

0: Output Disable 1: Output Enable

GPIO20~GPIO27 Output Enable bit[0]~bit[7] stand for GPIO20~GPIO27 separately

0: Output Disable 1: Output Enable

GPIO28~GPIO2F Output Enable bit[0]~bit[7] stand for GPIO28~GPIO2F separately

0: Output Disable 1: Output Enable

GPIO30~GPIO37 Output Enable bit[0]~bit[7] stand for GPIO30~GPIO37 separately

0: Output Disable 1: Output Enable

GPIO3C~GPIO3F Output Enable bit[4]~bit[7] stand for GPIO3C~GPIO3F separately

0: Output Disable 1: Output Enable

* GPI38~GPI3A without output enable feature.

GPIO40~41 , 44~47 Output Enable bit[0:1], bit[4:7] stand for GPIO40~1, 44~47 separately

0: Output Disable 1: Output Enable

＊

GPI42~GPI43 without output enable.

GPIO48~GPIO4F Output Enable bit[0]~bit[7] stand for GPIO48~GPIO4F separately

0: Output Disable 1: Output Enable

GPIO50~GPIO57 Output Enable bit[0]~bit[7] stand for GPIO50~GPIO57 separately

0: Output Disable 1: Output Enable

GPIO58~GPIO59 Output Enable bit[0]~bit[1] stand for GPIO58~GPIO59 separately

0: Output Disable 1: Output Enable

GPXIOA00~GPXIOA07 Output Enable bit[0]~bit[7] stand for GPXIOA00~GPXIOA07 separately

0: Output Disable 1: Output Enable

0x00 0xFC

0x02 0xFC

0x00 0xFC

33

KB3930 Keyboard Controller Datasheet

Output Enable Register (Continued)

Offset Name Type. Description Default Bank

0x1D GPXAOE08 R/W

0x1E RSV RSV

0x1F GPXDOE00 R/W

GPXIOA08~GPXIOA11 Output Enable bit[0]~bit[3] stand for GPXIOA08~GPXIOA11 separately

0: Output Disable 1: Output Enable

Reserved

GPXIOD00~GPXIOD07 Output Enable bit[0]~bit[7] stand for GPXIOD00~GPXIOD07 separately

0: Output Disable 1: Output Enable

0x00 0xFC

RSV 0xFC

0x00 0xFC

Output Data Port Register

Offset Name Type. Description Default Bank

0x20 GPIOD00 R/W

0x21 GPIOD08 R/W

0x22 GPIOD10 R/W

0x23 GPIOD18 R/W

0x24 GPIOD20 R/W

0x25 GPIOD28 R/W

0x26 GPIOD30 R/W

0x27 GPIOD38 R/W

0x28 GPIOD40 R/W

0x29 GPIOD48 R/W

0x2A GPIOD50 R/W

0x2B GPIOD58 R/W

0x2C GPXAD00 R/W

0x2D GPXAD08 R/W

0x2E RSV RSV

0x2F GPXDD00 R/W

GPIO00~GPIO07 Output Data Port for output function. Bit[0]~bit[7] stand for GPIO00~GPIO07 separately

GPIO08~GPIO0F Output Data Port for output function. Bit[0]~bit[7] stand for GPIO08~GPIO0F separately

GPIO10~GPIO17 Output Data Port for output function. Bit[0]~bit[7] stand for GPIO10~GPIO17 separately

GPIO18~GPIO1F Output Data Port for output function. Bit[0]~bit[7] stand for GPIO18~GPIO1F separately

GPIO20~GPIO27 Output Data Port for output function. Bit[0]~bit[7] stand for GPIO20~GPIO27 separately

GPIO28~GPIO2F Output Data Port for output function. Bit[0]~bit[7] stand for GPIO28~GPIO2F separately

GPIO30~GPIO37 Output Data Port for output function. Bit[0]~bit[7] stand for GPIO30~GPIO37 separately

GPIO3C~GPIO3F Output Data Port for output function. Bit[4]~bit[7] stand for GPIO3C~GPIO3F separately

* GPI38~GPI3B have no output data ports.

GPIO40~41, 44~47 Output Data Port for output function. Bit[0:1],bit[4:7] stand for GPIO40~41, 44~47 separately

* GPI42~GPI43 have no output data ports.

GPIO48~GPIO4F Output Data Port for output function. Bit[0]~bit[7] stand for GPIO48~GPIO4F separately

GPIO50~GPIO57 Output Data Port for output function. Bit[0]~bit[7] stand for GPIO50~GPIO57 separately

GPIO58~GPIO59 Output Data Port for output function. Bit[0]~bit[1] stand for GPIO58~GPIO59 separately

GPXIOA00~GPXIOA07 Output Data Port for output function. Bit[0]~bit[7] stand for GPXIOA00~GPXIOA07 separately

GPXIOA08~GPXIOA11 Output Data Port for output function. Bit[0]~bit[3] stand for GPXIOA08~GPXIOA11 separately

Reserved

GPXIOD00~GPXIOD07 Output Data Port for output function. Bit[0]~bit[7] stand for GPXIOD00~GPXIOD07 separately

0x00 0xFC

RSV 0xFC

0x00 0xFC

34

KB3930 Keyboard Controller Datasheet

Input Data Port Register

Offset Name Type. Description Default Bank

0x30 GPIOIN00 R

0x31 GPIOIN08 R

0x32 GPIOIN10 R

0x33 GPIOIN18 R

0x34 GPIOIN20 R

0x35 GPIOIN28 R

0x36 GPIOIN30 R

0x37 GPIOIN38 R

0x38 GPIOIN40 R

0x39 GPIOIN48 R

0x3A GPIOIN50 R

0x3B GPIOIN58 R

0x3C GPXAIN00 R

0x3D GPXAIN08 R

0x3E RSV RSV

0x3F GPXDIN00 R

GPIO00~GPIO07 Input Data Port for input function. Bit[0]~bit[7] stand for GPIO00~GPIO07 separately

GPIO08~GPIO0F Input Data Port for input function. Bit[0]~bit[7] stand for GPIO08~GPIO0F separately

GPIO10~GPIO17 Input Data Port for input function. Bit[0]~bit[7] stand for GPIO10~GPIO17 separately

GPIO18~GPIO1F Input Data Port for input function. Bit[0]~bit[7] stand for GPIO18~GPIO1F separately

GPIO20~GPIO27 Input Data Port for input function. Bit[0]~bit[7] stand for GPIO20~GPIO27 separately

GPIO28~GPIO2F Input Data Port for input function. Bit[0]~bit[7] stand for GPIO28~GPIO2F separately

GPIO30~GPIO37 Input Data Port for input function. Bit[0]~bit[7] stand for GPIO30~GPIO37 separately

GPIO38~GPIO3B Input Data Port for input function. Bit[0]~bit[3] stand for GPIO38~GPIO3B separately

* GPO3C~GPO3F have no input data ports.

GPIO40~GPIO47 Input Data Port for input function. Bit[0]~bit[7] stand for GPIO40~GPIO47 separately

GPIO48~GPIO4F Input Data Port for input function. Bit[0]~bit[7] stand for GPIO48~GPIO4F separately

GPIO50~GPIO57 Input Data Port for input function. Bit[0]~bit[7] stand for GPIO50~GPIO57 separately

GPIO58~GPIO59 Input Data Port for input function. Bit[0]~bit[1] stand for GPIO58~GPIO59 separately

GPXIOA00~GPXIOA07 Input Data Port for input function. Bit[0]~bit[7] stand for GPXIOA00~GPXIOA07 separately

GPXIOA08~GPXIOA11 Input Data Port for input function. Bit[0]~bit[3] stand for GPXIOA08~GPXIOA11 separately

Reserved

GPXIOD00~GPXIOD07 Input Data Port for input function. Bit[0]~bit[7] stand for GPXIOD00~GPXIOD07 separately

0xFF 0xFC

0x0F 0xFC

0xFF 0xFC

0x01 0xFC

0xFF 0xFC

RSV 0xFC

0xFF 0xFC

35

KB3930 Keyboard Controller Datasheet

Pull-up Enable Register

Offset Name Type. Description Default Bank

0x40 GPIOPU00 R/W

0x41 GPIOPU08 R/W

0x42 GPIOPU10 R/W

0x43 GPIOPU18 R/W

0x44 GPIOPU20 R/W

0x45 GPIOPU28 R/W

0x46 GPIOPU30 R/W

0x47 RSV RSV

0x48 GPIOPU40 R/W

0x49 GPIOPU48 R/W

0x4A GPIOPU50 R/W

0x4B GPIOPU58 R/W

GPIO00~04, 06~07 Internal Pull-Up Resistor Enable for input function

bit[0:4],bit[6:7] stand for GPIO00~04, 06~07 separately

0: Pull-Up resistor disable 1: Pull-Up resistor enable

* GPIO05 (bit 5)do not exist internal pull-up resistor

GPIO08~GPIO0F Internal Pull-Up Resistor Enable for input function

bit[0]~bit[7] stand for GPIO08~GPIO0F separately

0: Pull-Up resistor disable 1: Pull-Up resistor enable

The ESB_CLK Pull-Up is changed to default off.

GPIO10~GPIO17 Internal Pull-Up Resistor Enable for input function

bit[0]~bit[7] stand for GPIO10~GPIO17 separately

0: Pull-Up resistor disable 1: Pull-Up resistor enable

GPIO18, 1B~1C, 1E~1F Internal Pull-Up Resistor Enable for input function

bit[0], bit[3:4], bit[6:7] stand for GPIO18, 1B~1C, 1E~1F separately

0: Pull-Up resistor disable 1: Pull-Up resistor enable.

* GPIO19/1A/1D (bit 1/2/5)do not exist internal pull-up resistor

GPIO20~GPIO27 Internal Pull-Up Resistor Enable for input function

bit[0]~bit[7] stand for GPIO20~GPIO27 separately

0: Pull-Up resistor disable 1: Pull-Up resistor enable

GPIO28~GPIO2F Internal Pull-Up Resistor Enable for input function

bit[0]~bit[7] stand for GPIO28~GPIO2F separately

0: Pull-Up resistor disable 1: Pull-Up resistor enable

GPIO30~GPIO37 Internal Pull-Up Resistor Enable for input function

bit[0]~bit[7] stand for GPIO30~GPIO37 separately

0: Pull-Up resistor disable 1: Pull-Up resistor enable

Reserved

GPIO41 Internal Pull-Up Resistor Enable for input function bit[1] stand for GPIO41

0: Pull-Up resistor disable 1: Pull-Up resistor enable

GPIO48~GPIO49 Internal Pull-Up Resistor Enable for input function

bit[0]~bit[1] stand for GPIO48~GPIO49 separately

0: Pull-Up resistor disable 1: Pull-Up resistor enable.

GPIO56/57 Internal Pull-Up Resistor Enable for input function bit[6]~bit[7] stand for GPIO56~57 separately

0: Pull-Up resistor disable 1: Pull-Up resistor enable.

GPIO58~GPIO59 Internal Pull-Up Resistor Enable for input function

bit[0]~bit[1] stand for GPIO58~GPIO59 separately

0: Pull-Up resistor disable 1: Pull-Up resistor enable.

0x00 0xFC

0x0F 0xFC

0x00 0xFC

0xFF 0xFC

0xFC

0x00 0xFC

36

KB3930 Keyboard Controller Datasheet

Pull-up Enable Register (Continued)

Offset Name Type. Description Default Bank

0x4C GPXAPU00 R/W

0x4D GPXAPU08 R/W

0x4E RSV RSV

0x4F GPXDPU00 R/W

GPXIOA00~ GPXIOA07 Internal Pull-Up Resistor Enable for input function

bit[0]~bit[7] stand for GPXIO00~ GPXIO07 separately

0: Pull-Up resistor disable 1: Pull-Up resistor enable

GPXIOA08~ GPXIOA11 Internal Pull-Up Resistor Enable for input function

bit[0]~bit[3] stand for GPXIOA08~ GPXIOA11 separately

0: Pull-Up resistor disable 1: Pull-Up resistor enable

Reserved

GPXIOD00~ GPXIOD07 Internal Pull-Up Resistor Enable for input function

bit[0]~bit[1] stand for GPXIOD00~ GPXIOD07 separately

0: Pull-Up resistor disable 1: Pull-Up resistor enable

0x00 0xFC

RSV 0xFC

0x00 0xFC

37

KB3930 Keyboard Controller Datasheet

Open Drain Enable Register

Offset Name Type. Description Default Bank

0x50 GPIOOD00 R/W0C

0x51 GPIOOD08 R/W0C

0x52 GPIOOD10 R/W0C

0x53 GPIOOD18 R/W0C

0x54 GPIOOD20 R/W0C

0x55 GPIOOD28 R/W0C

0x56 GPIOOD30 R/W0C

0x57 RSV RSV

0x58 GPIOOD40 R/W0C

0x59 GPIOOD48 R/W0C

0x5A GPIOOD50 R/W0C

0x5B GPIOOD58 R/W0C

GPIO00~GPIO07 Open Drain Enable for output function bit[0]~bit[7] stand for GPIO00~GPIO07 separately

0: Open drain disable 1: Open drain enable.

GPIO08~GPIO0F Open Drain Enable for output function bit[0]~bit[7] stand for GPIO08~GPIO0F separately

0: Open drain disable 1: Open drain enable.

GPIO10~GPIO17 Open Drain Enable for output function bit[0]~bit[7] stand for GPIO10~GPIO17 separately

0: Open drain disable 1: Open drain enable.

GPIO18~GPIO1F Open Drain Enable for output function bit[0]~bit[7] stand for GPIO18~GPIO1F separately

0: Open drain disable 1: Open drain enable.

GPIO20~GPIO27 Open Drain Enable for output function bit[0]~bit[7] stand for GPIO20~GPIO27 separately

0: Open drain disable 1: Open drain enable.

GPIO28~GPIO2F Open Drain Enable for output function bit[0]~bit[7] stand for GPIO28~GPIO2F separately

0: Open drain disable 1: Open drain enable.

GPIO30~GPIO37 Open Drain Enable for output function bit[0]~bit[7] stand for GPIO30~GPIO37 separately

0: Open drain disable 1: Open drain enable.

RSV

GPIO40~41, 44~47 Open Drain Enable for output function bit[0:1], bit[4:7] stand for GPIO40~41, 44~47 separately

0: Open drain disable 1: Open drain enable.

* GPI42/43 do not exist open drain function

GPIO48~GPIO4F Open Drain Enable for output function bit[0]~bit[7] stand for GPIO48~GPIO4F separately

0: Open drain disable 1: Open drain enable.

GPIO50~GPIO57 Open Drain Enable for output function bit[0]~bit[7] stand for GPIO50~GPIO57 separately

0: Open drain disable 1: Open drain enable.

GPIO58~GPIO59 Open Drain Enable for output function bit[0]~bit[1] stand for GPIO58~GPIO59 separately

0: Open drain disable 1: Open drain enable.

0x00 0xFC

0xFC

0x00 0xFC

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KB3930 Keyboard Controller Datasheet

Input Enable Register

Offset Name Type. Description Default Bank

0x60 GPIOIE00 R/W

0x61 GPIOIE08 R/W

0x62 GPIOIE10 R/W

0x63 GPIOIE18 R/W

0x64 GPIOIE20 R/W

0x65 GPIOIE28 R/W

0x66 GPIOIE30 R/W

0x67 GPIOIE38 R/W

0x68 GPIOIE40 R/W

0x69 GPIOIE48 R/W

0x6A GPIOIE50 R/W

0x6B GPIOEE58 R/W

GPIO00~GPIO07 Input Enable for input function bit[0]~bit[7] stand for GPIO00~GPIO07 separately

0: GPIO input mode disable 1: GPIO input mode enable.

GPIO08~GPIOF Input Enable for input function bit[0]~bit[7] stand for GPIO08~GPIO0F separately

0: GPIO input mode disable 1: GPIO input mode enable.

GPIO10~GPIO17 Input Enable for input function bit[0]~bit[7] stand for GPIO10~GPIO17 separately

0: GPIO input mode disable 1: GPIO input mode enable.

GPIO18~GPIO1F Input Enable for input function bit[0]~bit[7] stand for GPIO18~GPIO1F separately

0: GPIO input mode disable 1: GPIO input mode enable.

GPIO20~GPIO27 Input Enable for input function bit[0]~bit[7] stand for GPIO20~GPIO27 separately

0: GPIO input mode disable 1: GPIO input mode enable.

GPIO28~GPIO2F Input Enable for input function bit[0]~bit[7] stand for GPIO28~GPIO2F separately

0: GPIO input mode disable 1: GPIO input mode enable.

GPIO30~GPIO37 Input Enable for input function bit[0]~bit[7] stand for GPIO30~GPIO37 separately

0: GPIO input mode disable 1: GPIO input mode enable.

GPIO38~GPIO3B Input Enable for input function bit[0]~bit[3] stand for GPIO38~GPIO3B separately

0: GPIO input mode disable 1: GPIO input mode enable.

* GPO3C~GPO3F have no input functions.

GPIO40~GPIO47 Input Enable for input function bit[0]~bit[7] stand for GPIO40~GPIO47 separately

0: GPIO input mode disable 1: GPIO input mode enable.

GPIO48~GPIO4F Input Enable for input function bit[0]~bit[7] stand for GPIO48~GPIO4F separately

0: GPIO input mode disable 1: GPIO input mode enable.

GPIO50~GPIO57 Input Enable for input function bit[0]~bit[7] stand for GPIO50~GPIO57 separately

0: GPIO input mode disable 1: GPIO input mode enable.

GPIO58~GPIO59 Input Enable for input function bit[0]~bit[1] stand for GPIO58~GPIO59 separately

0: GPIO input mode disable 1: GPIO input mode enable.

0x20 0xFC

0x00 0xFC

0x0F 0xFC

0x00 0xFC

0xFF 0xFC

0x00 0xFC

0x03 0xFC

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KB3930 Keyboard Controller Datasheet

Input Enable Register (Continued)

Offset Name Type. Description Default Bank

0x6C GPXAIE00 R/W

0x6D GPXAIE08 R/W

0x6E RSV RSV

0x6F GPXDIE00 R/W

GPXIOA00~GPXIOA07 Input Enable for input function bit[0]~bit[7] stand for GPXIOA00~GPXIOA07 separately

0: GPIO input mode disable 1: GPIO input mode enable.

GPXIOA08~GPXIOA11 Input Enable for input function bit[0]~bit[3] stand for GPXIOA08~GPXIOA11 separately

0: GPIO input mode disable 1: GPIO input mode enable.

Reserved

GPXIOD00~GPXIOD07 Input Enable for input function bit[0]~bit[7] stand for GPXIOD00~GPXIOD07 separately

0: GPIO input mode disable 1: GPIO input mode enable.

0x00 0xFC

RSV 0xFC

0x00 0xFC

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KB3930 Keyboard Controller Datasheet

GPIO_MISC Control Register

Offset Name Bit Type Description Default Bank

0x70 GPIO_MISC 7

R/W ESB_DAT(GPIO0C) output current selection

0: 4mA 1: 8mA

R/W SPICLK(GPIO58) output current selection

6

0: 8mA 1: 16mA

R/W ESB_CLK(GPIO0B) output current selection

5

0: 8mA 1: 16mA

R/W RSV

4

R/W GPIO17 / GPIO18 are featured with signal bypass function.

3

R/W Alternative functions select for GPXIOA00~GPXIOA02.

2

RSV Reserved

1

R/W Beep glue logic switch.

0

Signal input via GPIO17 can be directly passed through GPIO18.

0: Pass through function disable 1: Pass through function enable

0: GPXIOA00~GPXIOA02 remain default output function 1: GPXIOA00~GPXIOA02 become SDICS#, SDICLK, and

SDIMOSI functions.

GPIO12 can be output a specific function as following formula.

GPIO12 = PWM2 ♁GPIO16(input) ♁GPIO17(input)

0: Beep glue logic function disable 1: Beep glue logic function enable

0x60 0xFC

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KB3930 Keyboard Controller Datasheet

GPIO_MISC 2 Control Register

Offset Name Bit Type Description Default Bank

0x71 GPIO_MISC2 7

6

5

4

3

2

1

0

R/W LPC bus redirection enable, will redirect LPC bus to relative

R/W Select GPIO25(KSO5) output current 4mA/16mA

R/W Enable SMBus port 3 (SCL3/SDA3)

R/W Enable SMBus port 2 (SCL2/SDA2)

RSV Reserved

R/W PECI function enable to GPIO41

KSO pins: 0: Disable 1: Enable PCICLK to GPIO25(KSO5) PCIRST# to GPIO26(KSO6) SERIRQ to GPIO27(KSO7) LFRAME# to GPIO28(KSO8) LAD3 to GPIO2B(KSO11) LAD2 to GPIO2C(KSO12) LAD1 to GPIO2D(KSO13) LAD0 to GPIO2E(KSO14)

=0, Select Output Current 4mA for GPIO25(KSO5) =1, Select Output Current 16mA for GPIO25(KSO5)

0:Disable 1:Enable

0x00 0xFC

GPIO Test Mux Register

Offset Name Bit Type Description Default Bank

0x72 GPIO_TMR 7

6~4

3~0

R/W Enable Test Mux Mode

0: Disable 1: Enable

RSV Reserved

RO Test Mux Mode Counter

Show Current Test Mode

0x00 0xFC

GPX MISC Control Register

Offset Name Bit Type Description Default Bank

0x73 GPX_MISC 7~3

RSV Reserved

R/W GPXIOA07 output power fail flag enable

2

0: Disable 1: Enable

R/W GPXIOA03 output power fail flag enable

1

0: Disable 1: Enable

R/W GPXA06 output VC(Voltage comparator) Enable

0

0: Disable 1: Enable

0x00 0xFC

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KB3930 Keyboard Controller Datasheet

4.2.4 GPIO Programming Sample

In this section gives some programming sample to control GPIO module. Please note,

ENE does not guarantee these codes in every field application. The following table describes

scenario of GPIO filed application.

Example

PIN Function

GPIO00 (GA20) Output

GPIO01 (KBRST#) Output

GPIO02 (GPIO) * Input

GPIO03 (GPIO) * Input

GPIO04 (GPIO) Output

GPIO05 (PCIRST#) Input

GPIO06 (GPIO) * Input

GPIO07 (GPIO) Output

Programming model

1. Set function selection register.

GPIOFS00 (0xFC00) = 0x03

2. Set related pins to be output enable.

GPIOOE00 (0xFC10) = 0x93

3. Set related pins to be input enable.

GPIOIE00 (0xFC60) = 0x6C

* GPIO02/03/06 do not exist in KBx930 chip

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KB3930 Keyboard Controller Datasheet

4.3 Keyboard and Mouse Control Interface (KBC)

4.3.1 KBC I/F Function Description

The KBC is compatible with i8042 and responsible for keyboard/mouse accessing via

legacy 60h/64h ports. The port 60h is the data port and port 64h is the command port. The legacy

IRQ1 for keyboard devices and IRQ12 for mouse devices can be generated. The KBC interface

provides fast GA20 control for legacy application.

KBC data register can be accessed by host or KBC firmware. Writing this register will setup a

OBF (Output Buffer Full) flag, which can be clear by firmware. While the host issues I/O write to

60h/64h port, an IBF (Input Buffer Full) flag will assert. The interrupts can be programmed to issue

while the flag of IBF/OBF asserting.

The following table gives a summary about port 60h/64h accessing.

Port Access Type Register Flag Comment

60h I/O Write Data KBCDAT (0xFC85) IBF Write data to keyboard/mouse

64h I/O Write Command KBCCMD (0xFC84) IBF Write command to keyboard/mouse

60h I/O Read Data KBCDAT (0xFC85) OBF Read data from keyboard/mouse

64h I/O Read Status KBCSTS (0xFC86) Read status from keyboard/mouse

KBC data register, KBCDAT, keeps data from host or data written by KBC firmware.

Bit 7 6 5 4 3 2 1 0

Name Keyboard/Mouse Data Register

KBC command register, KBCCMD, is used to keep the command from host. This register is

read only.

Bit 7 6 5 4 3 2 1 0

Name Keyboard/Mouse Command Register

KBC status register, KBCSTS, keeps the status as the following table. For more detail please

refer to the section, KBC Registers Description.

Bit 7 6 5 4 3 2 1 0

Name Parity Error Time Out Aux. Data Flag Un-inhibited Address (A2) System Flag IBF OBF

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KB3930 Keyboard Controller Datasheet

4.3.2 KBC Registers Description

KBC Command Byte Register (KBC command 20h/60h)

Offset Name Bit Type Description Default Bank

0x80 KBCCB 7

R/W PS/2 hardware mode enable

0: Disable 1: Enable

If the host issues command 20h via port 64h, and the KBC returns data via port 60h. This bit will always be read as zero.

R/W Scan code set2 conversion enable (PS/2 scan code set2

6

R/W Disable Auxiliary device

5

R/W Disable Keyboard device

4

R/W Inhibit Override

3

R/W System Flag (warm boot flag)

2

R/W IRQ12 Enable

1

R/W IRQ1 Enable

0

converts to set 1)

0: Disable 1: Enable

0: Enable 1: Disable

0: Disable 1: Enable

0: cold boot 1: warm boot

While KBCSTS[5]=1(Auxiliary Data Flag) and KBCSTS[0]=1 (OBF), then IRQ12 will issue.

0: Disable 1: Enable

While KBCSTS[5]=0 (Auxiliary Data Flag) and KBCSTS[0]=1 (OBF), then IRQ1 will issue.

0: Disable 1: Enable

0x40 0xFC

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KB3930 Keyboard Controller Datasheet

KBC Configuration

Offset Name Bit Type Description Default Bank

0x81 KBCCFG 7

R/W Keyboard lock enable

0: Disable 1: Enable

R/W Fast gate A20 control

6

0: Disable gate A20 control 1: Enable gate A20 control

R/W KBC hardware command sets (90h~93h, D4h) enable.

5

0: Disable 1: Enable

R/W KBC hardware command sets (60h, A7h~ABh, Adh~Aeh)

4

R/W Keyboard lock flag status

3

R/W KBC hardware command sets (A4h, A6h) enable.

2

R/W IBF (KBCSTS[1]) interrupt enable. (IBF from 0 to 1)

1

R/W OBF (KBCSTS[0]) interrupt enable (OBF from 1 to 0)

0

enable.

0: Disable 1: Enable

0: keyboard not lock or not inhibit 1: keyboard lock or inhibit

0: Disable 1: Enable

0x00 0xFC

KBC Interrupt Pending Flag

Offset Name Bit Type Description Default Bank

0x82 KBCIF 7-3

RSV Reserved

R/W1C Status of KBC command handled by firmware

2

While receiving KBC commands which need firmware to handle, the hardware will set this bit. Then the firmware will deal with all the following command until this bit is clear by firmware.

R/W1C IBF interrupt pending flag

1

0: no IBF interrupt occurs 1: IBF interrupt occurs

R/W1C OBF interrupt pending flag

0

0: no OBF interrupt occurs 1: OBF interrupt occurs

0x00 0xFC

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KB3930 Keyboard Controller Datasheet

KBC Hardware Command Enable

Offset Name Bit Type Description Default Bank

0x83 KBCHWEN 7

R/W KBC hardware command set (FEh) enable

0: Disable 1: Enable

R/W KBC hardware command set (E0h) enable

6

0: Disable 1: Enable

R/W KBC hardware command set (D3h) enable

5

0: Disable 1: Enable

R/W KBC hardware command set (D2h) enable

4

0: Disable 1: Enable

R/W KBC hardware command set (D1h) enable

3

0: Disable 1: Enable

R/W KBC hardware command set (D0h) enable

2

0: Disable 1: Enable

R/W KBC hardware command set (C0h) enable

1

0: Disable 1: Enable

R/W KBC hardware command set (20h) enable

0

0: Disable 1: Enable

0x00 0xFC

KBC Command Buffer

Offset Name Bit Type Description Default Bank

0x84 KBCCMD 7-0

RO Command written to port 64h will be stored in this register

0x00 0xFC

KBC Data Input/Output Buffer

Offset Name Bit Type Description Default Bank

0x85 KBCDAT 7-0

R/W Data written to this register to make OBF set (OBF=1).

The host read this register via port 60h.

0x00 0xFC

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KB3930 Keyboard Controller Datasheet

KBC Host Status

Offset Name Bit Type Description Default Bank

0x86 KBCSTS 7

R/W Parity error

0: No parity error occurs in PS/2 protocol 1: Parity error occurs in PS/2 protocol.

R/W Timeout

6

0: No timeout occurs in PS/2 protocol 1: Timeout occurs in PS/2 protocol.

R/W Auxiliary data flag

5

RO Uninhibited

4

0: keyboard inhibited 1: keyboard not inhibited

RO Address (A2)

3

0: output buffer data from 60h 1: output buffer data from 64h

RO System flag

2

R/W1C IBF

1

R/W1C OBF

0

0x00 0xFC

(Reserved)

Offset Name Bit Type Description Default Bank

0x87 RSV 7-0

RSV Reserved

0x00 0xFC

(Reserved)

Offset Name Bit Type Description Default Bank

0x88 RSV 7-0

RSV Reserved

0x00 0xFC

(Reserved)

Offset Name Bit Type Description Default Bank

0x89 RSV 7~0

RSV Reserved

0x00 0xFC

KBC Write Data

Offset Name Bit Type Description Default Bank

0x8A KBCDATR 7-0

RO Read back port of KBCDAT, [0xFC85]

0x00 0xFC

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KB3930 Keyboard Controller Datasheet

4.4 ENE Serial Bus Controller (ESB)

4.4.1 ESB Function Description

To extend the usage of the current design, an ENE serial bus interface is introduced. An

external ESB device can be controlled by firmware transparently. As the following table, 4 memory

address ranges are reserved for ESB devices.

Range1

Range2

Range3

Range4

Memory Range

0xFCA0~0xFCAF

0xFCB0~0xFCBF

0xFCC0~0xFCCF

0xFD00~0xFDFF

In the ESB architecture, external ESB devices are supported. And each device can be

configured with interrupt capability. A figure gives the topology of ENE Serial Bus as following.

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KB3930 Keyboard Controller Datasheet

4.4.2 ESB Registers Description

ESB Configuration

Offset Name Bit Type Description Default Bank

0x90 ESBCFG 7

R/W Loop back test enable

0: Disable 1: Enable

R/W ESB clock selection.

6-5

00: (main clock) / 8 (2MHz) 01: (main clock) / 4 (4MHz) 10: (main clock) / 2 (8MHz) 11: (main clock) / 1 (16MHz)

R/W External device access mode.

4

0: Access external device via 4 predefined memory ranges.

(automatic mode)

1: Access external devices via ESBCA, ESBCD and ESBRD

registers. (byte mode)

R/W ESB clock output enable

3

0: Disable 1: Enable

R/W ESB interrupt enable

2

0: Disable 1: Enable

R/W ESB host queries device interrupt status automatically. (when

1

R/W ESB function enable

0

ESBCFG[3]=1) 0: Disable 1: Enable

0: Disable 1: Enable

0x00 0xFC

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KB3930 Keyboard Controller Datasheet

ESB Command and Status

Offset Name Bit Type Description Default Bank

0x91 ESBCS 7

RSV Reserved

R/W1C Device resume signal flag

6

0: no event 1: event occurs.

R/W1C ESB bus timeout status

5

0: no timeout event 1: bus timeout

R/W1C Device data received status.

4

0: no data received 1: data received.

R ESB host busy flag.

3

0: not busy 1: host busy

W Start to send command, command byte in ESBCD, 0xFC94

2

Please write “0” will not work. 1: send command

R/W ESB access command type (while ESBCFG[3]=1)

1-0

00: interrupt query 01: read 10: write 11: Reserved

0x00 0xFC

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KB3930 Keyboard Controller Datasheet

ESB Interrupt Enable of External Device

Offset Name Bit Type Description Default Bank

0x92 ESBINTE 7

RSV Reserved

R/W Device resume signal interrupt enable

6

0: Disable 1: Enable

R/W Bus timeout interrupt enable

5

0: Disable 1: Enable

R/W Device data received interrupt enable

4

0: Disable 1: Enable

R/W Interrupt enable (IRQ3) of external ESB device.

3

0: Disable 1: Enable

R/W Interrupt enable (IRQ2) of external ESB device.

2

0: Disable 1: Enable

R/W Interrupt enable (IRQ1) of external ESB device.

1

0: Disable 1: Enable

R/W Interrupt enable (IRQ0) of external ESB device.

0

0: Disable 1: Enable

0x00 0xFC

ESB Command Address

Offset Name Bit Type Description Default Bank

0x93 ESBCA 7-0

R/W External ESB device address to be accessed. (when

ESBCFG[3]=1) The address is predefined according to different device.

0x00 0xFC

ESB Command Data

Offset Name Bit Type Description Default Bank

0x94 ESBCD 7-0

R/W Write data port to external ESB device (when ESBCFG[3]=1)

0x00 0xFC

ESB Received Data

Offset Name Bit Type Description Default Bank

0x95 ESBRD 7-0

R/W Read data port to external ESB device (when ESBCFG[3]=1)

If loop back test enabled, ESBCFG[7]=1, the register will be writable, otherwise, read-only.

0x00 0xFC

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KB3930 Keyboard Controller Datasheet

ESB Enable for External Device

Offset Name Bit Type Description Default Bank

0x96 ESBED 7-5

RSV Reserved

R/W Low clock mode enable (clock source 32KHz)

4

For performance and power saving consideration, while low clock mode enabled, please set the query function off.

0: Disable 1: Enable

R/W Enable external ESB device decoding address

3

R/W Enable external ESB device decoding address

2

R/W Enable external ESB device decoding address

1

R/W Enable external ESB device decoding address

0

0xFEE0~0xFEFF

0: Disable 1: Enable

0xFCC0~0xFCCF

0: Disable 1: Enable

0xFCB0~0xFCBF

0: Disable 1: Enable

0xFD00~0xFDFF.

0: Disable 1: Enable

0x00 0xFC

ESB Interrupt Event Pending Flag for External Chip

Offset Name Bit Type Description Default Bank

0x97 ESBINT 7

6

5

4

3

2

1

0

R/W1C Interrupt event pending flag of IRQ7 (cascade mode only)

0: no event 1: event occurs

R/W1C Interrupt event pending flag of IRQ6 (cascade mode only)

0: no event 1: event occurs

R/W1C I Interrupt event pending flag of IRQ5 (cascade mode only)

0: no event 1: event occurs

R/W1C Interrupt event pending flag of IRQ4 (cascade mode only)

0: no event 1: event occurs

R/W1C Interrupt event pending flag of IRQ3

0: no event 1: event occurs

R/W1C Interrupt event pending flag of IRQ2

0: no event 1: event occurs

R/W1C Interrupt event pending flag of IRQ1

0: no event 1: event occurs

R/W1C Interrupt event pending flag of IRQ0

0: no event 1: event occurs

0x00 0xFC

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KB3930 Keyboard Controller Datasheet

ESB Cascade Mode Configuration

Offset Name Bit Type Description Default Bank

0x98 ESBCAS 7

6

5

4

3-1

0

R/W Interrupt enable of IRQ7 for external chip

0: disable 1: enable

R/W Interrupt enable of IRQ6 for external chip

0: disable 1: enable

R/W Interrupt enable of IRQ5 for external chip

0: disable 1: enable

R/W Interrupt enable of IRQ4 for external chip

0: disable 1: enable

RSV Reserved

R/W Cascade mode enable

0: disable 1: enable

0x00 0xFC

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KB3930 Keyboard Controller Datasheet

ESB Programming Sample

In this section gives some programming sample to control ESB module. Please note, ENE

does not guarantee these codes in every field application. The following table describes scenario of

ESB filed application.

Example

A device connecting to ESB master.

Programming model

GPIOFS08[4:3] (0xFC01[4:3])= 11b ; ESB function selection pin

GPIOIE08[4] (0xFC61[4]) = 1b ; set related pin as an input

ESBCFG (0xFC90) = 0x69 ; ESB clock=32MHz / EPB mode enable

ESBED (0xFC96) = 0x02 ; enable ESB

Now F/W can access register 0xFCC0~0xFCCF

55

4.5 Reserved

KB3930 Keyboard Controller Datasheet

This page is leaved blank intentionally.

56

KB3930 Keyboard Controller Datasheet

4.6 PECI

4.6.1 PECI Functional Description

The Platform Environment Control Interface (PECI) is a one-wire bus interface that provides

a communication channel between Intel processor and chipset components to external monitoring

devices. The PECI is a subset of SST(Simple Serial Transport) application. The PECI specification

provides information for electrical requirements, platform topologies, power management handling,

bus device enumeration, commands and addressing for Intel based system.

Please be noted that the PECI enable bit is in GPIO_MISC2, and should be set properly before

PECI start to work.

Figure4.6.1Examplestreamof4bits:“0101”

(Logic ‘0’ encodes into 1000 pulse; Logic ‘1’ encodes into 1110 pulse)

Figure4.6.2ConceptualBlockDiagramforPECIapplication

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KB3930 Keyboard Controller Datasheet

4.6.2 PECI Register Description (Base address = FCD0h, 16 bytes)

PECI function configuration

Offset Name Bit Type Description Default Bank

0xD0 PECICFG 7~6

R/W PECI operation frequency Selection, default support highest

RSV

5

R/W Slow clock at idle state disable (for low power)

4

R/W

3

R/W Stealth cycle at quarter t

2

RSV

1

R/W PECI function enable

0

speed.

00: 2M ~ 15.6k Hz 01: 1M ~ 7.8k Hz 10: 0.5M ~ 3.9k Hz 11: 0.25M ~ 2k Hz

Reserved

0: enable 1: disable

PECI Interrupt Enable (total enable)

time

0: disable 1: enable

This bit is set, then quarter t

Reserved

PECI state machine will come back to idle state, when this bit is disabled.

BIT

time will be reduced 1T.

BIT

0x00 0xFC

PECI function control

Offset Name Bit Type Description Default Bank

0xD1 PECICTL 7~3

RSV

2

R/W Issue abort command

1

R/W Issue package to client

0

Reserve

This bit will be auto clear when abort behavior finish. The originator can't abort message when receives data state.

This bit will be auto clear when package transfer finish.

0x00 0xFC

PECI status observation

Offset Name Bit Type Description Default Bank

0xD2 PECIST 7~6

RSV

5

4

3

2

1

0

Reserved

RO

TX active flag for transmitter state

RO

RX active flag for receiver state

RO

PECI bus line status for debugging

RO

Bus busy

RO

FIFO full flag for write/read state

RO

FIFO empty flag for write/read state

0x01 0xFC

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KB3930 Keyboard Controller Datasheet

PECI interrupt enable control

Offset Name Bit Type Description Default Bank

0xD3 PECIINTE 7

R/W

6

R/W

5

RSV

4

R/W

3

R/W

2

R/W

1

R/W

0

PECI data input de-bounce enable

0: no de-bounce

1: de-bounce enable

PECI output enable selection

0: normal mode

PECI output enable high, when issue package

1: PECI output enable always high

PECI output data selection

0: normal mode

1: PECI output data always high for debugging

Reserved

Interrupt Enable of Client Abort

Interrupt Enable of FCS fault

Interrupt Enable of FIFO half

Interrupt Enable of FIFO error

0x00 0xFC

PECI interrupt status (event pending flag)

Offset Name Bit Type Description Default Bank

0xD4 PECIINT 7~4

RSV

R/W1C

3

R/W1C

2

R/W1C

1

R/W1C

0

Reserved 0x00 0xFC

Interrupt Status of Client Abort

The client reply to FCS is a one's complement. That means client will abort this message.

Interrupt Status of FCS fault

The client reply to FCS is not correct. If FCS value is wrong then this bit will be set.

Interrupt Status of FIFO half If FIFO half, this bit will be set.

That means FW must be write/read register PECIWD/PECIRD.

Interrupt Status of FIFO error

If full flag is set and write data to PECIWD, this bit will be set;

Otherwise, If empty flag is set and read data from PECIRD, then this bit will be set.

If this bit is set, FIFO all pointers and data will be clear.

PECI target address

Offset Name Bit Type Description Default Bank

0xD5 PECIADR 7~0

R/W

This is the address of the PECI device targeted to receive a message.

0x00 0xFC

PECI write length byte

Offset Name Bit Type Description Default Bank

0xD6 PECIWLB 7~0

R/W

The Write Length byte in the PECI header is used to convey the number of bytes the originator will send to the target device. The length byte includes command and data byte.

0x00 0xFC

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KB3930 Keyboard Controller Datasheet

PECI read length byte

Offset Name Bit Type Description Default Bank

0xD7 PECIRLB 7~0

R/W

The Read Length byte is used by the target to determine the

number of data bytes it must supply to the originator before

Returning the FCS over that data.

0x00 0xFC

PECI write data byte

Offset Name Bit Type Description Default Bank

0xD8 PECIWD 7~0

R/W

PECI Write data. This includes both commands and data. All commands require at least one Command byte with the exception of Ping().

0x00 0xFC

PECI read data byte

Offset Name Bit Type Description Default Bank

0xD9 PECIRD 7~0

RO

PECI Received (Read) data from client devices. 0x00 0xFC

PECI received FCS value

Offset Name Bit Type Description Default Bank

0xDA PECICFCS 7~0

RO

The FCS value received from client 0x00 0xFC

PECI generated FCS value

Offset Name Bit Type Description Default Bank

0xDB PECIOFCS 7~0

RO

The FCS value generated from originator 0x00 0xFC

PECI t

Offset Name Bit Type Description Default Bank

0xDC PECIQTB 7~0

counter value observation

bit

RO

The counter value of quarter tBIT time for debugging 0x01 0xFC

PECI FIFO write/read pointer observation

Offset Name Bit Type Description Default Bank

0xDD PECIPOIN 7~4

3~0

RO

FIFO Read Pointer

FIFO read pointer points to the location in the FIFO to read from next

FIFO Write Pointer

FIFO write pointer points to the location in the FIFO to write to next

0x00 0xFC

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KB3930 Keyboard Controller Datasheet

4.7 OWM

4.7.1 OWM Functional Description

OWM is called One Wire Bus Master Interface (GPIO0A).

OWM supports Dallas One Wire Bus Master and TI HDQ protocol.

OWM supports Reset/Break, Read and Write command.

Separate 8-bit read and write buffers.

Configurable timing registers can be setting by F/W.

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KB3930 Keyboard Controller Datasheet

OWM bus master configuration

Offset Name Bit Type Description Default Bank

0xF0 OWMCFG 7

5~4

R/W

6

RSV

3

2

1

0

R/W

EN : One Wire Bus Master Interface Enable

0: Disable One Wire Bus Master Interface

1: Enable One Wire Bus Master Interface

TI/Dallas Mode Select

1: TI mode

0: Dallas mode

Reserved

ETMOI: Enable Timeout Interrupt.

Interrupt occurs if timeout interrupt flag is set

0: Disable

1: Enable

EWRI: Enable Write Command Complete Interrupt.

Interrupt occurs if write command complete flag is set

0: Disable

1: Enable

ERDI: Enable Read Command Complete Interrupt.

Interrupt occurs if read command complete flag is set

0: Disable

1: Enable

ERSTI: Enable Reset/Break Completely Interrupt.

Interrupt occurs if reset/break complete flag is set

0: Disable

1: Enable

0x00 0xFC

OWM bus master status

Offset Name Bit Type Description Default Bank

0xF1 OWMSR 7

6~5

4

3

2

1

0

RO

R/W1C

BSY : One Wire Host Busy Status

0: Idle

1: Busy

Reserved

PDR: Presence Detect Result. (for Dallas Only)

The detect result status of the presence detect when reset/break complete interrupt occurs.

0: Not Exist

1: Exist

TMO: Timeout flag of read/write command for slave response.

0: No timeout event

1: Timeout event

WRC: Status flag of write command for operation completion

0: Write command not complete

1: Write command complete

RDC : Status flag of read command for operation completion

0: Read command not complete

1: Read command complete

RSTC: Status flag of reset/break for operation completion

0: Reset/Break command not complete

1: Reset/Break command complete

(Set when the reset high time reached after reset low time )

0x00 0xFC

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KB3930 Keyboard Controller Datasheet

OWM bus master command

Offset Name Bit Type Description Default Bank

0xF2 OWMCMD 7~2

1~0

RSV

R/W

Reserved 0x03 0xFC

One Wire Interface Command

00: Reset /Break

01: Read

10: Write

11: No operation

OWM bus master write data buffer (transmit)

Offset Name Bit Type Description Default Bank

0xF3 OWMWB 7~0

R/W

The transmit data buffer send to a slave device 0x00 0xFC

OWM bus master read data buffer (receive)

Offset Name Bit Type Description Default Bank

0xF4 OWMRB 7~0

RO

The receive data buffer got from a slave device 0x00 0xFC

OWM reset/break low timing

Offset Name Bit Type Description Default Bank

0xF5 OWMRSTL 7

6~0

RSV

R/W

Reserved 0x40 0xFC

The Reset Time Low interval,,

Clock time base = 8us

OWM reset/break high timing

Offset Name Bit Type Description Default Bank

0xF6 OWMRSTH 7

6~0

RSV

R/W

Reserved 0x40 0xFC

The Reset Time High interval

Clock time base = 8us

OWM write slot timing

Offset Name Bit Type Description Default Bank

0xF7 OWMWT 7~0

R/W

Write 1-bit Data time interval

Clock time base = 2us

0x2D 0xFC

OWM write 1 low timing

Offset Name Bit Type Description Default Bank

0xF8 OWMW1L 7~0

R/W

Write 1 time interval

Clock time base = 1us

0x0A 0xFC

OWM write 0 low timing

Offset Name Bit Type Description Default Bank

0xF9 OWMW0L 7~0

R/w

Write 0 time interval

Clock time base = 1us

0x50 0xFC

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KB3930 Keyboard Controller Datasheet

OWM read slot timing

Offset Name Bit Type Description Default Bank

0xFA OWMRT 7

R/W

Host Read 1-bit Data time, clock time base = 2us . 0x2D 0xFC

OWM read low timing

Offset Name Bit Type Description Default Bank

0xFB OWMRL 7~4

3~0

RSV

R/W

Reserved 0x03 0xFC

For Dallas only, Host to pull low time

Clock time base = 1us

OWM read sample timing

Offset Name Bit Type Description Default Bank

0xFC OWMRS 7~0

R/W

The time interval for Host to check read data 0 or 1,

Clock time base = 1us.

0x14 0xFC

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KB3930 Keyboard Controller Datasheet

4.8 Pulse Width Modulation (PWM)

4.8.1 PWM Function Description

Pulse width modulation (PWM) is a powerful technique for controlling analog circuits with

a processor’s digital outputs. PWM is employed in a wide variety of applications, ranging from

measurement and communications to power control and conversion.

The KBC supports 4 PWM channels. 2 channels (PWM0/PWM1) are for 8-bit resolution

and 2 channels (PWM2/PWM3) are for 14-bit resolution. The PWM provides clock source selection

which is defined in the register description.

. The duty cycle of PWM is illustrated as the above figure. The following table summarizes

the relationship about the applications with the definition in the PWM registers description.

Definition Formula Comment

Duty Cycle (PWM High Period Length+1)/(PWM Cycle Period Length+1) *100%

Cycle Length ( PWM Cycle Length Register +1) * (PWM clock source)

Cycle Length ( PWMCYC + 1 ) * 2 * ( 1 + Prescaler )/(Peripheral clock or fixed 1 MHz)

For 8-bit

For 14-bit

For the limitation of current design, in some critical cases, the PWM output will be the one

as the following table.

Condition PWM Output

H>C Always “1” (High) H=0x00 and C=0x00 Always “1” (High) H=0x00 and C=0xFF A Short Pulse H=0xFF and C=0x00 Always “1” (High) Switch to GPIO mode and output low Always “0” (Low)

H= High Period Length (PWMHIGH) , C= Cycle Period Length (PWMCYCL)

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KB3930 Keyboard Controller Datasheet

4.8.2 PWM Registers Description

PWM Configuration

Offset Name Bit Type Description Default Bank

0x00 PWMCFG 7-6

5

4

3-2

1

0

R/W PWM1 clock source selection

0: 0.976μs (1μs) 1: 62.5μs (64μs) 2: 250μs (256μs) 3: 3.99ms (4ms)

RSV Reserved

R/W PWM1 Enable

0: Disable 1: Enable

R/W PWM0 clock source selection

0: 0.976μs (1μs) 1: 62.5μs (64μs) 2: 250μs (256μs) 3: 3.99ms (4ms)

RSV Reserved

R/W PWM0 Enable

0: Disable 1: Enable

0x00 0xFE

PWM0 High Period Length

Offset Name Bit Type Description Default Bank

0x01 PWMHIGH0 7-0

R/W High Period Length of PWM0.

This should be smaller than Cycle Length.

0x00 0xFE

PWM0 Cycle Length

Offset Name Bit Type Description Default Bank

0x02 PWMCYC0 7-0

R/W Cycle Length of PWM0.

0x00 0xFE

PWM1 High Period Length

Offset Name Bit Type Description Default Bank

0x03 PWMHIGH1 7-0

R/W High Period Length of PWM1.

This should be smaller than Cycle Length.

0x00 0xFE

PWM1 Cycle Length

Offset Name Bit Type Description Default Bank

0x04 PWMCYC1 7-0

R/W Cycle Length of PWM1

0x00 0xFE

Reserved

Offset Name Bit Type Description Default Bank

0x05 RSV 7-0

RSV RSV

0x00 0xFE

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KB3930 Keyboard Controller Datasheet

PWM2 Configuration

Offset Name Bit Type Description Default Bank

0x06 PWMCFG2 7

R/W PWM2 Enable

0: Disable 1: Enable

R/W PWM2 pre-scaler clock selection

6

0: peripheral clock 1: 1MHz clock (fixed)

R/W The 6-bit pre-scaler of PWM2

5-0

The pre-scalar value = register value + 1

0x00 0xFE

PWM3 Configuration

Offset Name Bit Type Description Default Bank

0x07 PWMCFG3 7

6

5-0

R/W PWM3 Enable

0: Disable 1: Enable

R/W PWM3 pre-scaler clock selection

0: peripheral clock 1: 1MHz clock (fixed)

R/W The 6-bit pre-scaler of PWM3

The pre-scaler value = register value + 1

0x00 0xFE

PWM2 High Period Length (14-bit)

Offset Name Bit Type Description Default Bank

0x08

0x09

PWMHIGH2H

PWMHIGH2L

R/W Higher 6 bits (of 14-bit)

5-0

R/W Lower 8 bits (of 14-bit)

7-0

0x00 0xFE

PWM2 Cycle Length (14-bit)

Offset Name Bit Type Description Default Bank

0x0A

0x0B

PWMCYC2H

PWMCYC2L

R/W Higher 6 bits (of 14-bit)

5-0

R/W Lower 8 bits (of 14-bit)

7-0

0x00 0xFE

PWM3 High Period Length (14-bit)

Offset Name Bit Type Description Default Bank

0x0C

0x0D

PWMHIGH3H

PWMHIGH3L

R/W Higher 6 bits (of 14-bit)

5-0

R/W Lower 8 bits (of 14-bit)

7-0

0x00 0xFE

PWM3 Cycle Length (14-bit)

Offset Name Bit Type Description Default Bank

0x0E

0x0F

PWMCYC3H

PWMCYC3L

R/W Higher 6 bits (of 14-bit)

5-0

R/W Lower 8 bits (of 14-bit)

7-0

0x00 0xFE

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KB3930 Keyboard Controller Datasheet

4.8.3 PWM Programming Sample

In this section gives some programming sample to control PWM module. Please note,

ENE does not guarantee these codes in every field application. The following table describes

scenario of PWM filed application.

Example

Programming PWM0 with a period 100ms and high period 40ms, that is, duty cycle is 40%.

100 ms

40 ms

Programming model

1. Set related GPIO function selection register.

GPIOFS08[7] (0xFC01[7]) = 1b

2. Select clock source = 4ms , and enable PWM0

PWMCFG[3:0] (0xFE00[3:0]) = 1101b

3. Cycle = 4ms * (24+1)

PWMCYCL0 (0xFE02) = 0x18

4. Duty cycle = 40/100 = 40% ; (X+1)/(24+1) = 40% -> X=9

PWMHIGH0 (0xFE01) = 0x09

For PWM2/3 as 800Hz pulse :

The formula is as:

(PWMCYC+1)*2*(1+Prescaler)*(1/11Mhz)= (1/800hz)…… (Set Prescaler=0)

PWMCYC = 6874 = 0x1ADB

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KB3930 Keyboard Controller Datasheet

4.9 Fan Controller

4.9.1 Fan Function Description

The KBC provides 2 interfaces with speed monitor for fan control. Two clock selections for fan

controller, one is based on main clock and the other is fixed 62.5μs. The fan controller can be

configured as a PWM function, as known as FANPWM.

4.9.1.1 Fan Tachometer Monitor

The fan tachometer is implemented by a 12-bit counter with four resolution(In Reg

FANSTS0/FANSTS1) as follows, 62.5μs, 31.25μs, 15.625μs, 7.8125μs. The following figure

gives an example for fan speed monitor and control with 62.5μ s. The KBC uses the pin

FANPWM0/1 to drive external fan device, and the fan device feedback the speed via the pin

FANFB0/1. The fan controller keeps the speed in the monitor register. The fan controller will

compare the speed and check if the current speed is higher or slower than the expected one. If

slower, then the controller will increase the frequency to drive FANPWM0/1 automatically, otherwise

decrease the frequency. The expected speed can be programmable by F/W.

As following RPM table is given for programmers. In this table, the information between RPM

and value for fan speed set is shown with 62.5μs resolution. The target speed counter value is

require when fan controller is operated under auto-fan mode.

RPM Round/1min Round/1sec

6000 6000 100 10000 160 (10000/62.5)

5000 5000 83.33 12000 192 (12000/62.5)

4000 4000 66.667 15000 240 (15000/62.5)

3000 3000 50 20000 320 (20000/62.5)

2000 2000 33.333 30000 480 (30000/62.5)

1000 1000 16.667 60000 960 (60000/62.5)

500 500 8.3 120000 1920(120000/62.5)

μs/Round

RPM (round/min) = 60,000,000 / (FANMON *62.5)

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Value (Set Counter)

KB3930 Keyboard Controller Datasheet

4.9.1.2 FANPWM Function

The fan controller can be used as a 12-bit PWM function. While PWM function applied, the fan

controller will refer to the peripheral clock, and the PWM high period and cycle time can be

determined as the following formula:

PWM Cycle Length = (PWM cycle register + 1 ) * peripheral clock resolution

PWM High Period = (PWM high period register + 1 ) * peripheral clock

Please note, to program the high pulse width of PWM (FANPWMH0/FANPWML0 and

FANPWMH1/FANPWML1, i.e., 0xFE26/0xFE27 and 0xFE36/0xFE37), high-byte first and then

low-byte in order.

The fan controller could be operated in Auto-fan or Fixed-fan mode.

In Auto-fan mode, it’s required to set the Fan Speed Set Counter Value based on the table in

4.9.1.1 (Be cautious that the resolution could be different by register value)

In Fixed-fan mode, it’s required to set the PWM cycle length, PWM high period based on the

formula in 4.9.1.2. By setting these registers, specific PWM frequency, duty cycle could be

generated.

4.9.2 Fan Registers Description

Fan0 Configuration

Offset Name Bit Type Description Default Bank

0x20 FANCFG0 7

R/W FAN0 monitor clock selection.

0: peripheral clock

1: the monitor base clock will based on FANSTS0[6:5](0xFE21)

R/W

6

R/W FANPWM0 cycle width enable

5

R/W FANPWM0 enable.

4

R/W FAN0 speed monitor interrupt enable

3

R/W FAN0 speed monitor timeout error interrupt enable

2

R/W Auto-fan mode control enable.

1

R/W FAN0 tachometer monitor enable.

0

FAN0 speed monitor counter edge trigger selection.

0: count pulse event on rising edge. 1: count pulse event on rising and falling edge.

0: Disable 1: Enable

FANCFG0[0] and FANCFG0[4] should be set at the same time to make it work. (The tachometer is required for feedback, PWM should also be enabled)

0: Disable 1: Enable

0x00 0xFE

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KB3930 Keyboard Controller Datasheet

Fan0 Control and Status Register

Offset Name Bit Type Description Default Bank

0x21 FANSTS0 7

R/W FAN0 auto-load FANCPWM function enable

0: Disable 1: Enable

R/W FANPWM clock resolution selection.

6-5

FANCFG0[7](0xFE20) should be set for selection take effect

00: 62.5us (default) 01: 31.25us 10: 15.625us 11: 7.8125us

R/W FAN0 digital noise filter enable.

4

0: Disable 1: Enable

RSV Reserved

3-2

R/W1C Flag of FAN0 speed monitor timeout error

1

0: no timeout error 1: timeout error event

R/W1C Flag of FAN0 speed monitor update event.

0

0: no update event. 1: update event

0x00 0xFE

Fan0 Speed Monitor Counter Value (12-bit)

Offset Name Bit Type Description Default Bank

0x22 FANMONH0 3-0

0x23 FANMONL0 7-0

RO High 4 bits of FAN0 speed monitor counter value

RO Low 8 bits of FAN0 speed monitor counter value

0x0F 0xFE

0xFF 0xFE

Fan0 Speed Set Counter Value (12-bit)

Offset Name Bit Type Description Default Bank

0x24 FANSETH0 3-0

0x25 FANSETL0 7-0

Notice: These two registers are used in auto-fan mode and are set as target fan speed counter value

R/W High 4 bits of target FAN0 speed counter value.

R/W Low 8 bits of target FAN0 speed counter value.

0x00 0xFE

FANPWM0 High Pulse Width Bits (12-bit)

Offset Name Bit Type Description Default Bank

0x26 FANPWMH0 3-0

0x27 FANPWML0 7-0

Notice: These two registers are used in fixed-fan mode and are set as target FANPWM width to change effective fan speed

PWM high period = (PWM high pulse register + 1) * peripheral clock

R/W High 4 bits of FANPWM0 high pulse width.

(FANCFG0[1]=0 only)

R/W Low 8 bits of FANPWM0 high pulse width.

(FANCFG0[1]=0 only)

0x00 0xFE

Current FANPWM0 High Pulse Width Bits (12-bit)

Offset Name Bit Type Description Default Bank

0x28

0x29

FANCPWMH0

FANCPWML0

3-0

7-0

RO

High 4 bits of current FANPWM0 high pulse width.

RO

Low 8 bits of current FANPWM0 high pulse width.

0x00 0xFE

FANPWM0 Cycle Length (12-bit)

71

Offset Name Bit Type Description Default Bank

0x2A

0x2B

Notice: These two registers are used in fixed-fan mode and are set as target FANPWM cycle Cycle length = (PWM cycle register + 1 ) * peripheral clock

FANPWMCH0

FANPWMCHL0

R/W High 4 bits of Cycle length of FANPWM0 (FANCFG0[5]=1)

3-0

R/W Low 8 bits of Cycle length of FANPWM0 (FANCFG0[5]=1)

7-0

KB3930 Keyboard Controller Datasheet

0x00 0xFE

FANPWM0 Auto-Load High Pulse Width Bits

Offset Name Bit Type Description Default Bank

0x2C FANUPWM0 7-4

RSV Reserved

R/W If auto-load feature enabled (FANSTS0[7]=1), this register

3-0

value will be auto-loaded into FANCPWMH0 registers and FANCPWML0 will be forced to be zero while monitor timeout occurs

0x0F 0xFE

FAN tachometer monitor controller configuration for FANFB2

Offset Name Bit Type Description Default Bank

0x2D FANTMCFG0 7-6

5-4

RSV Reserved

R/W

R/W1C Flag bit for Fan tachometer monitor timeout error event.

3

R/W FAN digital filter enable for Fan tachometer monitor

2

R/W Test mode enable for Fan tachometer monitor

1

R/W FAN tachometer monitor enable

0

FAN tachometer monitor speed sample range FANTMCFG0[1](0xFE2D) should be set

00: 62.5us (default) 01: 31.25us 10: 15.625us

11: 7.8125us

0: no timeout error 1: timeout error event

0: Disable 1: Enable

1: the monitor base clock will be peripheral clock. 0: the monitor base clock will be based on FANTMCFG0[5:4]

To enable addition FAN Tachometer Monitor FANFB2

0: Disable 1: Enable

0x00 0xFE

for selection take effect

FAN tachometer monitor speed monitor counter value for FANFB2

Offset Name Bit Type Description Default Bank

0x2E

0x2F

FANTMMONH0

FANTMMONL0

R/W High 4 bits of FANFB2 speed monitor counter value

3-0

R/W Low 8 bits of FANFB2 speed monitors counter value.

7-0

0x0F 0xFE

0xFF 0xFE

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KB3930 Keyboard Controller Datasheet

Fan1 Configuration

Offset Name Bit Type Description Default Bank

0x30 FANCFG1 7

R/W FAN1 monitor clock selection.

0: peripheral clock

1: the monitor base clock will based on FANSTS1[6:5](0xFE31)

R/W

6

R/W FANPWM1 cycle width enable

5

R/W FANPWM1 enable.

4

R/W FAN1 speed monitor interrupt enable

3

R/W FAN1 speed monitor timeout error interrupt enable

2

R/W Automatic FANPWM control enable.

1

R/W FAN1 tachometer monitor enable.

0

FAN1 speed monitor counter edge trigger selection.

0: count pulse event on rising edge. 1: count pulse event on rising and falling edge.

0: Disable 1: Enable

FANCFG1[0] and FANCFG1[4] should be set at the same time to make it work. (The tachometer is required for feedback, PWM should also be enabled)

0: Disable 1: Enable

0x00 0xFE

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KB3930 Keyboard Controller Datasheet

Fan1 Control and Status Register

Offset Name Bit Type Description Default Bank

0x31 FANSTS1 7

R/W FAN1 auto-load FANCPWM function enable

0: Disable 1: Enable

R/W FANPWM clock resolution selection.

6-5

FANCFG1[7](0xFE30) should be set for selection take effect

00: 62.5us (default) 01: 31.25us 10: 15.625us 11: 7.8125us

R/W FAN1 digital noise filter enable.

4

0: Disable 1: Enable

R/W Reserved

3-2

R/W Flag of FAN1 speed monitor timeout error

1

0: no timeout error 1: timeout error event

R/W Flag of FAN1 speed monitor update event.

0

0: no update event. 1: update event

0x00 0xFE

Fan1 Speed Monitor Counter Value (12-bit)

Offset Name Bit Type Description Default Bank

0x32 FANMONH1 3-0

0x33 FANMONL1 7-0

R/W High 4 bits of FAN1 speed monitor counter value

R/W Low 8 bits of FAN1 speed monitor counter value

0x0F 0xFE

0xFF 0xFE

Fan1 Speed Set Counter Value (12-bit)

Offset Name Bit Type Description Default Bank

0x34 FANSETH1 3-0

0x35 FANSETL1 7-0

Notice: These two registers are used in auto-fan mode and are set as target fan speed counter value

R/W High 4 bits of target FAN1 speed counter value.

R/W Low 8 bits of target FAN1 speed counter value.

0x00 0xFE

FANPWM1 High Pulse Width Bits (12-bit)

Offset Name Bit Type Description Default Bank

0x36 FANPWMH1 3-0

0x37 FANPWML1 7-0

Notice: These two registers are used in fixed-fan mode and are set as target FANPWM width to change effective fan speed PWM high period = (PWM high pulse register + 1) * peripheral clock

R/W High 4 bits of FANPWM1 high pulse width.

(FANCFG1[1]=0 only)

R/W Low 8 bits of FANPWM1 high pulse width.

(FANCFG1[1]=0 only)

0x00 0xFE

Current FANPWM1 High Pulse Width Bits (12-bit)

Offset Name Bit Type Description Default Bank

0x38

0x39

FANCPWMH1

FANCPWML1

RO High 4 bits of current FANPWM1 high pulse width.

3-0

RO Low 8 bits of current FANPWM1 high pulse width.

7-0

0x00 0xFE

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KB3930 Keyboard Controller Datasheet

FANPWM1 Cycle Length (12-bit)

Offset Name Bit Type Description Default Bank

0x3A

0x3B

Notice: These two registers are used in fixed-fan mode and are set as target FANPWM cycle Cycle length = (PWM cycle register + 1 ) * peripheral clock

FANPWMCH1

FANPWMCHL1

R/W High 4 bits of Cycle length of FANPWM1 (FANCFG1[5]=1)

3-0

R/W Low 8 bits of Cycle length of FANPWM1 (FANCFG1[5]=1)

7-0

0x00 0xFE

FANPWM1 Update High Pulse Width Bits

Offset Name Bit Type Description Default Bank

0x3C FANUPWM1 7-4

RSV Reserved

R/W If auto-load feature enabled (FANSTS1[7]=1), this register

3-0

value will be auto-loaded into FANCPWMH1 registers and FANCPWML1 will be forced to be zero while monitor timeout occurs

0x0F 0xFE

FAN tachometer monitor controller configuration for FANFB3

Offset Name Bit Type Description Default Bank

0x3D FANTMCFG1 7-6

5-4

RSV Reserved

R/W

R/W1C Flag bit for Fan tachometer monitor timeout error event.

3

R/W FAN digital filter enable for Fan tachometer monitor

2

R/W Test mode enable for Fan tachometer monitor

1

R/W FAN tachometer monitor enable

0

FAN tachometer monitor speed sample range FANTMCFG1[1](0xFE3D) should be set

00: 62.5us (default) 01: 31.25us 10: 15.625us

11: 7.8125us

0: no timeout error 1: timeout error event

0: Disable 1: Enable

1: the monitor base clock will be peripheral clock. 0: the monitor base clock will be based on FANTMCFG1[5:4]

To enable addition FAN Tachometer Monitor FANFB3

0: Disable 1: Enable

0x00 0xFE

for selection take effect

FAN tachometer monitor speed monitor counter value for FANFB3

Offset Name Bit Type Description Default Bank

0x3E

0x3F

FANTMMONH1

FANTMMONL1

R/W High 4 bits of FANFB3 speed monitor counter value

3-0

R/W Low 8 bits of FANFB3 speed monitors counter value.

7-0

0x0F 0xFE

0xFF 0xFE

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KB3930 Keyboard Controller Datasheet

4.9.3 Fan Programming Sample

In this section gives some programming sample to control FAN module. Please note, ENE

does not guarantee these codes in every field application. The following table describes scenario of

FAN filed application.

Example

FAN0 @ 4000 rpm with automatic PWM control

FAN1 @ some rpm with fixed PWM control

Programming model

For FAN0:

1. set related GPIO function select register to enable alternative output.

GPIOFS10[2] (0xFC02[2]) = 1b

2. set related GPIO input enable.

GPIOIE10[4] (0xFC62[4]) = 1b

3. set FAN0 configuration register

FANCFG0 (0xFE20) = 0x93

4. set FAN0 speed monitor counter value

FANMONH0 (0xFE24) = 0x00

FANMONL0 (0xFE25) = 0xF0

For FAN1:

1. set related GPIO function select register to enable alternative output.

GPIOFS10[3] (0xFC02[3]) = 1b

2. set FAN1 configuration register

FANCFG1 (0xFE30) = 0x90

3. set FAN1 speed monitor counter value

FANPWMH1 (0xFE36) = 0x03

FANPWML2 (0xFE37) = 0xE8

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4.10 General Purpose Timer (GPT)

4.10.1 GPT Function Description

The KBC provides 4 GPTs (General Purpose Timers), two 16-bit timers and two 8-bit

timers. These 4 GPTs operate based on 32.768KHz and all timers have the interrupt capability. The

GPT is simply a free run counter. While the timer meets the specific value in count register, for

instance, 0xFE53 and 0xFE55, an interrupt issues (if interrupt enabled) and the counter reset to be

zero.

- GPT0 and GPT1 are 8-bit timers.

- GPT2 and GPT3 are 16-bit timers.

4.10.2 GPT Registers Description

GPT Configuration

Offset Name Bit Type Description Default Bank

0x50 GPTCFG 7-5

RSV Reserved

R/W GPT test mode enable.

4

In test mode, the GPT runs with main clock.

0: Disable 1: Enable

R/W GPT3 counting and interrupt enable.

3

0: Disable 1: Enable

R/W GPT2 counting and interrupt enable.

2

0: Disable 1: Enable

R/W GPT1 counting and interrupt enable.

1

0: Disable 1: Enable

R/W GPT0 counting and interrupt enable.

0

0: Disable 1: Enable

0x00 0xFE

GPT Pending Flag

Offset Name Bit Type Description Default Bank

0x51 GPTPF 7

WO Writing “1” to this bit forces GPT3 restart.

WO Writing “1” to this bit forces GPT2 restart.

6

WO Writing “1” to this bit forces GPT1 restart.

5

WO Writing “1” to this bit forces GPT0 restart.

4

R/W1C Interrupt pending flag of GPT3.

3

R/W1C Interrupt pending flag of GPT2.

2

R/W1C Interrupt pending flag of GPT1.

1

R/W1C Interrupt pending flag of GPT0.

0

0x00 0xFE

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GPT0 Counter Value

Offset Name Bit Type Description Default Bank

0x53 GPT0 7-0

R/W Once GPT0 counter meets this value, an interrupt issues.

GPT0 restart to count from zero.

0x00 0xFE

Reserved

Offset Name Bit Type Description Default Bank

0x54 RSV 7-0

RSV Reserved

0x00 0xFE

GPT1 Counter Value

Offset Name Bit Type Description Default Bank

0x55 GPT1 7-0

R/W

Once GPT1 counter meets this value, an interrupt issues.

GPT1 restart to count from zero.

0x00 0xFE

GPT2 Counter Value (16-bit)

Offset Name Bit Type Description Default Bank

0x56 GPT2H 7-0

0x57 GPT2L 7-0

R/W High byte of GPT2 counter value

R/W Low byte of GPT2 counter value

Once GPT2 counter meets this 16-bit value, an interrupt issues. GPT2 restart to count from zero.

0x00 0xFE

GPT3 Counter Value (16-bit)

Offset Name Bit Type Description Default Bank

0x58 GPT3H 7-0

0x59 GPT3L 7-0

R/W High byte of GPT3 counter value.

R/W Low byte of GPT3 counter value.

Once GPT3 counter meets this 16-bit value, an interrupt issues. GPT3 restart to count from zero.

Once GPT2 counter meets this 16-bit value, an interrupt issues. GPT3 restart to count from zero.

0x00 0xFE

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4.10.3 GPT Programming Sample

In this section gives some programming sample to control GPT module. Please note,

ENE does not guarantee these codes in every field application. The following table describes

scenario of GPT filed application.

Example

Programming GPT0 to issue an interrupt every 5ms

Programming model

1. Set GPT configuration register, enable GPT0 interrupt.

GPTCFG[0] (0xFE50[0]) = 1b

2. Fill the GPT counter value.

GPT0 (0xFE53) = 0xA6 ; 5000/30 = 0xA6

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KB3930 Keyboard Controller Datasheet

4.11 SDI Host/Device Interface Controller

The SDI host/device controller can be programmed to a SPI Host or a SPI Device (0xFE74.7).

The Default is the SPI Host. The SPI Host and Device use the same IO.

4.11.1 SDI Host/Device Interface Description

The Serial Peripheral Interface Bus or SPI (often pronounced “spy”) bus is a

synchronous serial data link standard designed by Motorola that operates in full duplex mode.

Devices communicate in master/slave mode where the master device initiates the data frame.

In KBCx930, the SDI host could support the SPI mode 0/1, and is configurable by SFICFG[1]

SDI slave could support the SPI mode 0.

4.11.2 SDI Host Interface Description

SDI host interface configuration

Offset Name Bit Type Description Default Bank

0x70 SHICFG 7

RO SDI host Idle flag. If this bit set, the SDI host is in an idle state.

0: busy 1: idle

RSV Reserved

6-5

R/W

4

R/W SDI host CLK divider.

3-2

R/W SDI Host SDIMOSI/SDIMISO Timing.

1

R/W SDI host controller enable

0

SDI host SDICS# Pin Control

0 : Set SDICS# High

1 : Set SDICS# Low

SPICLK frequency = peripheral clock / [( divider +1)*2]

0: SDIMOSI changes data at falling edge of SDICLK. (device

latches at rising edge of SDICLK)

SDIMISO latch data at rising edge of SDICLK. (device

changes at falling edge of SDICLK).

1: SDIMOSI changes data at rising edge of SDICLK. (device

latches at falling edge of SDICLK)

SDIMISO latch data at falling edge of SDICLK. (device

changes at rising edge of SDICLK).

0: Disable 1: Enable

0x00 0xFE

SDI host interface transmit data port

Offset Name Bit Type Description Default Bank

0x71 SHITBUF 7-0

R/W While SHICFG[7]=0 (SDI not busy), writing to this register

forces data output to SDIMOSI in continuously serial 8 bits. MSB first.

0x00 0xFE

SDI host interface receive data port

Offset Name Bit Type Description Default Bank

0x72 SHIRBUF 7-0

RO SDI host reading port.

0x00 0xFE

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4.11.2 SDI Device Interface Description

SDI device interface configuration

Offset Name Bit Type Description Default Bank

0x78 SDICFG 7

6~4

RO SDICS# status

RSV Reserved

R/W SDI command mode

3

0: Disable. (Normal mode) 1: Enable. (Command mode)

(When enable this mode, SDICFG[2:1] would not take effect) (Configurable command : Read TX buffer in register SDICMD)

R/W Enable SDI device TX.

2

0: Disable 1: Enable

R/W Enable SDI device RX.

1

0: Disable 1: Enable

R/W SDI device controller enable

0

0: Disable 1: Enable

0x44 0xFE

SDI device interface interrupt configuration

Offset Name Bit Type Description Default Bank

0x79 SDIRS 7

RSV Reserved

R/W1C (Normal mode only) Transmit buffer empty pending flag

6

R/W1C (Normal mode only) Receive buffer full pending flag

5

R/W1C SDICS# rising edge pending flag

4

RSV Reserved

3

R/W (Normal mode only) Transmit buffer empty interrupt enable bit

2

0: Disable 1: Enable

R/W (Normal mode only) Receive buffer full interrupt enable bit

1

0: Disable 1: Enable

R/W SDICS# rising edge interrupt enable bit

0

0: Disable 1: Enable

0x00 0xFE

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SDI device interface transmit status

Offset Name Bit Type Description Default Bank

0x7A SDITSTS 7

6~4

RSV Reserved

RO

RSV Reserved

3

R/W1C (Normal mode only) Transmit buffer underflow flag

2

1

0

RO (Normal mode only) Transmit buffer full flag

R (Normal mode only) Transmit buffer empty flag

W Write 1 to clear Tx buffer

Transmit buffer count

In normal mode:

The count is the number how many data in Tx Buffer aren’t transmitted yet.

In command mode:

The count is the number of transmitted byte data in single transition.

Normal mode:

FIFO's write point and read point are both reset to point to position "0".

Command mode:

Only FIFO's write point is reset to point to position "0".

0x00 0xFE

SDI device interface receive status

Offset Name Bit Type Description Default Bank

0x7B SDIRSTS 7

6~4

RSV Reserved

RO

RSV Reserved

3

R/W1C (Normal mode only) Receive buffer overflow flag

2

1

0

RO (Normal mode only) Receive buffer full flag

R (Normal mode only) Receive buffer empty flag

W Write 1 to clear Rx buffer

Receive Buffer count

Normal mode :

The count is the number how many data in Rx Buffer aren’t read yet.

Command mode:

The count is the number of received byte data in single transition.

Normal mode:

FIFO's write point and read point are both reset to point to position "0".

Command mode:

Only FIFO's write point is reset to point to position "0".

0x00 0xFE

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SDI device interface transmit data port

Offset Name Bit Type Description Default Bank

0x7C SDITBUF 7~0

WO SDI Device Interface Transmitted Data Port

(4 bytes buffers, External SPI Host must supply SPI clock) Normal mode: Please check full flag to finish the write operation. If the TX buffer is full, SDI will skip the newly data and preserve

the previous data. If the TX buffer is empty, SDI will always Transmit data = 0x00.

0x00 0xFE

SDI device interface receive data port

Offset Name Bit Type Description Default Bank

0x7D SDIRBUF 7

RO SDI Device Interface Received Data Port

(4 bytes buffers, Read the data from the external SPI Host)

Normal mode:

Please check empty flag to finish the reading operation. If the RX buffer is full, SDI will skip the newly data and preserve

the previous data. If the RX buffer is empty, SDI will always read data = 0x00.

Command mode:

In a transaction, SDI will only receive 4 bytes data. If over 4 bytes data, SDI will skip the newly data and preserve

the previous data. We can read the RX buffer according the Rx buffer's read point.

0x00 0xFE

Command : Read TX buffer

Offset Name Bit Type Description Default Bank

0x7E SDICMD 7~0

R/W Configurable command. : Read TX buffer

This function should be used along with SDI command mode (SDICFG[3], 0xFE78.3 = 1)

0x5A 0xFE

SDI TX/RX buffer write point and read point

Offset Name Bit Type Description Default Bank

0x7F SDIPT 7~6

5~0

RO Normal mode:

When writing SDI Tx buffer, write point will increase 1 until SDI Tx buffer is full.

Command mode:

When writing SDI Tx buffer, write point will increase 1.

RSV Reserved

0x00 0xFE

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4.11.3 SDI Programming Sample

In this section gives some programming sample to control SDI module. Please note,

ENE does not guarantee these codes in every field application. The following table describes

scenario of SDI filed application.

Example

A SPI device is attached. Here is a READ STATUS command.

Programming model

GPXAFS00[2:0] (0xFC0C[2:0]) = 111b; //Select SDI function pins

GPXDIE00[0] (0xFC6C[0]) = 1b; //Enable SDI data input

SDICSR (0xFE70) = 0x01; //Set SDICS# low, SPI clock = Peripheral //clock/2

SDIBO (0xFE71) = 0x05; //Transfer CMD(0x05) to device

Wait SDICSR[7] (0xFE70[7]) = 1b; //Wait bus idle

SDIBO (0xFE71) = 0x00; //Transfer dummy byte to device and //device sends status byte to SDI

Wait SDICSR[7] (0xFE70[7]) = 1b; //Wait bus idle

SDICSR (0xFE70) = 0x00; //Set SDICS# high

Read SDIBI (0xFE72); //Get device status

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4.12 Watchdog Timer (WDT)

4.12.1 WDT Function Description

A Watchdog Timer (WDT) is a hardware timing device that triggers a system reset while

the system encounters any unrecoverable situation. The WDT utilizes 32.768KHz for operation. The

WDT triggers the system reset in three ways.

- Reset the 8051 microprocessor only.

- Reset the whole logic, except GPIO modules.

- Reset the whole logic, including GPIO modules.

Here gives the highlight of WDT features:

- 20 bit Watchdog

- Watchdog password protection.

- Interrupt support.

- WDT LED blinking support.

- New 24 bit timer (TMR) support.

4.12.2 WDT Registers Description

WDT Configuration

Offset Name Bit Type Description Default Bank

0x80 WDTCFG 7

R/W WDT clock source selection

0: DPLL 32.768KHz source 1: Internal OSC or External Crystal 32.768KHz source

RSV

6~4

RSV Reserved

3

R/W WDT test mode enable.

2

R/W WDT interrupt enable.

1

R/W WDT reset enable.

0

Reserved

0: normal mode 1: test mode, clock driven by internal 32MHz. (WDTCFG[7]

ignore)

0: Disable 1: Enable

Once WDT resets, two WDT pending flags are clear.

0: Disable 1: Enable

0x00 0xFE

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WDT Pending Flag

Offset Name Bit Type Description Default Bank

0x81 WDTPF 7-5

RSV Reserved

R/W1C WDT interrupt flag

1

Once the timer counts to half of WDT (0xFE82), an interrupt occurs. If the timer counts to WDT(0xFE82), a WDT reset occurs.

0: no event 1: event occurs

R/W1C WDT reset flag

0

Once the timer counts to WDT (0xFE82), a WDT reset occurs and this flag is set.

0: no event 1: event occurs

0x00 0xFE

WDT High 8-bit Counter Value (for WDT reset system of 10 bits counter)

Offset Name Bit Type Description Default Bank

0x82 WDT 7-0

R/W The high 8-bits of WDT counter value.

The WDT timer unit is 32ms. Please note, fill this value at least greater than or equal 3 (>=3)

for hardware limitation.

0x00 0xFE

WDT Blinking LED Configuration

Offset Name Bit Type Description Default Bank

0x83 LEDCFG 7~6

5-3

2-0

R/W The low 2-bits of WDT counter value.

The WDT timer unit is 32ms. Please note, fill this value at least greater than or equal 3 (>=3)

for hardware limitation.

RSV Reserved

R/W LED Blinking configuration.

0: LED output keeps high 1: LED output keeps low 500ms for every 1 sec. 2: LED output keeps low 500ms for every 2 sec 3: LED output keeps low 500ms for every 4 sec 4: LED output keeps low 500ms for every 8 sec

0x00 0xFE

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WDT TMR (24-bit Timer) Configuration

Offset Name Bit Type Description Default Bank

0x84 TMR_CFG 7

R/W TMR enable

0: Disbale/reset TMR 1:Enable TMR

RSV Reserved

6~3

RO TMR interrupt pending flag overflow.

2

While TMR interrupt flag (TMR_CFG[1]) is set and an interrupt event occurs again. This bit will be set and can be clear via writing TMR_CFG[7] with “0”.

0: no event 1: event occurs

R/W1C TMR interrupt flag.

1

When TMR counter[23:16] is equal to TMR_MATCH register. This bit will be set.

0: no event 1: event occurs

R/W TMR counter start control.

0

0: stop counting 1: start counting

0x00 0xFE

WDT TMR (24-bit Timer) Counter Match Value

Offset Name Bit Type Description Default Bank

0x85

TMR_MATCH

R/W The 8bit match value register.

7-0

If the clock source is from 32.768KHz OSC, the time base is approximated as 2.048s. When timer counter[23:16] is reached this value, timer emits interrupt and TMR_CFG[1] is set to 1 .

0x00 0xFE

WDT TMR (24-bit Timer) Counter Value 1

Offset Name Bit Type Description Default Bank

0x86 TMR_V1 7-0

RO Value for TMR counter[23:16]

0x00 0xFE

WDT TMR (24-bit Timer) Counter Value 2

Offset Name Bit Type Description Default Bank

0x87 TMR_V2 7-0

RO Value for TMR counter[15:8]

0x00 0xFE

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KB3930 Keyboard Controller Datasheet

4.12.3 WDT Programming Sample

In this section gives some programming sample to control WDT module. Please note, ENE

does not guarantee these codes in every field application. The following table describes scenario of

WDT filed application.

Example

Set WDT=512ms to reset system, and an interrupt occurs while WDT=256ms (half of WDT)

Programming model

WDT (0xFE82) = 0x10 ; set WDT=512ms

WDTCFG (0xFE80) = 0x03 ; enable interrupt and WDT reset

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KB3930 Keyboard Controller Datasheet

4.13 Low Pin Count Interface (LPC)

4.13.1 LPC Function Description

The Low Pin Count (LPC) is an interface for modern ISA-free system. The KBC

connects to the system via LPC interface. The following LPC cycle types are supported.

Type Address Data

LPC I/O Read 16-bit 8-bit

LPC I/O Write 16-bit 8-bit

LPC Memory Read 32-bit 8-bit

LPC Memory Write 32-bit 8-bit

FWH Read 28-bit 8-bit

FWH Write 28-bit 8-bit

4.13.2 LPC I/O Decode Range

Item Port Comment

Keyboard Controller 60h/64h

Embedded Controller 62h/66h (default) Programmable

Legacy I/O 68h/6Ch, 2Eh/2Fh

EC Index-I/O FF29h~FF2Bh/FF2Dh~FF2Fh(default) 2 Sets, Programmable.

Debug Port 80h Only write cycle support interrupt

4.13.3 LPC Memory Decode Range

Memory Address (hex) Size Setting

(LPCSCFG[3],LPCFWH[7:6])

000C_0000 ~ 000F_FFFF＊

FFFC_0000 ~ FFFF_FFFF

000C_0000 ~ 000F_FFFF＊

FFF8_0000 ~ FFFF_FFFF

000C_0000 ~ 000F_FFFF＊

FFF0_0000 ~ FFFF_FFFF

000C_0000 ~ 000F_FFFF＊

FFE0_0000 ~ FFFF_FFFF

000C_0000 ~ 000F_FFFF＊

FFC0_0000 ~ FFFF_FFFF

000E_0000 – 000F_FFFF

FFFE_0000 – FFFF_FFFF

＊ LPC module decodes low memory address only in 256K range.

256K (default) 0b,00b

512K 0b,01b

1M 0b,10b

2M 0b,11b

4M 1b,00b

128K 1b,11b

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KB3930 Keyboard Controller Datasheet

4.13.4 FWH Memory Decode Range

Memory Address (hex) Size Setting

(LPCSCFG[3],LPCFWH[7:6])

00C_0000 ~ 00F_FFFF＊

FFC_0000 ~ FFF_FFFF

00C_0000 ~ 00F_FFFF＊

FF8_0000 ~ FFF_FFFF

00C_0000 ~ 00F_FFFF＊

FF0_0000 ~ FFF_FFFF

00C_0000 ~ 00F_FFFF＊

FE0_0000 ~ FFF_FFFF

00C_0000 ~ 00F_FFFF＊

FC0_0000 ~ FFF_FFFF

00E_0000 – 00F_FFFF

FFE_0000 – FFF_FFFF

＊ LPC module decodes low memory address only in 256K range.

256K (default) 0b,00b

512K 0b,01b

1M 0b,10b

2M 0b,11b

4M 1b,00b

128K 1b,11b

4.13.5 Index-I/O Port

The KBC provides a method to communicate with the host via legacy I/O port. The host

can access the XRAM space inside the KBC. The I/O port is called Index-I/O. Two Index-I/Os are

supported and programmable. The registers, LPCIBAH and LPCIBAL (0xFE92 and 0xFE93), are

nd

used to specify the desired I/O port base. To enable the 2

should be set. The index-I/O base address will be 8 bytes align if the LPCSCFG[5] set, otherwise 4

bytes alignment . For example, while the base address is 0xFF2C and LPCSCFG[5] set, the 1

index-I/O address will be 0xFF29 (io_base +1).

The following table collects the port definition for the host

is assumed to be io_base.

1st Index-I/O 2nd Index-I/O (LPCSCFG[5]=1)

XRAM address (high) io_base+1 XRAM address (high) io_base+5

XRAM address (low) io_base+2 XRAM address (low) io_base+6

XRAM data (high) io_base+3 XRAM data (high) io_base+7

Index-I/O, the LPCSCFG[5], (0xFE90[5])

st

. The base address of Index-I/O

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KB3930 Keyboard Controller Datasheet

Here is an example how to use an Index-I/O.

EC F/W Host software

1. EC F/W setups the base address, for instance, 0x380. That is, LPCIBAH=0x03 and LPCIBAL=0x80.

nd

2. If the 2 bit. That is, LPCSCFG[5]=1 (0xFE90[5]=1).

Index-I/O is needed, turn on the enable

1. Host setups the desired XRAM address:

Port 0x381 = high byte of XRAM address

Port 0x382 = low byte of XRAM address

2. And then the host can access the content/data via Port 0x383.

nd

3. If the 2

Port 0x385 = high byte of XRAM address

Port 0x386 = low byte of XRAM address

Port 0x387 = content/data of XRAM address

Index-I/O required.

4.13.6 Extended I/O Port (Debug Port, Port80)

Developers may use legacy I/O port, 0x80 for debug. The KBC provides a debug

interface for this application, called extended I/O port (debug port). The port address can be

programmable in the KBC. The host software can use this interface not only for debug but also for

special communication with the EC F/W. This interface provides interrupt capability as well. That is,

while host accesses this I/O port, an interrupt to 8051 occurs. There is one thing should be reminded.

The interrupt feature is only for I/O-write to this port, not for I/O-read. Please note, the interrupt

capability is controlled in the register ECCFG[2] (0xFF04[2]).

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4.13.7 LPC Registers Description

LPC SIRQ Configuration for Quiet Mode

Offset Name Bit Type Description Default Bank

0x90 LPCSCFG 7-6

R/W LPC Register Bank Switch

Registers, 0xFE91~0xFE9F, are mapping to 2 banks.

00: Bank 0 01: Bank 1 10: Reserved 11: Reserved

nd

R/W Enable 2

5

R/W Switch of CIR/User-defined IRQ

4

Switch between CIR and User defined SIRQ, and the SIRQ channel is defined in LPCTCFG[3:0]

0: User defined SIRQ 1: CIR SIRQ (Any one from CIRPF [3:0],FEC2h )

R/W Memory size 4MB enable (LPC/FWH).

3

If this bit enable, please make sure LPCFWH[7:6]=00b

0: Disable 1: Enable

R/W LPC I/O 2Eh/2Fh decode enable.

2

If enabled, 0xFE9A/0xFE9B are configured to take in charge of LPC I/O 2Eh/2Fh.

0: Disable 1: Enable

Ro LPC SIRQ mode

1

0: Continuous mode 1: Quiet mode

WO Force LPC SIRQ cycle start.

0

Writing “1” to this bit forces SIRQ signal low for a pulse.

index-I/O mode

0x20 0xFE

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Datasheet KB3930QF Datasheet (Ene)

Specifications and Main Features

Frequently Asked Questions

User Manual