The KB2514 is a very high frequency video amplifier &
wide range OSD processor 1 chip system with I2C Bus
control used in monitors. It contains 3 matched R/G/B video
amplifiers with OSD processor and provides flexible
interfacing to I2C Bus controlled adjustment systems.
FUNCTIONS
•R/G/B video amplifier
•OSD processor
•I2C bus control
•Cut-off brightness control
•R/G/B sub contrast/cut-off control
•Half tone
FEATURES
VIDEO AMP PART
32-DIP-600A
ORDERING INFORMATION
DevicePackageOperating Temperature
KB251432-DIP-600A-20 °C − +75 °C
•3-channel R/G/B video amplifier, 150MHz @f-3dB
•I2C bus control items
- Contrast control: -38dB
- Sub contrast control for each channel: -12dB
- Brightness control
- OSD contrast control: -38dB
- Cut-off brightness control (AC coupling)
- Cut-off control for each channel (AC coupling)
- Switch registers for SBLK and video half tone and
CLP/BLK polarity selection and INT/EXT CLP selection
•Built in ABL (automatic beam limitation)
•Built in video input clamp, BRT clamp
•Built in video half tone (3mode) function on OSD
pictures
•Capable of 8.0Vp-p output swing
•Improvement of rise & fall time (2.2ns)
•Cut-off brightness control
•Built in blank gate with spot killer
•Clamp pulse generator
•OSD intensity
•BLK, CLP polarity selection
•Clamp gate with anti OSD sagging
•Built in 1K-byte SRAM
•256 ROM fonts (each font consists of 12 × 18
dots.)
•Full screen memory architecture
•Wide range PLL available (15kHz ~ 90kHz,
Reference 800 X 600)
•Programmable vertical height of character
•Programmable vertical and horizontal
positioning
•Character color selection up to 16 different
colors (in a units of character)
•Programmable background color (up to 16
colors)
•Character blinking and shadowing
•Character scrolling
•72MHz pixel frequency from on-chip PLL
(Reference 800 X 600)
•Full white pattern generation function
1
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Preliminary
KB2514 VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
BLOCK DIAGRAM
6
VDDA
VDD
VSS
VCC3
GND3
VREF1
VREF
ABL
CONT_CAP
RIN
GND1
VCC1
31
28
11
12
15
13
9
4
5
8
7
R OSD
ROM
(448 x 18 x 12)
Font Data
Output Stage
Band
Gap.Ref
ABL
Video
Input
Clamp
CLP
OSD
Input
Cilp.
HT DET.
12
R/G/B OSD
FBLK
Intensity
Multi (3 mode)
Half Tone
Video
Half Tone
SW
OSD
Half Tone
SW
FBLKI2C
916
ROM
Address
Display Ctrl
H/V/CLK Ctrl
Timing Controller
I2CFBLK
(480 x 16)
Ctrl Font
Controller
Sub
Cont.
Control
OSD
Cont.
Control
ROM
Display
H/V/CLK Ctrl
RGB OSD
FBL
INTE
HT DET.
I2C
I2C
RAM Data
Frame Ctrl
ROM Ctrl
Frame Ctrl
ROM Ctrl
BLK
CLP
Video
Contrast
Control
Register
BLK
Int
Clamp
Pulse
Gen.
+
I2C Cont. Cntl
Data Receiver
16Ctrl Data
CLK
H_Pulse
V_Pulse
Latches
I2C bus
decoder
D/A
R cut off
G cut off
HFLB
B cut off
Sub
Cont.
Control
OSD
PLL
Amp
Out
Birght
Control
CLPI2C
V/I
V/I
V/I
BLK
2
VSSA
32
HFLB
1
VFLB
3
VCO_IN_P
30
SDA
SCL
29
27
RCT
26
GCT
25
BCT
10
CLP_IN
24
R OUT
22
VCC2
23
R CLP
GND2
19
GIN
14
20
G CLP
G-CHANNEL
21
BIN
G OSD
CLPHT DET. FBLKCLPBLKI2C
16
17
G OUT
B CLP
B-CHANNEL
18
B OSD
CLPHT DET. FBLKCLPBLKI2C
B OUT
Figure 1. Functional Block Diagram
2
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Preliminary
VIDEO AMP MERGED OSD PROCESSOR FOR MONITORSKB2514
PIN CONFIGURATION
1
VFLB
VSSA
2
VCO_IN_P
3
4
VREF1
5
VREF
6
VDDA
CONT_CAP
7
ABL_IN
8
9
GND3
CLP_IN
10
VCC3
11
KB2514
KB2502
HFLB
VDD
SDA
SCL
VSS
RCT
GCT
BCT
ROUT
RCLP
VCC2
32
31
30
29
28
27
26
25
24
23
22
12
13
14
15
16
RIN
VCC1
GIN
GND1
BIN
Figure 2. Pin Configuration
GOUT
GCLP
GND2
BOUT
BCLP
21
20
19
18
17
3
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Preliminary
KB2514 VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
Table 1. Pin Configuration
Pin No.SymbolI/OConfiguration
1VFLBIVertical flyback signal
2VSSA-Ground (PLL part)
3VCO_IN_PI
4VREF1OCharge pump output
5VREFOPLL regulator filter
6VDDA-+5V supply voltage for PLL part
7CONT_CAP-Contrast control for AMP part
8ABL-Auto beam limit.
9GND3-Ground for video AMP part(for AMP control)
10CLP_IN-Video clamp pulse input
11VCC3-+12V supply voltage for video AMP part(for AMP control)
12RINIVideo signal input (red)
13VCC1-+12V supply voltage for video AMP(for main video signal process)
14GINIVideo signal input (green)
15GND1-Ground for video AMP part(for main video signal process)
16BINIVideo signal input (blue)
17BCLP-B output clamp cap
18BOUTOVideo signal output (blue)
This voltage is generated at the external loop filter and goes into the
input stage of the VCO.
19GND2-Ground for video AMP part(for video output drive)
20GCLP-G output clamp cap
21GOUTOVideo signal output (green)
22VCC2-+12V supply voltage for video AMP part(for video output drive)
23RCLP-R output clamp cap
24ROUTOVideo signal output (red)
25BCT-B cut-off output
26GCT-G cut-off output
27RCT-R cut-off output
28VSS-Ground for digital part
29SCLI
30SDAI/O
31VDD-+5V supply voltage for digital part
32HFLBIHorizontal flyback signal
Serial clock (I2C)
Serial data (I2C)
4
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VIDEO AMP MERGED OSD PROCESSOR FOR MONITORSKB2514
PIN DESCRIPTION
Table 2. Pin Description
Pin NoPin NameSchematicDescription
1
32
3
4
5
VFLB
HFLB
VCO_IN_P
VPEF1
VREF
7Contrast cap
(CONT_CAP)
VFLB
HFLB
4.0K
FLB signal is in TTL level
Multi polarity input
PLL loop filter output
BandGap ref. output
Contrast cap range
(0.1uF ~ 5uF)
VrefI2C Data
100µA
8ABL_IN
100K
2K
VCC
ABL input DC range
(1 ~ 4.5V)
VrefVref
250µA
5
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Preliminary
KB2514 VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
Table 2. Pin Description (Continued)
Pin NoPin NameSchematicDescription
10CLP_INMulti polarity input
VCC
50K
Clamp gate pulse TTL level
input
10K
12
14
Red video input
(RIN)
Green video input
VCC
Max input video signal is 0.7
Vpp
VCC
(GIN)
16
Blue video input
(BIN)
Video_In
0.2K
17
20
23
Blue (B clamp cap)
Green (G clamp cap)
Red (R clamp)
0.2K
0.2K
12K
Brightness controlling actives by
charging and discharging of the
external cap. (0.1µF)
(During clamp gate)
CLP
Iclamp
6
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Preliminary
VIDEO AMP MERGED OSD PROCESSOR FOR MONITORSKB2514
Table 2. Pin Description (Continued)
Pin NoPin NameSchematicDescription
18
21
24
27
26
25
Blue video output
(BOUT)
Green video output
(GOUT)
Red video output
(ROUT)
Red cut-off control
(RCT)
Green cut-off control
(GCT)
Blue cut-off control
(BCT)
VCC
0.05K
0.5K
0.04K
Isink
0-600uA 0-200uA 50uA 100uA
Video_Out
0.2K
Video signal output
Cut-off control output
CTX
29SCL
30SDA
SCL
SDA
SCL
Serial clock input port of I2C bus
Serial data input port of I2C bus
ACK
7
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Preliminary
KB2514 VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
ABSOLUTE MAXIMUM RATINGS
(see 1)
(Ta = 25 °C)
Table 3. Absolute Maximum Ratings
Value
NoItemSymbol
MinTypMax
1Maximum supply voltage
2
Operating temperature
(see 2)
V
CC
V
DD
Topr-20-75°C
--13.2
--6.5
3Storage temperatureTstg-65150°C
4Operating supply voltage
V
V
5Power dissipationP
CCop
DDop
D
11.412.012.6
4.755.005.25
--W
THERMAL & ESD PARAMETER
Table 4. Thermal & ESD Parameter
Unit
V
V
(see 3)
NoItemSymbol
Value
MinTypMax
Thermal resistance
1
(junction-ambient)
θja-48-°C/W
2Junction temperatureTj-150-°C
Human body model
3
(C = 100p, R = 1.5k)
Machine model
4
(C = 200p, R = 0)
HBM2--KV
MM300--V
5Charge device modelCDM800--V
Unit
8
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Preliminary
VIDEO AMP MERGED OSD PROCESSOR FOR MONITORSKB2514
ELECTRICAL CHARACTERISTICS
DC ELECTRICAL CHARACTERISTICS
(Tamb = 25 °C, VCC = 12V, VDD = V
= 5V, ABL input voltage = 5V, HFLB input signal = S3, load resistors =
DDA
470Ω, except OSD part current 35mA, unless otherwise stated)
Maximum supply currentICC maxVCC = 12.6V105130140mA
ABS supply currentICC absVCC = 13.2V--175mA
Video input bias voltageV bias1.82.12.4V
Video black level voltage (POR)V blackpor1.201.501.80V
Black level voltage channel difference (POR)∆ V blackpor
Video black level voltage (FFH)V blackff
Black level voltage channel difference (FFH)∆ V blackff∆ 10--%
Video black level voltage (00H)V black0004 = 00H-0.20.5V
Black level voltage channel difference (00H)∆ V black00∆ 10--%
Spot killer voltageVspotVCC = Var.9.2010.411.2V
(see 4)
(see 5)
04 = FFH
(see 13)
MinTypMax
100125130mA
∆ 10--%
Value
2.22.73.2V
Unit
Cut-off current (FFH)ICTffPin25, 26, 27 = 12V
09 ~ 0B: FFH
0C: 00H
Cut-off current (00H)ICT00Pin25, 26, 27 = 12V
09 ~ 0C: 00H
Cut-off brightness current (FFH)ICTBRTffPin25, 26, 27 = 12V
09 ~ 0B: 00H
0C: FFH
Cut-off brightness current (80H)ICTBRT80Pin25, 26, 27 = 12V
09 ~ 0B: 00H
0C: 80H
Cut-off offset current 1ICS1Pin25, 26, 27 = 12V
09 ~ 0C: 00H
0E: 11H
500625750µA
-2.05.0µA
100180260µA
5090130µA
255075µA
9
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Preliminary
KB2514 VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
Table 5. DC Electrical Characteristics (Continued)
ParameterSymbolConditions
Value
MinTypMax
Cut-off offset current 2ICS2Pin25, 26, 27 = 12V
50100130µA
09 ~ 0C: 00H
0E: 12H
Soft BLK output voltageVsblk0D: 80H
-0.20.5V
0E: 14H
Clamp cap voltage (POR)Vcap6.0 7.08.0V
Total external cut-off current range
Red
cut-off
Creen
cut-off
Blue
cut-off
600uA
Unit
Cut-Off Brightness
Cut-Off Offset
Switch
CS2
CS1
200uA
100uA
50uA
150uA
10
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Preliminary
VIDEO AMP MERGED OSD PROCESSOR FOR MONITORSKB2514
AC ELECTRICAL CHARACTERISTICS
(Tamb = 25 °C, VCC = 12V, VDD = V
470Ω, Vin = 0.7Vpp manually adjust video output pins 18, 21 and 24 to 4V DC for the AC test
otherwise stated
(see 12)
)
= 5V, ABL input voltage = 5V, HFLB input signal = S3, load resistors =
RGB input = S1
Contrast max. - Center attenuationCC = 20log (Vc80/Vcff)-8-6-4dB
Sub contrast center output voltageVd8003 = FFH
Sub contrast center output channel
difference
∆ Vd80∆ 10--%
04 ~ 0C = 80H
RGB input = S1
Sub contrast min. output voltageVd0003 = FFH, 05 ~ 07: 00H
Sub contrast min. output channel difference∆ Vd00∆ 10--%
04, 08 ~ 0C = 80H
RGB input = S1
Sub contrast max. - min. attenuationDD = 20log (Vd00/Vcff)-14-12-10dB
ABL control rangeABL
R/G/B video rising time
R/G/B video falling time
(see 7)
(see 7)
R/G/B blank output rising time
R/G/B blank output falling time
R/G/B video band width
(see 7, 8)
(see 7)
(see 7)
tr (video)03, 05 ~ 07: FFH
tf (video)-2.22.8ns
tr (blank) POR
tf (blank)-8.015.0ns
f (-3dB)
Video AMP 50MHz cross talkCT_50M
(see7, 9)
(see 15)
04, 08 ~ 0C: 80H
RGB input = S2
HFLB: S4
(see 16)
(see 17)
-12-10-8dB
150--MHz
Value
5.05.76.4Vpp
2.52.853.2Vpp
2.32.62.9Vpp
1.31.61.9Vpp
-2.22.8ns
-6.012.0ns
--25-20dB
Unit
Video AMP 130MHz cross talkCT_130M
(see7, 9)
Absolute gain matchAvmatch
Gain change between amplifierAvtrack
(see 6)
(see 7)
(see 18)
--15-10dB
-1-1dB
-1-1dB
11
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Preliminary
KB2514 VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
OSD ELECTRICAL CHARCTERISTICS
(Tamb = 25 °C, VCC = 12V, VDD = V
= 5V, HFLB input voltage = S3, load rosistors = 470Ω, V-AMP test
05 ~ 08: FFH
0D: 0FH
OSD white condition input
HTosd = 20log (V
htvideo/Vcff
htosd/Vocff
MinTypMax
-6.0-4.5-3.0dB
)
-7.0-5.5-4.0dB
)
Value
5.46.47.4Vpp
2.73.23.7Vpp
Unit
12
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Preliminary
VIDEO AMP MERGED OSD PROCESSOR FOR MONITORSKB2514
OPERATION TIMINGS
Table 8. Operation Timings
Parameter SymbolMinTypMaxUnit
Input Signal HFLB, VFLB
Horizontal flyback signal frequencyf
Vertical flyback signal frequencyf
I2C Interface SDA, SCL (Refer to Figure 3)
SCL clock frequency f
Hold time for start conditiont
Set up time for stop conditiont
Low duration of clockt
High duration of clockt
Hold time for datat
Set up time for datat
Time between 2 accesst
Fall time of SDAt
Rise time of both SCL and SDAt
HFLB
VFLB
SCL
hs
sus
low
high
hd
sud
ss
fSDA
rSDA
--120kHz
--200 Hz
--300kHz
500--ns
500--ns
400--ns
400--ns
0--ns
500--ns
500--ns
--20ns
---ns
SDA
SCL
ths
tsud
thigh
tss
tlow
Figure 3. I2C Bus Timing Diagram
thd
tsus
13
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Preliminary
KB2514 VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
OSD PART ELECTRICAL CHARACTERISTICS
OSD PART DC ELECTRICAL CHARACTERISTICS
(Ta = 25 °C, V
= VDD = 5V)
DDA
Table 9. OSD Part DC Electrical Characteristics
Parameter SymbolMinTypMaxUnit
Supply voltageV
Supply current
(no load on any output)
Input voltageV
Output voltage
(lout = ±1mA)
Input leakage currentI
VCO input voltageV
I
DD
V
V
V
VCO
DD
IH
IL
OH
OL
IL
4.755.005.25V
--25mA
0.8V
DD
--V
--VSS + 0.4V
0.8V
DD
--V
--VSS + 0.4V
-10-10µA
2.5V
14
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Preliminary
VIDEO AMP MERGED OSD PROCESSOR FOR MONITORSKB2514
NOTES:
1.Absolute maximum rating indicates the limit beyond which damage to the device may occur.
2.Operating ratings indicate conditions for which the device is functional but do not guarantee specific performance limits.
For guaranteed specifications and test conditions, see the electrical characteristics. The guaranteed specifications apply
only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under
the listed test conditions.
3.VCC supply pins 11, 13, and 22 must be externally wired together to prevent internal damage during VCC power on/off
cycles.
4.The supply current specified is the quiescent current for VCC1/VCC2 and VCC3 with RL = ∞, The supply current
for VCC2 (pin 22) also depends on the output load.
5.Output voltage is dependent on load resistor. Test circuit uses RL = 470Ω
6.Measure gain difference between any two amplifiers Vin = 700mVpp.
7.When measuring video amplifier bandwidth or pulse rise and fall times, a double sided full ground plane printed circuit
board without socket is recommended. Video amplifier 50MHz cross talk test also requires this printed circuit board. The
reason for a double sided full ground plane PCB is that large measurement variations occur in single sided PCBs.
8.Adjust input frequency from 10MHz (AV max reference level) to the -3dB frequency (f -3dB).
9.Measure output levels of the other two undriven amplifiers relative to the driven amplifier to determine channel separation.
Terminate the undriven amplifier inputs to simulate generator loading. Repeat test at fin = 50MHz for cross talk 50MHz.
10. A minimum pulse width of 200 ns is guaranteed for a horizontal line of 15kHz. This limit is guaranteed by design. if a lower
line rate is used a longer clamp pulse may be required.
11. During the AC test the 4V DC level is the center voltage of the AC output signal. For example. If the output is 4Vpp the
signal will swing between 2V DC and 6V DC.
12. These parameters are not tested on each product which is controlled by an internal qualification procedure.
13. The conditions block’s 03, 04, 05... etc. signify sub address’ 0F03, 0F04, 0F05... etc.
14. Sub address 0F03, 0F05 ~ 0F07: FFH
0F04, 0F08 ~ 0F0C: 80H
RGB input = S1,
When the ABL input voltage is 0V, the R/G/B’s output voltage is VR/VG/VB and uses the formula ABLR = 20log (VR/V
15. OSD TST mode = High, CLP operation off,
RGB input = S5 (frequency sweep),
RGB input clamp cap = 2.1V DC,
RGB clamp cap (pin 23/20/17) = Vcap voltage (7.0V),
S5’s frequency 1MHz → 130MHz sweep, -3dB point = 20log (V
130MHz/V1MHz
)
03, 05 ~ 07: FFH
04, 08 ~ 0C: 80H
0F: 80H
16. OSD TST mode = High, CLP operation off,
RGB input clamp cap = 2.1V DC,
RGB clamp cap (pin 23/20/17) = Vcap voltage (7.0V),
03, 05 ~ 07: FFH
04, 08 ~ 0C: 80H
0F: 80H
R input = S5 (50MHz)
CT_50M = 20log (V
outG/VoutR
) or 20log (V
outB/VoutR
)
17. OSD TST mode = High, CLP operation off,
RGB input clamp cap = 2.1V DC,
RGB clamp cap (pin 23/20/17) = Vcap voltage (7.0V),
03, 05 ~ 07: FFH
04, 08 ~ 0C: 80H
0F: 80H
R input = S5 (130MHz)
CT_150M = 20log (V
outG/VoutR
) or 20log (V
outB/VoutR
)
cffR
)
15
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Preliminary
KB2514 VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
TEST SIGNAL FORMAT
Table 10. Test Signal Format
Signal
Name
S1Video gain measurement
[V]
S2Video Tr/Tf measurement
[V]
S3HFLB (posi & nega.) input
[V]
Video
4uS
f = 200kHz
Input Signal FormalSignal Description
Video = 1MHz/0.7Vpp
Sync = 50kHz
Sync
[t]
f = 200kHz
V = 0.7Vpp
Duty = 50%
Duty = 50%
t = 2uS
0.7
Vpp
[t]
f = 50kHz
t = 2uS
V = 0V/5V
f = 50kHz
S4OSD level measurement
[V]
[V]
f = 200kHz
S5Crosstalk test
[V]
Duty = 50%
[t]
5V
0V
[t]
Vi
[t]
Blank Tr/Tf measurement
f = 50kHz
V = 0V/5V
Bandwidth measurement
1MHz/10MHz/50MHz/
Vref
130MHz
Vref = input clamp voltage
Vi = 0.7Vpp
•S1, S2 signal’s low level must be synchronized with the S3 signal’s sync. term.
•The input signal level uses the IC pin as reference.
16
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Preliminary
VIDEO AMP MERGED OSD PROCESSOR FOR MONITORSKB2514
TEST CIRCUIT
VDD = 5.0V
ABL
1MΩ
BNC1
100u
BNC6
BNC2
33pF
33
10uF5.6K
1u
100u
33
33
27K
1u
100
1
2
SW1
1
VFLB
2
VSSA
3
VCO_IN_P
4
VREF1
5
VREF
6
VDDA
7
CONT_CAP
8
ABL_IN
9
GND3
10
CLP_IN
KB2514
HFLB
VDD
SDA
SCL
VSS
RCT
GCT
BCT
ROUT
RCLP
32
31
30
29
28
27
26
25
24
23
0.1u
33
33
33
2K
2K
2K
100u
BNC3
4.7K
BNC5
4.7K
BNC5
470
BNC7
BNC8
BNC9
75
75
75
0.1u
0.1u
0.1u
100u
11
12
13
14
15
16
VCC3
RIN
VCC1
GIN
GND1
BIN
Magnetic core
Figure 4. Test Circuit
VCC2
GOUT
GCLP
GND2
BOUT
BCLP
22
470
21
0.1u
20
19
470
18
0.1u
17
VSS = 12.0V
17
Page 19
Preliminary
KB2514 VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
FUNCTIONAL DESCRIPTIONS
DATA TRANSMISSION
The interface between KB2514 and MCU follows the I2C protocol. After the starting pulse, the transmission takes
place in the following order: Slave address with R/W bit, 2-byte register address, 2-byte data, and stop condition.
an acknowledge signal is received for each byte, excluding only the start/stop condition. The 2-byte register
address is composed of an 8-bit row address, and an 8-bit column address. The order of transmission for a 2-byte
register address is 'Row address → Column address'. The 2 bytes of data is because KB2514 has a 16-bit base
register configuration. KB2514's slave address is BAh. It is BBh in read mode, and BAh in write mode.
•Address Bit Pattern for Display Registers Data
(a) row address bit pattern
R3 - R0: Valid data for row address
A15A14A13A12A11A10A9A8
XXXXR3R2R1R0
(b) Column address bit pattern
C4 - C0: Valid data for column address
A7A6A5A4A3A2A1A0
XXXC4C3C2C1C0
X:Don't care bit
•Data Transmission Format
Start → Slave address → ACK → Row address → ACK → Column address → ACK
Data byte N → ACK → Data byte N+1 → ACK → Stop
Figure 5. Data Transmission Format at Writing Operation
Preliminary
KB2514 VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
MEMORY MAP
27 2829
Row
Row
Row
Row
Row
Row
Row 16
00 01
00
01
12
13
14
15
00 010203
0001 0203 0405
02
Character & Attribute Registers [Display RAM]
(30 x15 Character Display)
Frame Control Registers
Video-AMP Control Registers
Figure 9. Memory Map of Display Registers
The display RAM's address of the row and column number are assigned in order. The display RAM is composed of
3 register groups (character & attribute register, frame control register and V-AMP control register).
The display area in the monitor screen is 30 column × 15 row, so the related character & attribute registers are also
30 column × 15 row. Each register has a character address and characteristics corresponding to the display
location on the screen, and one register is composed of 16 bits. The lower 8 bits select the font from the 256 ROM
fonts, and the upper 8 bits give font characteristics to the selected font.
The frame control registers are in the 16th row. It controls OSD's display location, character height and scroll in
units of frame.
The V-AMP control registers are also located in the 17th row.
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Preliminary
Character & Attribute Register: Row00 ~ 14, Column00 ~ 29
Character code address
This is the address of 256 ROM fonts.
Character color
The character color is chosen from 16 colors using these 3 bits and the
frame control register 3’s CINT bit.
Raster color is determined by these bits.
The raster color is chosen from out of 16 colors using these 3 bits and the
frame control register 3’s RINT bit.
Character shadowing / CTL0(Extended Code)
If you set the frame control register 0’s EX-EN bit to '0', this bit carries out
character shadowing feature.( If SHA bit is '1', the character shadowing is
shown)
If you set the frame control register 0’s EX-EN bit to '1', this bit is used for
extended code.
Character blinking / CTL1(Extended Code)
If you set the frame control register 0’s EX-EN bit to '0', this bit carries out
character blinking feature.( If Blink bit is '1', the character blinking feature is
shown)
If you set the frame control register 0’s EX-EN bit to '1', this bit is used for
extended code.
If you set the Frame Control Register 0’s 'EX-EN' bit as '1', the Character & Attribute Register’s 'SHA' and 'Blink'
bits are used to call the Extended Code.
In other words, the combination of SHA and Blink bits can call four kind Extended Code 'CTL00', 'CTL01',
'CTL10' and 'CTL11', the CINT, RINT, SHA and Blink features can be carried out in a unit of character fonts.
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Table 11. Register Description (Continued)
RegistersBitsDescription
Frame Control
Registers - 0
(Row15,
Column00)
EN
(Bit 0)
Erase
(Bit 1)
OSD enable
OSD is enabled when this bit is '1'. In other words, if this bit isn't '1'OSD is
not output inspite of writing control data. We recommend that you enable
the OSD after setting the control registers (such as the character & attribute
register) because of video and OSD output timing.
RAM erasing
If this bit is '1', the RAM data (character & attribute registers) is erased. The
time spent in carrying out this operation is called erasing time, which can be
calculated as follows.
Erasing time = RAM clock × 480 (RAM cell no.)
RAM clock = 12 dot clock
Dot clock = 1/(dot frequency)
Dot frequency = Horizontal frequency × resolution (mode)
Therefore, the maximum erasing time value is:
BliT
(Bit 2)
BliEN
(Bit 3)
ScrT
(Bit 4)
ScrEN
(Bit 5)
BGEN
(Bit 6)
EX-EN
(Bit 7)
FullW
(Bit 8)
(Erasing Time)
= (12 × 480) / (15k × 320) = 1.2ms
MAX
Blink time control
If this bit is '1', blink time is 0.5sec, and if not, 1sec.
Blinking enable
Blinking effect is controlled by this bit.
If this bit is ’1’, blinking effect is enabled.
If this bit is '0', a full OSD screen blinking effect is disabled.
Scroll time control
If this bit is '1', scroll time is 0.5sec, and if not, 1sec.
Scroll enable
Scrolling effect is controlled by this bit. If this bit is '1', scrolling effect is
enabled. You must remember that scrolling can be turned on/off only when
OSD is enabled/disabled.
Back ground enable
If the BGEN bit is '1' and the raster color is black, the raster is transparent.
That is, the video back ground is shown. If not, the OSD raster covers the
video’s back ground. Refer to other color effect.
Extended code enable
If the EX-EN bit is '1', the Character & Attribute register’s Blink, SHA bits
carry out Extended Code features instead of Blink and SHA features.
Full white pattern enable
If the FullW bit is '1', the full white pattern is displayed in the screen.
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Table 11. Register Description (Continued)
RegistersBitsDescription
Frame Control
Registers - 1
(Row15,
Column01)
CH5 ~ CH0
(Bit 5 ~ 0)
VPOL
(Bit 6)
HPOL
(Bit 7)
dot1, dot0
(Bit 9, 8)
Character height control
While the purpose of VZ[1:0] (vertical character height) is to control the
absolute size of the character, the purpose of CH[5:0] (Character Height) is
to output OSD of a uniform size even if the resolution changes. If you adjust
the value in the range of CH = 18 ~ CH = 63, each line's repeating number
is decided (standard height CH = 18 is the reference value), by which the
line is repeated. For more information on repeating number selection, refer
to character height.
Polarity of vertical fly back signal
If this bit is '1', VFLB's polarity is positive, and if '0', it is negative. In other
words, this bit is set to '1' if active high, and '0' if active low.
Polarity of horizontal fly back signal
If this bit is '1', HFLB's polarity is positive, and if '0', it is negative. In other
words, this bit is set to '1' if active high, and '0' if active low.
As shown above, the number of dots per horizontal line is decided by a
combination of these two bits.
Horizontal frequency
PLL's horizontal frequency is decided by the combination of these 3 bits.
This is related to the selection of DOT[1:0], so you can't numerically
express the frequency range with only the HF[2:0] selection. For more
information, please refer to HF Bits Selection.
Full range PLL
If this bit is '1', the OSD_PLL block's VCO operates at full range (4.8MHz -
96MHz). If it is '0', it operates within the region decided by the HF bit [C:A]
explained above. if you can’t optimize OSD screen decided by the HF bit in
the high region, you may set the FPLL bit to '1'.
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Table 11. Register Description (Continued)
RegistersBitsDescription
Frame Control
Registers - 1
(Row15,
Column01)
The purpose of bits 'HPOL', and 'VPOL' is to provide flexibility when using the KB2514 IC. No matter which polarity
you choose for the input signal, the IC will handle them identically, so you can select active high or active low
according to your convenience.
CP1, CP0
(Bit F, E)
Charge pump output current control
This is the PLL block's internal phase detector output status, converted into
current. Refer to PLL control.
CP1CP0Charge Pump Current
000.50 mA
010.75 mA
101.00 mA
111.25 mA
The output is decided by the combination of these two bits.
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Tabel 4. Register Description (Continued)
RegistersBitsDescription
Frame Control
Registers - 2
(Row 15,
Column 02)
Frame Control
Registers - 3
(Row 15,
Column 03)
VP7 ~ VP0
(Bit 7 ~ 0)
HP7 ~ HP0
(Bit F ~ 8)
CTL 00
(Bit 3 ~ 0)
CTL 01
(Bit 7 ~ 4)
CTL 10
(Bit B ~ 8)
Vertical start position control ( = VP[7:0] × 4)
Signifies top margin height from the V-Sync reference edge.
Horizontal start position control ( = HP[7:0] × 6)
Signifies delay of the horizontal display from the H-Sync reference edge to
the character's 1st pixel location.
Extended code
In case the EX-EN bit is '1' and the Character & Attribute register’s E and F
bits are '0', these bits have meanings.
If you set the CINT(character color intensity) bit '1', the character color
intensity feature is carried out.
If you set the RINT(raster color intensity) bit '1', the raster color intensity
feature is carried out.
If you set the SHA(character shadowing) bit '1', the character shadowing
feature is carried out.
If you set the Blink(character blinking) bit '1', the character blinking feature
is carried out.
Extended code
In case the EX-EN bit is ’1’ and the Character & Attribute register’s E bit is
'1' and F bit is '0', these bits have meanings.
If you set the CINT(character color intensity) bit '1', the character color
intensity feature is carried out.
If you set the RINT(raster color intensity) bit '1', the raster color intensity
feature is carried out.
If you set the SHA(character shadowing) bit '1', the character shadowing
feature is carried out.
If you set the Blink(character blinking) bit '1', the character blinking feature
is carried out.
Extended code
In case the EX-EN bit is '1' and the Character & Attribute register’s E bit is
'0' and F bit is '1', these bits have meanings.
If you set the CINT(character color intensity) bit '1', the character color
intensity feature is carried out.
If you set the RINT(raster color intensity) bit '1', the raster color intensity
feature is carried out.
If you set the SHA(character shadowing) bit '1', the character shadowing
feature is carried out.
If you set the Blink(character blinking) bit '1', the character blinking feature
is carried out.
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Tabel 4. Register Description (Continued)
RegistersBitsDescription
Frame Control
Registers - 3
(Row 15,
Column 03)
CTL 11
(Bit F ~ C)
Extended code
In case the EX-EN bit is '1' and the Character & Attribute register’s E and F
bits are '1', these bits have meanings.
If you set the CINT(character color intensity) bit '1', the character color
intensity feature is carried out.
If you set the RINT(raster color intensity) bit '1', the raster color intensity
feature is carried out.
If you set the SHA(character shadowing) bit '1', the character shadowing
feature is carried out.
If you set the Blink(character blinking) bit '1', the character blinking feature
is carried out.
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Tabel 4. Register Description (Continued)
RegistersBitsDescription
V-AMP Control
Registers - 0
(Row 16,
Column 00)
V-AMP Control
Registers - 1
(Row 16,
Column 01)
V-AMP Control
Registers - 2
(Row 16,
Column 02)
V-AMP Control
Registers - 3
(Row 16,
Column 03)
V-AMP Control
Registers - 4
(Row 16,
Column 04)
VC7 ~ VC0
(Bit7 ~ 0)
BRT7 ~ BRT0
(BitF ~ 8)
RSB7 ~ RSB0
(Bit7 ~ 0)
GSB7 ~ GSB0
(BitF ~ 8)
BSB7 ~ BSB0
(Bit7 ~ 0)
OSD7 ~ OSD0
(BitF ~ 8)
RWB7 ~ RWB0
(Bit7 ~ 0)
GWB7 ~ GWB0
(BitF ~ 8)
BWB7 ~ BWB0
(Bit7 ~ 0)
CUT7 ~ CUT0
(BitF ~ 8)
The contrast adjustment is made by contrdling simultaneously the gain
of three internal variable gain amplifiers.
The contrast adjustment allows to cover a typical range of 38dB.
The brightness adjustment controls to add the same black level
(pedestal) to the 3-channel R/G/B signals after contrast amplifier.
R channel SUB contrast control.
The SUB contrast adjustment is used to adjust the white balance, and
the gain of each channel is controlled.
The SUB contrast adjustment allows you to cover a typical tange of
12dB.
G channel SUB contrast control.
The SUB contrast adjustment is used to adjust the white balance, and
the gain of each channel is controlled.
The SUB contrast adjustment allows you to cover a typical tange of
12dB.
B channel SUB contrast control.
The SUB contrast adjustment is used to adjust the white balance, and
the gain of each channel is controlled.
The SUB contrast adjustment allows you to cover a typical tange of
12dB.
The OSD contrast adjustment is made by contrdling simultaneously the
gain of three internal variable gain amplifiers.
The OSD contrast adjustment allows to cover a typical range of 38dB.
R channel cut-off control.
The cut-off adjustment is used to adjust the raster white balance.
G channel cut-off control.
The cut-off adjustment is used to adjust the raster white balance.
B channel cut-off control.
The cut-off adjustment B used to adjust the raster white balance.
The cut-off brightness adjustment is made by simultaneously controlling
the external cut-off current.
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Tabel 4. Register Description (Continued)
RegistersBitsDescription
V-AMP Control
Registers - 5
(Row 16,
Column 05)
HT
(Bit 0)
HG1 ~ HB1
(Bit3 ~ 1)
Video & OSD half tone enable.
If you set this bit to '1', the half tone function is on.
Then you can see the video signal & OSD raster.
HG1 ~ HB1 bits select OSD raster color 1 to be half tone.
To carry out half tone function, set the HT bit to '1'.
Polarity of horizontral fly back signal
If this bit is '0', HFLB’s polarity is negative, and if '1', it is positive.
Polarity of clamp pulse signal
If this bit is '0', CLP’s polarity is positive, and if '1', it is negative.
This bit has meaning only if the CLPS bit is set to '1'.
Clamp pulse generation enable
If this bit is '0', clamp signal is made using the HFLB signal, so there is
no need to supply the clamp signal.
and if '1' you must supply external clamp signal.
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VIDEO AMP PART ADDRESS MAP
Register sub address
Table 12. Video AMP Part Address Map
SUB
Address
FEDCBA9876543210
FunctionPOR
[Hex]
1000Brightness controlContrast control
1001SUB contrast control (G)SUB contrast control (R)
1002OSD contrast controlSUB contrast control (B)
1003Cut-off control (G)Cut-off control (R)
1004Cut-off brightness controlCut-off control (B)
1005
HexB7B6B5B4B3B2B1B0Cut-Off Brightness (µA)Int. Value (Hex)
00000000000
8010000000100O
FF11111111200
Increment/bit0.781
Cut-Off Register (R/G/B-ch) (SUB ADRS: 03/04H)
(cont = 80H, subcont: 80H)
HexB7B6B5B4B3B2B1B0Cut-Off EXT (µA)Int. Value (Hex)
00000000000
8010000000300O
FF11111111600
Increment/bit2.344
Gain
(dB)
Int. Value
(Hex)
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KB2514 VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
ADDRESSING
•ROM Fonts
KB2514 provides 256 Rom fonts for displaying OSD Icons, which allows the use of multi-language OSD Icons.
Font $000 is reserved for blank data.
01EF
$000$001$00E$00F
00
$010$011$01E$01F
01
Fonts
$0E0$0E1$0EE$0EF
0E
$0F0$0F1$0FE$0FF
0F
Figure 11. Composition of the ROM Fonts
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VIDEO AMP MERGED OSD PROCESSOR FOR MONITORSKB2514
COLORING
If you have an Intensity feature, the number of possible colors you can express becomes doubled. In other words,
the number of colors you can represent with three colors blue, green, and red is 8 ( = 23), but with the intensity
feature, it is 16 ( = 24).
•Character Color
Character color is assinged for each font, and the 4 components for expressing a color are listed below.
BlueCharacter & attribute register's CB bit[A]
GreenCharacter & attribute register's CG bit[9]
RedCharacter & attribute register's CR bit[8]
IntensityIf the EX-EN bit is '1' and the Frame Control Register 3 CTL’s CINT bit called by Character &
Attribute register’s Blink, SHA bits is '1', the character intensity feature is enabled.
•Raster Color
BlueCharacter & Attribute register's RB bit[D]
GreenCharacter & Attribute register's RG bit[C]
RedCharacter & Attribute register's RR bit[B]
Intensity
According to the 'EX-EN', 'RINT' and 'CINT' bits setting, raster and character color intensity can be assigned in
units of character.
Address 000h is appointed as blank data. RAM's initial values are all 0, and all bits are written as 0 when you
erase the RAM, so blank data means the initial value. In other words, blank data means 'do nothing'. You don't
need to write any data for the space font, except for 000h. It just needs to be an undotted area.
If the EX-EN bit is '1' and the Frame Control Register 3 CTL’s RINT bit called by Character &
Attribute register’s Blink, SHA bits is '1', the RASTER intensity feature is enabled.
Notes for When Making KB2514 Fonts
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•Other Color Effet
The Frame Control Register 0 'BGEN' bit's function is shown in the Figure below. If you set the 'BGEN' bit as '0'
after selecting A's raster color as black, the raster color black will be displayed. But if you set the 'BGEN' bit as
'1', after selecting B's raster color as black, the raster color black becomes invisible, so the video back ground
color (gray) is displayed as if it is the raster color.
BGEN bit = 0 & Rastor Color = Black
Black
A
Gray
Light Blue
Gray
BGEN bit = 1 & Rastor Color = Black
B
BGEN bit = 1 & Rastor Color = Light Blue
C
Figure 12. Color Effect by BGEN Bit
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HEIGHT/POSITIONING
•Character Height
The purpose of CH[5:0] (Character Height) is to output a uniformly sized OSD even if the resolution changes.
To express a Character Height of CH = 18 ~ CH = 63 after receiving CH[5:0]'s input from the frame control
register-1, decide on each line's repeating number (Standard Height CH = 18) and repeat the lines.
The following Figure shows two examples of a height-controlled character. height control is carried out by
repeating some of the lines.
1
2
3
4
5
6
Standard Font(12*18)
7
8
9
10
11
12
13
14
15
16
17
18
Standard font
in high vertical resolution
Height-controlled font
: added
line
Standard Font(12*18)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Standard font
in more higher vertical resolution
Figure 13. Character Height
: added
line
Height-controlled font
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KB2514 VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
Repeating line-number can be found by the following formula.
[# of the repeating lines = 2 + N × M],
where N = 1, 2, 3, ... and M = round{14 ÷ (CH[5:0]-18)}.
1. If CH[5:0] is greater than 32 and less than or equal to 46 (32 < CH[5:0] ≤ 46), all lines are repeated once or
twice. The lines that are repeated twice are chosen by the following formula.
[# of the repeating lines = 2 + N × M],
where N = 1, 2, 3, ... and M = round {14 ≤ (CH[5:0]-32)}.
2. If CH[5:0] is greater than 46 and less than or equal to 60 (46 < CH[5:0] ≤ 60), all lines are repeated two or three
times. The lines that are repeated three times are chosen by the following formula.
[# of the repeating lines = 2 + N × M],
where N = 1, 2, 3, ... and M = round {14 ≤ (CH[5:0]-46)}.
3. If CH[5:0] is greater than 60 and less than or equal to 64 (60 < CH[5:0] ≤ 64), all Lines are repeated three or four
times. The lines that are repeated four times are chosen by the following formula.
[# of the repeating lines = 2 + N x M],
where N = 1, 2, 3, ... and M = round {14 ≤ (CH[5:0]-60)}.
CH's reference value is 18, and even if you input 0, it operates in the same way as when CH = 18. The repeating
line-number is limited to 16. If the M value is less than or equal to 1, all lines of the standard font are repeated more
than once.
Table 13. Repeating Line as Controlling by CH bits
Preliminary
KB2514 VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
•Positioning
The frame control register-2's HP Bit [F:8] signifies delay of the horizontal display from the H-Sync reference
edge to the character's 1st pixel location, and is controlled by multiplying HP [F:8]'s range value by 6. Also, VP
bit[7:0] signifies the top margin height from the V-Sync reference edge, and is controlled by multiplying 4 to the
VP [7:0]'s range value. Refer to the Figure shown below.
(HFLB)
HP[7:0]
VP[7:0]
(VFLB)
OSD characters
30 columns (= 30 x 12 dots)
15 rows
(=15 x 18 lines)
Background Screen
Figure 14. Frame Composition with the OSD Characters
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VISUAL EFFECTS
•Shadowing
The character shadow can only be black. Character shadow is making 1 pixel to the right and below the
character.
Shadowing
Figure 15. Character Shadowing
•Scrolling
Scrolling is slowly displaying or erasing a character from the top line to the bottom. This effect makes it look as
if 1 character line is scrolling up or down. asharacter line is scrolling up or down.
Figure 16. Scrolling
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KB2514 VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
PLL CONTROL
•Introduction
PLL (Phase Lock Loop) is feedback controlled circuit that maintains a constant phase difference between a
reference signal and an oscillator output signal.
Generally, PLL is composed as follow Figure.
Reference Signal
PFD
(Phase Frequency Detector)
(Frequency Detector)
LF
(Loop Filter)
FD
VCO (Voltage
Controlled Oscillator)
Figure 17. Block Diagram of General PLL
- PFD (Phase Frequency Detector)
PFD compares the phase of the VCO output frequency, with the phase of a reference signal frequency output
pulse is generated in proportion to that phase difference.
- LF (Loop Filter)
LF smooths the output pulse of the phase detector and the resulting DC component is the VCO input.
- VCO (Voltage Controlled Oscillator)
VCO is controlled by loop filter output. The output of the VCO is fed back to the phase frequency detector
input for comparison which in turn controls the VCO oscillating frequency to minimize the phase difference.
- FD (Frequency Divider)
FD divides too much different frequency that is oscillated from the VCO to compare it with reference signal
frequency.
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•PLL of the KB2514
PLL is composed of the phase detector, charge pump, VCO, and N-divider as 4 sub-blocks.
HFLB (Pin32)
Detector
Div_out
Phase
Loop
Filter
CP_out
(Pin4)
Charge
Pump
N-Divider
CP0CP1DOT0DOT1HF0 HF1 HF2
# Composed of External Components
VCO_in
(Pin3)
Figure 18. Block Diagram of the PLL Built in KB2514
VCO
VCO_out
The following is the description of the input/output signals.
- HFLB (Input)
Horizontal flyback signal is refrence signal of the PLL built in KB2514.
The HFLB signal's frequency range is 15 ~ 90kHz, so the PLL block must be a wide range PLL that can cover
HFLB's entire frequency range.
> 4.2V
fHFLB
~2us
< 0.4V
- VCO (Input)
Error signal that passes through an external loop filter is input into VCO.
Operation voltage range is 1-4V. You can raise immunity towards external noise by lowering VCO
sensitivity. You can do this by making it have the maximum operation voltage range possible in the 5V power
voltage.
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- DOT0, 1 (Input)
Mode control signal that controls the number of dots per line in the frame control register. There are 4 modes:
320, 480, 640, and 800 dots/line.
According to your choice of mode, the OSD_PLL block's N-Divider is controlled by one of ÷320, ÷480, ÷640, or
÷800 Divider.
- HF0, 1, 2 (Input)
The horizontal Sync frequency information is received from the micro controller through the frame control
registers-1's bit C-A.
- CP0, 1 (Input)
Charge Pump's output sourcing (or sinking) current control pin.
This control data is received through frame control registers-1's bits E-D.
- VCO_OUT (Output)
VCO output that becomes a system clock. It is the OSD R, G, B output signal's dot frequency, and the standard
signal for OSD's various timings.
Also, it is input into the N-Divider and makes a PLL loop
> 4.2V
< 0.4V
fclk
Rise Time : < 4nS
Fall Time : < 4nS
- CP_OUT (Output)
Charge Pump circuit's output. input into external loop filter. It becomes one of 3 states according to the standard
signal input into the phase detector (HFLB) and the divider output (Div_Out).
- HFLB Div_Out is lead: Current sink
- HFLB Lag: Current source
- HFLB In-Phase: High impedence
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TUNNING FACTORS OF THE KB2514 PLL
•PLL External Circuit
You may follow the recommendations for PCB art work and input/output signal characteristic improvement in
recommendation.
The external circuit that has the most influence on KB2514 PLL block operation is pin 3 (VCO_IN) and pin 4
(CP_OUT)'s surrounding circuit. Refer to OSD PLL block.
34
C1
C2
R1R2
1MΩ
5
No Connection
(pin open)
Figure 19. PLL External Circuit
Because the PLL circuit is basically a feedback circuit, there are many components that influence the
characteristics. C1, C2, R1, and R2 do not have a localized effect.
As you can see, they are connected to the PLL control bits and influence the characteristics through their
complicated relationships. The main functions of the time canstant and their reference values are as follows.
Table 14. Main Function of Time Constant in PLL External Circuit
Time CanstantRecommended ValueMain Function
C110uFInfluences the damping ratio and controls the PLL
response time
R15.6KΩ(7.5KΩ)Same as C1
R227KΩ (or 33KΩ)Charge pump current adjustment
C233pFRemoves ripple caused by R-C circuit
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•PLL Control Bit
After configuring an external circuit using the recommended values, carry out programming using the
recommended values for frequency range and control bits given in the Table below.
•Locking Range
As you can see the figure below, it is 2.35V that measured voltage at pin-3 to optimize OSD quality. The proper
voltage range is 1.5 ~ 3.25V.
Locking Range
1.62 5V
Ve (min)
fmax
4V
3.25V
2.37V
1.5V
f0
0.75V
¥ð
-2
fC
fL
¥ð
2
Ve (max)
1.625V
Figure 20. Locking Range
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VIDEO AMP MERGED OSD PROCESSOR FOR MONITORSKB2514
•HF Bits Selection
HF bits is not selecting from out of 8 (23) steps uniformly, but selecting the step shown in figure below. In
example, at 800 mode, there are 5 steps that the frequency range is controlled by HF bits.
Table 16. HF Bits Selection
DIVDOT1DOT0HF2HF1HF0
32000
48001
64010
80011
After fixing time constants of the external circuit and PLL control bits except HF bits, if HF bits are stepped up, the
voltage measured at pin-3 drops. On the contrary, if HF bits are stepped down, the voltage rises.
The voltage measured at pin-3 don't change by changing CP bits.
•External Register at pin-4
The external register at pin-4 is the factor that changes greatly at PLL tunning. The initial value of this external
register value is decided as follows.
At first, the external register is replaced variable-register (about 50KΩ range).
and then, set the lowest PLL control bits at the lowest frequency allowed by set.
and then, change variable-register to be 2.35V that optimum voltage is locking.
and then, measure register value at this time.
also, set the highest PLL control bits at the highest frequency allowed by set.
and then, change variable-register to be 2.35V that optimum voltage is locking.
and then, measure register value at this time.
You may decide the average of these two registers' value to initial value.
47
Page 49
Preliminary
KB2514 VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
The table below shows that other factors change as changing external register's value.
Fixing FactorVariable FactorChangeVoltageCurrentLock Range
Time constants of the external circuit
and PLL control bits except
Rext
↑↑↓↓ (shift)
↓↓↑↑ (shift)
48
Page 50
Preliminary
VIDEO AMP MERGED OSD PROCESSOR FOR MONITORSKB2514
RECOMMENDATION
5V Power Routing
KB2514's OSD part power is composed of analog VDD and digital VDD. To eliminate clock noise influence in the
digital block, you need to separate the analog VDDA and digital VDD.
(BD102 use: Refer to Application Circuit )
12V Power Routing
Because KB2514 is a wideband AMP of above 150MHz, 12V power significantly affects the video characteristics.
The effects from the inductance and capacitance are different for each board, and , therefore, some tuning is
required to obtain the optimum performance. The output power, VCC2, must be separated from VCC1 and VCC3
using a coil, which is parallel-connected to the damping resistor.The appropriate coil value is between 20uH 200uH. Parallel-connected a variable resistor to the coil and control its resistance to obtain the optimum video
waveform.
(Moreover, BD103 can tune using a coil and variable resistor to obtain the optimum video waveform.
L103, R124, BD103: Refer to application circuit)
VCC1, VCC3 12V Power
Use a 104 capacitor and large capacitor greater than 470uH for the power filter capacitor.
12V Output Stage Power VCC2
Do not use the power filter capacitor.
5V Digital Power VDD
Don't use a coil or magnetic core to the VDD input. Make the power filter capacitor, an electric capacitor of greater
than 50uF, single and connect it to VSS, the digital GND.
Output Stage GND2
Care must be taken during routing because it ,as an AMP output stage GND, is an important factor of video
oscillation. R/G/B clamp cap and R/G/B load resistor must be placed as close as possible to the GND2 pin. GND2
must be arranged so that it has the minimum GND loop, which at one point must be connected to the main GND.
Digital GND VSS
When this is to be connected directly to the GND2, it can cause the OSD clock noise, so the loop connection
should be routed as far away as possible. If the OSD clock noise affects the screen, separate VSS GND from all
GND and connect it to the main board using a bead. Again, the bead connection point should be placed as far
away as possible to the GND2.
Analog Block
The PLL built in to KB2514 is sensitive to noise due to the wide range PLL characteristics. Therefore, you need to
isolate the analog block in the following manner. First make a separate land for the analog block (pin2 - pin6)'s
ground, and connect it to the main ground through a 1MΩ resistor. The analog GND of both sides of a double faced
PCB must be separated from the main ground. (Separate pin 2's 5V analog GND, which is the GND for OSD PLL,
from the main and digital GNDs and connect it to the main GND using about 1MΩ resistor. GND for pins 2 - 6 is the
No. 2 VSSA GND.)
49
Page 51
Preliminary
KB2514 VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
I2C Control Line (SCL, SDA Line)
I2C communication noise (noise generated in the OSD display pattern when data is transmitted in the I2C line) may
be generated because of an I2C control line that passes near the analog block. The I2C control lines near KB2514
must be separated from the analog block as much as possible.
Furthermore, the I2C bus interference can be prevented by inserting a series resistor in the line.
Horizontal Flyback Signal
Display jittering can be generated if the horizontal signal (HFLB) input to KB2514 is not a clean signal.
We recommend a short path and shielded cable for obtaining a clean signal.
Generally, the input horizontal signal (HFLB) is generated by using a high voltage horizontal flyback signal. The
effect from the high voltage flyback signal can be reduced by separating the R115 and R117 GND, which
determines the flyback signal slice level, from the transistor GND, which generates the actual KB2514 input
horizontal signal. Furthermore, the flyback signal sharpness must be maintained by minimizing the values of R115,
R116 and R117 resistors, which set the horizontal signal slice level. values.
(R115, R116, R117: Refer to application circuit )
HFLB Input Signal Generator
You can correct the circuit by reducing the resistors that sets the slice level of the horizontal signal in the HFLBgenerating circuit.
50
Page 52
Preliminary
12_1V
12V
BD103
VIDEO AMP MERGED OSD PROCESSOR FOR MONITORSKB2514
APPLICATION BOARD CIRCUIT
C117
R117
150
D102
R115
2K
13
Q102
2N3904
CN2
1N4148
1N4148
1N4148
RB01
75
CB02
104
6
RB02
75
CB02
104
16
BIN
BCLP17BOUT
RB03
470
RB04
100
RG01
75
15
18
RB15
47
CB08
270pF
14
C119
102
5V
SK101
WSP-401M
C126
C116
1nF
C118
330pF
R116
1N4148
1.8nF
1nF
10K
G1
12345678910111213
C123
103
C124
103
L101
100uH
R103
390
R118
R119
DR02
70V
DG02
6.3V
DB02
12V
R107
1K
R101
4.7K
R102
100
560
560
2
CN1
12345
1N4148
DR01
DG01
DB01
RR01
75
RG02
RR02
75
75
CR01
CG02
104
104
13
GIN14GND1
GND2
19
VCC311RIN12VCC1
GOUT
GCLP
VCC222RCLP
20
21
CG02
104
RG03
470
RG15
47
RG04
CG08
100
270pF
12V
C109
R123
VREF1
VREF5VDDA6CONT_CAP
VSS
SCL29SDA
27
28
C160
103
1M
C110
+
100uF
BD102
5V
R108
3
VCO_IN
30
R124
5.6K
C113
C114
10uF
33pF
2
VFLB1VSSA
C152
104
+
470uF
C103
HFLB
VDD
31
220
27uH
C151
32
104
C128
104
5V
R114
470
R109
27K
4
+
47uF
L103
1N4148
1N4148
C102
+
1uF
C112
+
1uF
10
7
8
ABL_IN
GND9CLP_IN
KB2514
ROUT
BCT
GCT26RCT
23
24
25
CR02
104
RR03
470
RR15
47
RR04
CR08
100
270pF
CB05
RB12
2.2K
2N5401C-Y
6
7
9
8
BIN
GIN
RIN
LG01
0.15uH
VBB
ROUT1GOUT
RB08
RG08
CG07
56
56
37pF
RG14
75
LB01
0.15uH
DRIVER IC
BOUT
GND
VCC
2
5
3
4
CB07
37pF
RB14
75
C121
104
C108
+
47uF
70V
DB03
DG03
1SS244
DR03
1SS244
1SS244
+
+
CB04
CG04
1uF
G_OUT
1uF
RB09
75K
RB10
RG10
39
39
B_OUT
RR09
75K
RG09
75K
C106
C107
70V
DMS-200D
DMS-200D
DMS-200D
220uF
104
+
1SS244
1SS244
1SS244
12V
RR08
CR07
56
37pF
RR14
75
LR01
0.15uH
DB04
DG04
DR04
+
CR04
1uF
RR10
SKB01
39
SKG01
SKR01
R_OUT
CG05
RG12
2.2K
2N5401C-Y
104
QG02
DMS-200D
RG11
100
RG20
4.7K
13
QG01
2
2N5551C-Y
CG05
104
2
13
RG13
82K
DG05
1N4148
SK102
C120
CR05
RR12
2.2K
2N5401C-Y
1nF
RR11
100
RR20
4.7K
13
QR01
2
2N5551C-Y
CR05
104
104
2
QR02
13
RR13
82K
DR05
1N4148
R104
390
RB11
100
RB20
4.7K
13
QB01
2
2N5551C-Y
CB05
104
104
2
QB02
13
RB13
82K
DB05
1N4148
G2G2
Figure 21. Application Board Circuit
51
Page 53
Preliminary
12_1V
12V
BD103
KB2514 VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
TYPICAL APPLICATION CIRCUIT
C117
R117
150
D102
R115
2K
13
Q102
2N3904
CN2
1N4148
1N4148
1N4148
RB01
75
CB02
104
6
RB02
75
CB02
104
16
BIN
BCLP17BOUT
RB03
470
RG01
75
15
18
RB15
47
14
C119
102
5V
SK101
12345678910111213
C123
103
C124
103
L101
100uH
R103
390
DR02
70V
DG02
6.3V
DB02
12V
R107
1K
R101
4.7K
R102
100
WSP-401M
C126
C116
1nF
C118
330pF
R116
1N4148
1.8nF
1nF
10K
G1
R118
560
R119
560
2
CN1
12345
1N4148
DR01
DG01
DB01
RR01
75
RG02
RR02
75
75
CR01
CG02
104
104
13
GIN14GND1
GND2
19
VCC311RIN12VCC1
GOUT
GCLP
VCC222RCLP
20
21
CG02
104
RG03
470
RG15
47
12V
C109
R123
VREF1
VREF5VDDA6CONT_CAP
VSS
SCL29SDA
27
28
C160
103
1M
C110
+
100uF
BD102
5V
R108
3
VCO_IN
30
R124
5.6K
C113
C114
10uF
33pF
2
VFLB1VSSA
C152
104
+
470uF
C103
HFLB
VDD
31
220
27uH
C151
32
104
C128
104
5V
R114
470
R109
27K
4
+
47uF
L103
1N4148
1N4148
C102
C112
+
+
1uF
1uF
10
7
8
ABL_IN
GND9CLP_IN
KB2514
ROUT
BCT
GCT26RCT
23
24
25
CR02
104
RR03
470
RR15
47
CB05
RB12
2.2K
2N5401C-Y
6
7
9
8
BIN
GIN
RIN
G_OUT
+
RG10
39
VBB
ROUT1GOUT
RG14
75
CG04
1uF
LG01
0.15uH
2
B_OUT
BOUT
+
DRIVER IC
GND
VCC
5
3
4
RB14
75
C121
104
C108
+
47uF
70V
DB03
DG03
1SS244
DR03
1SS244
1SS244
CB04
1uF
RB09
75K
LB01
0.15uH
RB10
39
RR09
75K
RG09
75K
C106
C107
70V
DMS-200D
DMS-200D
DMS-200D
220uF
104
+
1SS244
1SS244
1SS244
12V
RR14
75
DB04
DG04
DR04
+
CR04
1uF
LR01
0.15uH
RR10
SKB01
39
SKG01
SKR01
R_OUT
CG05
RG12
2.2K
2N5401C-Y
104
QG02
DMS-200D
RG11
100
RG20
4.7K
13
QG01
2
2N5551C-Y
CG05
104
2
13
RG13
82K
DG05
1N4148
SK102
C120
CR05
RR12
2.2K
2N5401C-Y
1nF
RR11
100
RR20
4.7K
13
QR01
2
2N5551C-Y
CR05
104
104
2
QR02
13
RR13
82K
DR05
1N4148
R104
390
RB11
100
RB20
4.7K
13
QB01
2
2N5551C-Y
CB05
104
104
2
QB02
13
RB13
82K
DB05
1N4148
G2G2
Figure 22. Typical Application Circuit
52
Page 54
Preliminary
VIDEO AMP MERGED OSD PROCESSOR FOR MONITORSKB2514
ROM FONTS
Figure 23. ROM Fonts
53
Page 55
Preliminary
KB2514 VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
54
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