Datasheet KB2512 Datasheet (Samsung)

JUN. 2000

Ver 0.3

DATA SHEET

KB2512

Preliminary

KB2512 DEFLECTION PROCESSOR FOR MULTISYNC MONITORS

DEFLECTION PROCESSOR

32-SDIP-400

The KB2512 is a monolithic integrated circuit assembled in 32 pins
shrunk dual in line plastic package. This IC controls all the functions
related to the horizontal and vertical deflection in multi modes or multi­frequency computer display monitors.

The internal sync processor, combined with the very powerful geometry
correction block make the KB2512 suitable for very high performance
monitors with very few external components. The horizontal jitter level is
very low. It is particularly well suited for high-end 17” and 19” monitors.

FUNCTIONS

ORDERING INFORMATION

• Deflection processor

• I2C bus control

• B+ regulator

• Vertical parabola generator

• Vertical dynamic focus

FEATURES

Device Package Operating Temperature

KB2512 32-SDIP-400 0 °C ~ 70 °C

• Horizontal dynamic phase (side pin balance &
parallelogram)

• Vertical dynamic focus (Vertical focus amplitude)

(HORIZONTAL)

• Self-adaptive

• Dual PLL concept

• 150kHz maximum frequency

• X-RAY protection input

• I2C controls: Horizontal duty-cycle, H-position, free
running frequency, frequency generator for burn-in
mode.

(VERTICAL)

• Vertical ramp generator

• 50 to 185Hz AGC loop

• Geometry tracking with V-POS & V-AMP

• I2C Controls: V-AMP, V-POS, S-CORR, C-CORR

• DC breathing compensation

(I2C GEOMETRY CORRECTIONS)

• Vertical parabola generator
(pincushion-E/W, keystone, corner)

(GENERAL)

• Sync processor

• 12V supply voltage

• Hor. & Vert. lock/unlock outputs

• Read/Write I2C interface

• Horizontal and vertical moire

• B+ Regulator

- Internal PWM generator for B+ current mode
step-up converter.

- I2C adjustable B+ reference voltage

- Output pulses synchronized on horizontal
frequency

- Internal maximum current limitation.

- Soft start

• Compared with the KB2511B, KB2512 HAS:

- Corner correction

- Horizontal moire

- B+ soft start

- Increased max. Vertical frequency

- No horizontal focus

- No step down option for DC/DC converter.

1

DEFLECTION PROCESSOR FOR MULTISYNC MONITORS KB2512

BLOCK DIAGRAM

HREF

HGND

H/HVIN

VSYNCIN

VCC

XRAY

VREF

VGND

SDA

SCL

GND

PLL1F

H POSITION

7

8

13

V

R

PHASE/

EF

FREQUENCY

COMPARATOR

11

1

2

29

25

21

19

5V

32

31

30

27

H-PHASE(7 bits)

SYNC INPUT

SELECT

(1bit)

V

R

EF

RESET

GENERATOR

2

I C INTERFACE

SYNC

PROCESSOR

HLOCKOUT

3

LOCK/UNLOCK

IDENTIFICATION

R0

C0

5

6 12 4

VCO

Forced

Freq.
2 bits

Free running

5 bits

VSYNC

MOIRE

CANCEL

5 BITS+ON/OFF

6 bits 8 bits

S AND C

CORRECTION

HFLY

PHASE

COMPARATOR

VERTICAL

OSCILLATOR

RAMP GENERATOR

+

VPOS

7bits

PLL2C

PHASE

SHIFTER

SAFETY

PROCESSOR

2

X

Spin Bal

6 bits

2

X

Key Bal

6 bits

VAMP

7 bits

B+ ADJUST

GEOMETRY

TRACKING

+

5V
Vcc
XRAY

7 bits

H-DUTY

(5 bits)

CONTROLLER

HSYNC

Moire Cancel
5 bits + on/off

Corner

7 bits

B+

Horizontal

4

X
EW

7 bits

2

X

keyst
6 bits

X

HOUT

26

HOUT

BUFFER

+

AMPVDF

6 bits

14

COMP

B+ OUT

28

REGIN

15

16

ISENSE

17

BGND

9

HMOIRE

10

FOCUS

22 20

VCAP

VACCAP

18

BREATH

23

VOUT

24

EWOUT

2

KB2512 DEFLECTION PROCESSOR FOR MULTISYNC MONITORS

PIN CONFIGURATIONS

1

2

3

4

5

6

7

8

9

10

11

H/HVIN

VSYNCIN

HLOCKOUT

PLL2C

C0

R0

PLL1F

HPOSITION

HMOIRE

FOCUSOUT

HGND

32

5V

31

SDA

30

SCL

29

VCC

GND

28

27

26

25

24

23

22

BOUT

HOUT

XRAY

EWOUT

KB2512

VOUT

VCAP

12

HFLY

13

HREF

14

COMP

15

REGIN

16

ISENSE

3

VREF

VAGCCAP

VGND

BREATH

B+GND

21

20

19

18

17

DEFLECTION PROCESSOR FOR MULTISYNC MONITORS KB2512

PIN DESCRIPTION

Table 1. Pin Description

No Pin Name Description

1 H/HVIN TTL compatible horizontal sync input (separate or composite)
2 VSYNCIN TTL compatible vertical sync input (for separated H&V)
3 HLOCKOUT First PLL lock/unlock output (0V unlocked - 5V locked)
4 PLL2C Second PLL loop filter
5 C0 Horizontal oscillator capacitor
6 R0 Horizontal oscillator resistor
7 PLL1F First PLL loop filter
8 HPOSITION Horizontal position filter (capacitor to be connected to HGND)

9 HMOIRE Horizontal moire output (to be connected to PLL2 C through a resistor divider)
10 FOCUSOUT Vertical dynamic focus output
11 HGND Horizontal section ground
12 HFLY Horizontal Flyback input (positive polarity)
13 HREF Horizontal section reference voltage (to be filtered)
14 COMP B+ error amplifier output for frequency compensation and gain setting
15 REGIN Regulation input of B+ control loop
16 ISENSE Sensing of external B+ switching transistor current
17 B+GND Ground (related to B+ reference adjustment)
18 BREATH DC breathing input control (compensation of vertical amplitude against EHV

variation)
19 VGND Vertical section ground
20 VAGCCAP Memory capacitor for automatic gain control loop in vertical ramp generator
21 VREF Vertical section reference voltage (to be filtered)
22 VCAP Vertical sawtooth generator capacitor
23 VOUT Vertical ramp output

(with frequency independent amplitude and S or C corrections if any).

It is mixed with vertical position voltage and vertical moire.
24 EWOUT Pincushion-East/West correction parabola output
25 XRAY X-RAY protection input (with internal latch function)
26 HOUT Horizontal drive output (internal transistor, open collector)
27 GND General ground (referenced to Vcc)
28 BOUT B+ PWM regulator output
29 Vcc Supply voltage (12V typ)
30 SCL

31 SDA
32 5V Supply voltage (5V typ)

I2C clock input

I2C data input

4

KB2512 DEFLECTION PROCESSOR FOR MULTISYNC MONITORS

REFERENCE DATA

Table 2. Reference Data

Parameter Value Unit

Horizontal frequency 15 to 150 kHz
Autosynch frequency (for given R0 and C0) 1 to 4.5FO FH
± Horizontal sync polarity input Yes
Polarity detection (on both horizontal and vertical section) Yes
TTL composite sync Yes
Lock/unlock identification (on both horizontal 1st PLL and vertical section) Yes

I2C control for H-position
XRAY protection Yes

I2C horizontal duty cycle adjust
I2C free running frequency adjustment

Stand-by function Yes
Dual polarity H-drive outputs No
Supply voltage monitoring Yes
PLL1 inhibition possibility No
Blanking output No
Vertical frequency 35 to 200 Hz
Vertical Autosync (for 150nf on pin22 and 470nf on pin20) 50 to 185 Hz
Vertical S correction Yes
Vertical C correction Yes
Vertical amplitude adjustment Yes
DC breathing control on vertical amplitude Yes
Corner correction Yes

±10 %

30 to 60 %

0.8 to 1.3FO FH

East/West parabola output (also known as pin cushion output) Yes
East/West correction amplitude adjustment Yes
Keystone adjustment Yes
Vertical position adjustment Yes
Internal dynamic horizontal phase control Yes
Side pin balance amplitude adjustment Yes
Parallelogram adjustment Yes
Tracking of geometric corrections with vertical amplitude and position Yes
Reference voltage (both on horizontal and vertical) Yes

5

DEFLECTION PROCESSOR FOR MULTISYNC MONITORS KB2512

Table 2. Reference Data (Continued)

Parameter Value Unit

Vertical dynamic focus Yes
I2C horizontal dynamic focus amplitude adjustment
I2C horizontal dynamic focus symmetry adjustment
I2C vertical dynamic focus amplitude adjustment

No
No

Yes

Deflection of input sync type Yes
Vertical moire output Yes
Horizontal moire output Yes

I2C controlled moire amplitude

Yes
Frequency generator for burn-in Yes
Fast I2C read/write
B+ regulation adjustable by I2C

400 kHz

Yes
B+ soft start Yes

6

KB2512 DEFLECTION PROCESSOR FOR MULTISYNC MONITORS

ABSOLUTE MAXIMUM RATINGS

Table 3. Absolute Maximum Ratings

No Item Symbol Value Unit

1 Supply voltage (Pin 29) V
2 Supply voltage (Pin 32) V
3 Maximum voltage on Pin 4

CC
DD

V

IN

Pin 5
Pin 6, 7, 8, 14, 15, 16, 20, 22
Pin 9, 10, 18, 23, 24, 25, 26, 28
Pin 1, 2, 3, 30, 31

4 ESD susceptibility

VESD 2
Human body model, 100pF discharge through 1.5KΩ
EIAJ norm, 200pF discharge through 0Ω

5 Storage temperature Tstg - 40, +150 °C
6 Operating temperature Topr 0, +70 °C

13.5 V

5.7 V

4.0

6.4

8.0

V

CC

V

DD

kV

300

V
V
V
V
V

V

THERMAL CHARACTERISTICS

Table 4. Thermal Characteristics

No Item Symbol Value Unit

1 Junction temperature Tj +150 °C
2 Junction-ambient thermal resistance θja 65 °C/W

SYNC PROCESSOR

OPERATING CODNITIONS(VDD = 5V, Tamb = 25 °C)

Table 5. Sync Processor Operating Conditions

Parameter Symbol Conditions Min Typ Max Unit

Horizontal sync input voltage HsVR Pin 1 0 5 V
Minimum horizontal input pulse duration MinD Pin 1 0.7 µs
Maximum horizontal input signal duty cycle Mduty Pin 1 25 %
Vertical sync input voltage VsVR Pin 2 0 5 V
Minimum vertical sync pulse width VSW Pin 2 5 µs
Maximum vertical sync input duty cycle VSmD Pin 2 15 %
Maximum vertical sync width on TTL H/V composite VextM Pin 1 750 µs
Sink and source current I

HLOCKOUT

Pin 3 250 µA

7

DEFLECTION PROCESSOR FOR MULTISYNC MONITORS KB2512

ELECTRICAL CHARACTERISTICS

(VDD = 5V, Tamb = 25 °C)

Table 6. Sync Processor Electrical Characteristics

Parameter Symbol Conditions Min Typ Max Unit

Horizontal and vertical input threshold
voltage (pin 1, 2)

Horizontal and vertical pull-up resister RIN Pins 1,2 200 KΩ
Falling and rising output CMOS buffer TfrOut Pin 3, Cout = 20pF 200 ns
Horizontal 1st PLL lock output status

(pin 3)
Extracted Vsync integration time (% of

(see 9)

TH

) on H/V composite

VINTH Low level

0.8 V

High level 2.2

VHlock Locked, I

Unlocked, I

LOCKOUT

LOCKOUT

= -250µA

= +250µA

4.4

0
5

0.5 V

VoutT C0 = 820pF 26 35 %

V

V

I2C READ/WRITE (See also I

2

C table control and I2C sub address control)

OPERATING CONDITIONS (VDD = 5V, Tamb = 25 °C)

Table 7. I2C Read/Write Operating Conditions

Parameter Symbol Condition Min Typ Max Unit

Input high level voltage VinH 3.0 - 5.0 V
Input low level voltage VinL 0 - 1.5 V
Hold time before a new

tBUF 1.3 - - µs

transmission can start
Hold time for start conditions tHDS 0.6 - - µs
Set-up time for stop conditions tSUP 0.6 - - µs
Hold time data tHDAT 0.3 - - µs
Set-up time data tSUPDAT 0.25 - - µs
Rise time of SCL tR - - 1.0 µs
Fall time of SCL tF - - 3.0 µs
Maximum clock frequency Fscl Pin 30 400 kHz
Low period of the SCL clock Tlow Pin 30 1.3 µs
High period of the SCL clock Thigh Pin 30 0.6 µs
SDA and SCL input threshold Vinth Pin 30, 31 2.2 V
Acknowledge output voltage on

VACK Pin 31 0.4 V

SDA input with 3mA

8

KB2512 DEFLECTION PROCESSOR FOR MULTISYNC MONITORS

I2C Bus Timing Requirement

SDA

SCL

t

BUF

Start:Clock High

t

HDS

HORIZONTAL SECTION

OPERATING CONDITIONS

Table 8. Horizontal Section Operating Conditions

Parameter Symbol Conditions Min Typ Max Unit

VCO

Minimum oscillator resistor Ro
Minimum oscillator capacitor Co
Maximum oscillator frequency Fo

OUTPUT SECTION

t

HDAT

t

SUPDAT

(Min.)
(Min.)

(Max.)

Stop:Clock High

t

SUP

t

t

HIGH

Data Change:Clock Low

LOW

Pin 6 6 KΩ
Pin 5 390 pF

150 kHz

Maximum input peak current I12m Pin 12 5 mA
Horizontal drive output maximum

HOI Pin 26, sunk current 30 mA

current

ELECTRICAL CHARACTERISTICS (VDD = 5V, Tamb = 25 °C)

Table 9. Horizontal Section Electrical Characteristics

Parameter Symbol Conditions Min Typ Max Unit

SUPPLY AND REFERENCE VOLTAGE

Supply voltage Vcc Pin 29 10.8 12 13.2 V
Supply voltage V
Supply current I
Supply current I
Horizontal reference voltage V
Vertical reference voltage V

DD
CC
DD

REF-H
REF-V

9

Pin 32 4.5 5 5.5 V
Pin 29 50 mA
Pin 32 5 mA
Pin 13, I = -2mA 7.4 8 8.6 V
Pin 21, I = -2mA 7.4 8 8.6 V

DEFLECTION PROCESSOR FOR MULTISYNC MONITORS KB2512

Table 9. Horizontal Section Electrical Characteristics (Continued)

Parameter Symbol Conditions Min Typ Max Unit

Max. sourced current on V
Max. sourced current on V

REF-H
REF-V

1st PLL SECTION

Polarity integration delay HpoIT Pin 1 0.75 ms
VCO control voltage (pin 7) V

VCO gain (pin 7) V

Horizontal phase adjustment

(see 11)

Horizontal phase setting value (Pin 8)

(see 11)

Minimum current value
Typical value
Maximum value

PLL1 filter current charge IPII1U

Free running frequency fo Ro = 6.49KΩ,

Free running frequency thermal drift (no
drift on external components)

(see 7)

Free running frequency adjustment
Minimum value
Maximum value

PLL1 capture range CR Ro = 6.49KΩ,

Safe forced frequency
SF1 Byte 11 x x x x x x
SF2 Byte 10 x x x x x x

2ND PLL SECTION HORIZONTAL OUTPUT SECTION

Flyback input threshold
voltage (pin12)

Horizontal jitter Hjit At 31.4kHz 70 ppm

I

REF-H

I

REF-V

VCO

COG

Pin 13 5 mA
Pin 21 5 mA

V
fo

fH (Max.)
Ro = 6.49KΩ,

REF-H

= 8V

1.3

6.2

V
V

17 kHz/V
Co = 820pF,
dF/dV = 1/11RoCo

Hph % of horizontal period ±10 %

Sub-address 01

Hphmin

Hphtyp

Hphmax

IPII1L

Byte x 1111111
Byte x 1000000
Byte x 0000000

PLL1 is unlocked
PLL1 is locked

Co = 820pF,

2.8

3.4

4.0

±140

±1

V
V
V

µA

mA

22.8 kHz

fo = 0.97/8RoCo

dF0/dT -150 ppm/c

Sub-address 02

fo(Min.)

fo(Max.)

Byte x x x 11111
Byte x x x 00000

0.8

1.3

Fo
Fo

Co = 820pF,
from fo + 0.5kHz to

4.5Fo (fo:22.8kHz)
fH (min.)
fH (max.)

100

23.5 kHz
kHz

SFF Sub-address 02

2F0
3F0

FBth 0.65 0.75 V

10

KB2512 DEFLECTION PROCESSOR FOR MULTISYNC MONITORS

Table 9. Horizontal Section Electrical Characteristics (Continued)

Parameter Symbol Conditions Min Typ Max Unit

Horizontal drive output duty-cycle
(pin 26)

(see 1)

Low level
High level

X-RAY protection input threshold
voltage

Internal clamping levels on 2nd PLL
loop filter (pin 4)

Threshold voltage to stop H-out, V-out,
B-out and XRAY when VCC < VSCinh

HDmin

HDmax

XRAYth

Vphi2 Low level

VSCinh Pin 29 7.5 V

Sub-address 00

Byte xxx11111
Byte xxx00000

Pin 25

(see 12)

High level

(see 2)

30
60

8 V

1.6

4.0

%
%

V
V

Threshold voltage to stop H-out, V-out,

VSDinh Pin 32 4.0 V

B-out and reset XRAY when VDD <
VSDinh

Horizontal drive output (low level) HDvd Pin 26 I

OUT

VERTICAL DYNAMIC FOCUS FUNCTION (POSITIVE PARABOLA)

Bottom DC output level HDFDC R
DC output voltage thermal drift

Vertical dynamic focus parabola

(see 17)

TDHDF

AMPVDF Sub-address 0F

= 10KΩ, Pin 10 2 V

LOAD

amplitude with VAMP and VPOS typical
Min. Byte 000000
Typ. Byte 100000
Max. Byte 111111

Parabola amplitude function of VAMP
(tracking between VAMP and VDF) with

VPOS typ. (Figure 1)

(see 3)

VDFAMP Sub-address 05

Byte 10000000
Byte 11000000
Byte 11111111

Parabola asymmetry function of VPOS
control (tracking between VPOS and

VDF) with VAMP Max.

VHDFKeyt Sub-address 06

Byte x0000000
Byte x1111111

= 30mA 0.4 V

200 ppm/C

0

0.5
1

0.6
1

1.5

0.52

0.52

Vpp
Vpp
Vpp

Vpp
Vpp
Vpp

Vpp
Vpp

11

DEFLECTION PROCESSOR FOR MULTISYNC MONITORS KB2512

VERTICAL SECTION

OPERATING CONDITIONS

Table 10. Vertical Section Operating Conditions

Parameter Symbol Conditions Min Typ Max Unit

OUTPUTS SECTION

Maximum EW output voltage VEWM Pin 24 6.5 V
Minimum EW output voltage VEWm Pin 24 1.8 V
Minimum load for less than 1% vertical amplitude

R

LOAD

Pin 20 65 MΩ

drift

ELECTRICAL CHARACTERISTICS (VCC = 12V, TAMB = 25 °C)

Table 11. Vertical Section Electrical Characteristics

Parameter Symbol Conditions Min Typ Max Unit

VERTICAL RAMP SECTION

Voltage at ramp bottom point VRB V

REF-V

= 8V,

2 V

Pin 22

Voltage at ramp top point (with sync) VRT V

REF-V

= 8V,

5 V

Pin 22
Voltage at ramp top point (without sync) VRTF Pin 22
Vertical sawtooth discharge time duration

VSTD With 150nF cap 70 µs

VRT-0.1

(pin 22)
Vertical free running frequency see

(see 4)

VFRF C

OSC (pin22)

=150nF

100 Hz
measured on
pin 22

AUTO -SYNC frequency

(see 13)

Ramp amplitude drift versus frequency at
Maximum vertical amplitude

Ramp linearity on pin 22 (∆I22/I22)

(see 4)

Vertical position adjustment voltage
(pin 23 - V

centering)

OUT

Vertical output voltage
(peak-to-peak on pin 23)

ASFR C22=150nF ± 5% 50 185 Hz
RAFD C

= 150nF

22

200 ppm/
50Hz < f < 185Hz

RIin 2.5 < V22 < 4.5V 0.5 %

Vpos Sub address 06

Byte x0000000
Byte x1000000
Byte x1111111 3.65

3.2

3.5

3.8

3.3 V

VOR Sub address 05

Byte x0000000
Byte x1000000
Byte x1111111 3.5

2.25
3

3.75

2.5 V

Vertical output maximum current (pin 23) VOI ±5 mA

V

Hz

V
V

V
V

12

KB2512 DEFLECTION PROCESSOR FOR MULTISYNC MONITORS

Table 11. Vertical Section Electrical Characteristics (Continued)

Parameter Symbol Conditions Min Typ Max Unit

Max vertical S-correction amplitude

(see 14)

XOXXXXXX inhibits S-CORR
X1111111 gives max S-CORR

Vertical C-Corr amplitude
XOXXXXXX inhibits C-corr

EAST/WEST FUNCTION

DC output voltage with typ. Vpos, keystone
and corner inhibited

DC output voltage thermal drift TDEW

Parabola amplitude with max. Vamp,
typ. V-Pos, keystone and corner inhibited

Parabola amplitude function of V-AMP control
(tracking between V-AMP and E/W) with typ.

Vpos, typ. EW amplitude, keystone and corner
inhibited

(see 8)

Keystone adjustment capability with typ.Vpos,
corner and E/W inhibited and max. vertical
amplitude.

(see 8)

Intrinsic keystone function of V-POS control
(tracking between V-pos and EW) max. E/W

and max. vertical amplitude and corner
inhibited.

(see 7)

A/B ratio
B/A ratio

Corner amplitude with max. VAMP, typ.
VPOS,

keystone and E/W inhibit

dVS Sub address 07

∆V/Vpp at TV/4
∆V/Vpp at 3TV/4

Ccorr Sub address 08

∆V/Vpp at TV/2
Byte X1000000
Byte X1100000
Byte X1111111

EW

DC

pin 24,
see figure 2

see note 7 100 ppm/

DC

EWpara Sub address 0A

Byte 1111111
Byte 1100000
Byte 1000000

EWtrack Sub address 05

Byte 1000000
Byte 1100000
Byte 1111111

KeyAdj Sub address 09

Byte 1x000000
Byte 1x111111

Key-

Sub address 06

Track

Byte x0000000
Byte x1111111

Corner Sub address 0B

Byte 11111111
Byte 11000000
Byte 10000000

-4

+4

-3
0
3

2.5 V

1.7

0.85
0

0.30

0.55

0.85

0.65

0.65

0.52

0.52

1.7
0

-1.7

%
%

%
%
%

C

Vpp
Vpp
Vpp

Vpp
Vpp
Vpp

Vpp
Vpp

Vpp
Vpp
Vpp

INTERNAL HORIZONTAL DYNAMIC PHASE CONTROL FUNCTION

Side pin balance parabola amplitude (Figure3)
with max. Vamp, typ. V-POS and

parallelogram inhibited

13

(see 8, 9)

SPBpara Sub address 0D

Byte x1111111
Byte x1000000

+1.4

-1.4

%T
%T

H
H

DEFLECTION PROCESSOR FOR MULTISYNC MONITORS KB2512

Table 11. Vertical Section Electrical Characteristics (Continued)

Parameter Symbol Conditions Min Typ Max Unit

Side pin balance parabola amplitude function
of Vamp control (tracking between Vamp and
SPB) with max. SPB, typ. V-POS and

parallelogram inhibited

(see 8, 9)

Parallelogram adjustment capability with max.
Vamp, typ. V-POS and max. SPB

(see8, 9)

Intrinsic parallelogram function of Vpos control
(tracking between V-pos and DHPC) with max.
Vamp, max. SPB and parallelogram inhibited

(see 8, 9)

A/B ratio
B/A ratio

VERTICAL MOIRE

Vertical moire (measured on V

OUT

) pin 23

BREATHING COMPENSATION

DC breathing control range

(see 15)

Vertical output variation versus DC breathing
control (Pin 23)

SPBtrack Sub address 05

Byte 10000000
Byte 11000000
Byte 11111111

ParAdj Sub address 0E

Byte x1111111
Byte x1000000

Partrack Sub address 06

Byte x0000000
Byte x1111111

VMOIRE

BRRANG

BRADj V18 ≥ V

Sub address 0C

Byte 01x11111

V18 1 12 V

REF-V

V18 = 4V

0.5

0.9

1.4

+1.4

-1.4

0.52

0.52

6 mV

0

-10

%T
%T
%T

%T
%T

%
%

H
H
H

H
H

14

KB2512 DEFLECTION PROCESSOR FOR MULTISYNC MONITORS

B+ SECTION

OPERATING CONDITIONS

Table 12. B+ Section Operating Conditions

Parameter Symbol Conditions Min Typ Max Unit

Minimum feedback resistor FeedRes Resistor between pins 15 and 14 5 KΩ

ELECTRICAL CHARACTERISTICS

(VCC = 12V, Tamb = 25 °C)

Table 13. B+ Section Electrical Characteristics

Parameter Symbol Conditions Min Typ Max Unit

Error amplifier open loop gain OLG
Sunk current on error amplifier output

Icomp

At low frequency
Pin 14

(see 12)

when BOUT is in safety condition
Unity gain band width UGBW

(see 7)

Regulation input bias current IRI Current sourced by pin 15

(PNP base)

Maximum guaranteed error amplifier
output current

EAOI Current sourced by pin 14

Current sunk by pin 14
Current sense input voltage gain CSG Pin 16 3
Max current sense input threshold

MCEth Pin 16 1.2 V

voltage
Current sense input bias current ISI Current sourced by pin 16

(PNP base)
Maximum external power transistor on

time
B+ output saturation voltage B+OSV V28 with I

Internal reference voltage IV

Tonmax % of H-period

@ fo = 27kHz

28

REF

On error amp positive input

for subaddress 0B

Byte 1000000
Internal reference voltage adjustment

range
Falling time t

V

REFADJ

FB+

Byte 111111

Byte 000000

Pin 28 100 ns

(see 10)

85 dB

0.5 mA

6 MHz

0.2 µA

0.5
2

mA
mA

1 µA

100 %

(see 6)

= 10mA 0.25 V

4.8 V

+20

-20

%
%

15

DEFLECTION PROCESSOR FOR MULTISYNC MONITORS KB2512

NOTES:

1. Duty cycle is the ratio of power transistor off time period. Power transistor is off when output transistor is off.

2. Initial condition for safe operation start up.

3. S and C correction are inhibited so the output sawtooth has a linear shape.

4. With register 07 at byte x0xxxxxx (s-correction is inhibited) then the S correction is inhibited, and with register 08 at byte
x0xxxxxx (C-Correction is inhibited) consequently the sawtooth has a linear shape.

5. These parameters are not tested on each unit. They are measured during our internal qualification.

6. The external power transistor is OFF during 400ns.

7. These parameters are not tested on each unit. They are measured during out internal qualification.

8. Refers to notes 4.

9. TH is the Horizontal period.

10. These parameters are not tested on each unit. They are measured during our internal qualification procedure which
includes characterization on batches coming from corners of our processes and also temperature characterization.

11. See Figure 7 for explanation of reference phase.

12. See Figure 11.

13. This is the frequency range for which the vertical oscillator will automatically synchronize, using a single capacitor value on
Pin 22 and with a constant ramp amplitude.

14. TV is the vertical period.

15. When not used the DC breathing control pin must be connected to 12V.

CAUTIONS:

The ICS near CDT can be latched up by EHT. Therefore, in order to minimize the impact of the EHT, it is necessary to place
ICs far from CDT.

16

KB2512 DEFLECTION PROCESSOR FOR MULTISYNC MONITORS

VDF

AMP

B

A

VDF

DC

Figure 1. Vertical Dynamic Focus Function

EW

PARA

B

A

EW

DC

Figure 2. E/W Output

B

A

SPB

PARA

DHPC

PC

Figure 3. Dynamic Horizontal Phase Control Output

17

DEFLECTION PROCESSOR FOR MULTISYNC MONITORS KB2512

Table 14. Typical Vertical Output Wave forms

Function Sub

Pin Byte Specification Picture Image

Address

Vertical Size 05 23

Vertical

06 23

Position

DC

Control

Vertical

07 23

S

Linearity

10000000

11111111

x0000000
x1000000
x1111111

x0xxxxxx

Inhibited

x1111111

V

OUTDC

V

OUTDC

Vpp

3.2V

3.5V

3.8V

∆V

∆V

Vpp

2.25V

3.75V

=4%

Vertical

C

Linearity

08 23

x1000000

x1111111

Vpp

Vpp

∆V

∆V

∆V

Vpp

∆V

Vpp

=3%

=3%

18

KB2512 DEFLECTION PROCESSOR FOR MULTISYNC MONITORS

Table 15. Geometry Output Wave forms

Function Sub

Pin Byte Specification Picture Image

address

Key stone

(trapezoid)

09 24 E/W + corner

inhibited

control

1x000000

1x111111

E/W

(pin cushion)

0A 24 Keystone +

corner Inhibited

control

10000000

1111111

Corner control 0B 24 Keystone + E/W

inhibited

11111111

0.65V

0.65V

2.5V

2.5V

2.5V

0V

1.7V

1.7V

2.5V

Parallelogram

control

Side pin

balance

control

Vertical

dynamic

focus

10000000

0E Internal SPB

Inhibited

1x000000

1x111111

0D Internal Parallelogram

Inhibited

1x000000

1x111111

OF 10

3.7V

3.7V

3.7V

3.7V

2V

T

V

1.7V

1.4% T

1.4% T

1.4% T

1.4% T

H

H

H

H

19

DEFLECTION PROCESSOR FOR MULTISYNC MONITORS KB2512

I2C BUS ADDRESS TABLE

Slave address (8C): Write mode
Sub address definition

Table 16. I2C Bus Address Table

D8 D7 D6 D5 D4 D3 D2 D1
0 0 0 0 0 0 0 0 0 Horizontal drive selection/horizontal duty cycle
1 0 0 0 0 0 0 0 1 Horizontal position
2 0 0 0 0 0 0 1 0 Forced Frequency/free running frequency
3 0 0 0 0 0 0 1 1 Synchro priority/horizontal moire amplitude
4 0 0 0 0 0 1 0 0 Refresh/B+ reference adjustment
5 0 0 0 0 0 1 0 1 Vertical ramp amplitude
6 0 0 0 0 0 1 1 0 Vertical position adjustment
7 0 0 0 0 0 1 1 1 S correction
8 0 0 0 0 1 0 0 0 C correction
9 0 0 0 0 1 0 0 1 E/W keystone

A 0 0 0 0 1 0 1 0 E/W amplitude
B 0 0 0 0 1 0 1 1 E/W corner adjustment
C 0 0 0 0 1 1 0 0 Vertical moire amplitude
D 0 0 0 0 1 1 0 1 Side pin balance
E 0 0 0 0 1 1 1 0 Parallelogram

F 0 0 0 0 1 1 1 1 Vertical dynamic focus amplitude

Slave address (8D): Read mode
No sub address needed

20

KB2512 DEFLECTION PROCESSOR FOR MULTISYNC MONITORS

Table 17. I2C Bus Address Table (continued)

D8 D7 D6 D5 D4 D3 D2 D1

WRITE MODE

00 HDrive

01 Xray

1: reset

[0]

02 Forced frequency Free running frequency

1: on

[0]: off

03 Sync

0: comp

[1]: sep

04 Detect

refresh

[0]: off

05 Vramp

0: off

[1]: on

06 Vertical position adjustment

07 S Select

1: on

[0]

08 C Select

1: on

[0]

09 EW key

0: off

[1]

0A East/west amplitude

0B E/W cor

0: off

[1]

0C Test V

1: on

[0]: off

0D SPB sel

0: off

[1]

0E Parallelogram

0: off

[1]

0F Test H

1: on

[0]: off

00 Hlock

0: on

[1]: no

0: off

[1]: on

[1] [0] [0] [0] [0] [0] [0]

1: F0x2

[0]: F0x3

HMoire

1: on

[0]

[1] [0] [0] [0] [0] [0] [0]

[1] [0] [0] [0] [0] [0] [0]

[1] [0] [0] [0] [0] [0] [0]

[1] [0] [0] [0] [0] [0]

[1] [0] [0] [0] [0] [0]

[1] [0] [0] [0] [0] [0]

[1] [0] [0] [0] [0] [0] [0]

[1] [0] [0] [0] [0] [0] [0]

Vmoire

1: on

[0]

[1] [0] [0] [0] [0] [0]

[1] [0] [0] [0] [0] [0]

[1] [0] [0] [0] [0] [0]

Vlock

0: on

[1]: no

Xray

1: on

[0]: off

[0] [0] [0] [0] [0]

Horizontal phase adjustment

[0] [0] [0] [0] [0]

[0] [0] [0] [0] [0]

Vertical ramp amplitude adjustment

East/west corner adjustment

[0] [0] [0] [0] [0]

Vertical dynamic focus amplitude

READ MODE

Polarity detection Synchro detection

H/V pol

[1], negative

[1], negative

Horizontal duty cycle

Horizontal moire amplitude

B+ reference adjustment

S correction

C correction

East/west keystone

Vertical moire

Side pin balance

Parallelogram

V pol

Vext det

[0], no det

H/V det

[0], no det

V det

[0], no det

[ ] initial value
Set the unspecified bit to [0] in order to assure the compatibility with future devices.

21

DEFLECTION PROCESSOR FOR MULTISYNC MONITORS KB2512

OPERATING DESCRIPTION

GENERAL CONSIDERATIONS
Power Supply

The typical values of the power supply voltages Vcc and VDD are respectively 12V and 5V. Perfect operation is
obtained if Vcc and VDD are maintained in the limits: 10.8 to 13.2V and 4.5 to 5.5V.
In order to avoid erratic operation of the circuit during the transient phase of Vcc and VDD switching on, or switching
off, the value of Vcc and V
typically.
In the same manner, VDD is monitored and internal set-up is made until VDD reaches 4V (see I2C control table for
power on reset).

In order to have a very good power supply rejection, the circuit is internally powered by several internal voltage
references (the typical value is 8V). Two of these voltage references are externally accessible, one for the vertical
part and on one for the horizontal one. If needed, these voltage references can be used (until I
5mA). Furthermore it is necessary to filter the a.m. voltage references by the use of external capacitor connected to
ground, in order to minimize the noise and consequently the “jitter” on vertical and horizontal output signals.

I2C Control

are monitored and the outputs of the circuit are inhibited if Vcc is less than 7.5V

DD

is less than

load

KB2512 belongs to the I2C controlled device family, instead of being controlled by DC voltage on dedicated control
pins, each adjustment can be realized through the I2C interface. The I2C bus is a serial bus with a clock and a data
input. The general function and the bus protocol are specified in the Phillips-bus data sheets.

The interface (data and clock) is TTL-level compatible. The internal threshold levels of the input comparator are

2.2V on rising edge and 0.8V on falling edge (when VDD is 5V). Spikes of up to 50ns are filtered by an integrator
and maximum clock speed is limited to 400kHz.

The data line (SDA) can be used in a bidirectional way that means in read-mode the IC clocks out a reply
information (1byte) to the micro-processor.
The bus protocol prescribes always a full-byte transmission. The first byte after the start condition is used to
transmit the IC-address (hexa 8C for write, 8D for read).

Write Mode

In write mode the second byte sent contains the sub address of the selected function to adjust (or controls to affect)
and the third byte the corresponding data byte. It is possible to send more than one data byte to the IC. If after the
third byte no stop or start condition is detected, the circuit increments automatically the momentary sub address in
the sub address counter by one (auto-increment mode). So it is possible to transmit immediately the next data
bytes without sending the IC address or sub address. It can be useful so as to reinitialize the whole controls very
quickly (flash manner). This procedure can be finished by a stop condition.

The circuit has 16 adjustment capabilities: 3 for horizontal part, 4 for vertical one, 2 for E/W correction, 2 for the
dynamic horizontal phase control, 1 for moire option, 3 for horizontal and vertical dynamic focus and 1 for B+
reference adjustment.
17 bits are also dedicated to several controls (on/off, horizontal forced frequency, sync priority, detection refresh
and XRAY reset).

22

KB2512 DEFLECTION PROCESSOR FOR MULTISYNC MONITORS

Read Mode

During read mode the second byte transmits the reply information.
The reply byte contains horizontal and vertical lock/unlock status, the XRAY activated or not, the horizontal and
vertical polarity detection. It also contains the Synchro detection status which is used by the MCU to assign sync
priority.
A stop condition always stops all the activities of the bus decoder and switches to high impedance both the data
and the clock line (SDA and SCL) .
See I2C sub address and control tables.

Sync processor

The internal sync processor allows the KB2512 to accept any kind of input Synchro signals:

• Separated horizontal & vertical TTL-compatible sync signals,

• Composite horizontal & vertical TTL-compatible sync signals.

Sync identification Status

The MCU can read (address read mode: 8D) the status register via the I2C bus, and then select the sync priority
depending on this status.
Among other data this register indicates the presence of sync pulses on H/HVIN, VSYNCIN and (when 12V is
supplied) whether a Vext has been extracted from H/HVIN. Both horizontal and vertical sync are detected even if
only 5V is supplied.

In order to choose the right sync priority the MCU may proceed as follows (see I2C address Table):

• Refresh the status register,

• Wait at least for 20ms(max. vertical period),

• Read this status register,

Sync priority choice should be:

Vext Det H/V Det V Det Sync Priority Subaddress 03 (D8) Comment Sync Type

No Yes Yes 1 Separated H & V

Yes Yes No 0 Composite TTL H & V

Of course, when choice is made, one can refresh the sync detections and verify that extracted Vsync is present
and that no sync change occurred.
The Sync processor is also giving sync polarity information.

IC status

The IC can inform the MCU about the 1st horizontal PLL and vertical section status, and about the XARY
protection (activated or not). Resetting the XRAY internal latch can be done either by decreasing the Vcc supply or
directly resetting it via the I2C interface.

23

DEFLECTION PROCESSOR FOR MULTISYNC MONITORS KB2512

Sync Inputs

Both H/HVin and Vsyncin inputs are TTL compatible trigger with Hysteresis to avoid erratic detection.
Both inputs include a pull up register connected to VDD.

Sync Processor Output

The sync processor indicates on the HLOCKOUT Pin whether 1st PLL is locked to an incoming horizontal sync.
HLOCKOUT is a TTL compatible CMOS output. Its level goes to high when locked. In the same time the D8 bit of
the status register is set to 0. This information is mainly used to trigger safety procedures (like reducing B+ value)
as soon as a change is detected on the incoming sync. Further to this, it may be used in an automatic procedure
for free running frequency(fo) adjustment.

Sending the desired fo on the sync input and progressively decreasing the free running frequently I2C register
value (address 02), the HLOCKOUT Pin will go high as soon as the proper setting is reached. Setting the free
running frequency this way allows to fully exploit the KB2512 horizontal frequency range.

HORIZONTAL PART
Internal input conditions

Horizontal part is internally fed by Synchro processor with a digital signal corresponding to horizontal Synchro
pulses or to TTL composite input.
concerning the duty cycle of the input signal, the following signals (positive or negative) may be applied to the
circuit.

Using internal integration, both signals are recognized on condition that Z/T < 25%, Synchronization occurs on the
leading edge of the internal sync signal. The minimum value of Z is 0.7µs.

Z

T

Z

An other integration is able to extract vertical pulse of composite Synchro if duty cycle is more than 25% (typically
d = 35%)

(see 7)

c

TRAMEXT

d

d

The last feature performed is the equalizing pulses removing to avoid parasitic pulse on phase comparator input
which is intolerant to wrong or missing pulse.

24

KB2512 DEFLECTION PROCESSOR FOR MULTISYNC MONITORS

PLL1

The PLL1 is composed of a phase comparator, an external filter and a voltage control oscillator (VCO).
The phase comparator is a phase frequency type designed in CMOS technology. This kind of phase detector
avoids locking on false frequencies. It is followed by a charge pump, composed of two current sources sunk and
sourced (I = 1mA typ. when locked, I = 140µA when unlocked). This difference between lock/unlock permits a
smooth catching of horizontal frequency by PLL1. This effect is reinforced by an internal original slow down system
when PLL1 is locked avoiding horizontal too fast frequency change.

The dynamic behavior of the PLL is fixed by an external filter which integrates the current of the charge pump.
A CRC filter is generally used (see Figure 4)

PLL1F

7

1.8KΩ

4.7uF 1uF

Figure 4. PLL1

PLL1 is internally inhibited during extracted vertical sync (if any) to avoid taking in account missing pulses or wrong
pulse on phase comparator. The inhibition results from the opening of a switch located between the charge pump
and the filter (see Figure 5).

The VCO uses an external RC network. It delivers a linear sawtooth obtained by charge and discharge of the
capacitor, by a current proportional to the current in the resistor. Typical thresholds of sawtooth are 1.6V and 6.4V.

PLL1F R0 C0

I2C

Forced

Frequency

PLL

7 6 5

VCO

I2C
Hpos
Adj.

OSC

HSYNC

H-LOCKOUT

3

Lockdet

1

Input

Interface

Tramext

Comp1

E2

High

Low

Lock/Unlock

Status

Charge

PUMP

Phase
Adjust

Tramext

Inhibition

Figure 5. Block Diagram

25

DEFLECTION PROCESSOR FOR MULTISYNC MONITORS KB2512

6.4V

1.6V

6.4V

1.6V

+

+

-

-

RS

Flip

Flop

0.84T0 T

Loop

7

Filter

(1.3V < V7 < 6V)

I2C Free running

Adjustment

+

-

(0.80<a<1.30)

6

R0

I

D

2

a

I

D

4 I

0

2

5

Co

Figure 6. Details of VCO

The control voltage of the VCO is typically comprised between 1.33V and 6V (see figure 6). The theoretical
frequency range of this VCO is in the ratio 1 to 4.5, the effective frequency range has to be smaller 1 to 4.2 due to
clamp intervention on filter lowest value. To avoid spread of external components and the circuit itself, it is possible
to adjust free running frequency through I2C. This adjustment can be made automatically on the manufacturing line
without manual operation by using lock/unlock information. The adjustment range is 0.8 to 1.3 F0 (where 1.3 F0 is
the free running frequency at power on reset).

The sync frequency has to be always higher than the free running frequency. As an example for a Synchro range
from 24kHz to 100kHz, the suggested free running frequency is 23kHz.
Another feature is the capability for MCU to force horizontal frequency throw I2C to 2xF0 or 3xF0 (for burn in mode
or safety requirement). In this case, inhibition switch is opened leaving PLL1 free but voltage on PLL1 filter is
forced to 2.66V for 2xF0 or 4.0V for 3xF0.

The PLL1 ensures the coincidence between the leading edge of the Synchro signal and a phase reference
obtained by comparison between the sawtooth of the VCO and an internal DC voltage I2C adjustable between

2.8V and 4.0V (corresponding to ±10%) (see Figure 7)

H osc
Sawtooth

7/8T

H

1/8T

H

6.4V

2.8V < Vb < 4.0V
Vb

Phase REF1 is obtained by compari­son between the sawtooth and a DC
voltage adjustable between 2.8V and

4.0V. The PLL1 ensures the exact
coincidence between the signals

Phase REF1

H Synchro

1.6V

phase REF and Hsyns. A ±TH/10
phase adjustment is possible

Figure 7. PLL1 Timing Diagram

26

KB2512 DEFLECTION PROCESSOR FOR MULTISYNC MONITORS

The KB2512 also includes a lock/unlock identification block which senses in real time whether PLL1 is locked or
not on the incoming horizontal sync signal. The resulting information is available on Hlockout (see sync processor).
The block function is described in figure 5.
When PLL1 is unlocked, It forces Hlockout to leave high.
The lock/unlock information is also available throw I2C read.

PLL2

The PLL2 ensures a constant position of the shaped Flyback signal in comparison with the sawtooth of the VCO
(Figure 8). The phase comparator of PLL2 (phase type comparator) is followed by a charge pump (typical output
current:0.5mA). The Flyback input is composed of an NPN transistor. This input must be current driven. The
maximum recommended input current is 5mA (see Figure 9).

The duty cycle is adjustable through I2C from 30% to 60%. For start up safe operation, initial duty cycle (after
power on reset) is 60% in order to avoid having a too long conduction period of the horizontal scanning transistor.
The maximum storage time (Ts max.) is (0.44TH-T
max is around 34% of TH.

H osc
Sawtooth

/2). Typically, T

FLY

7/8T

H

1/8T

/TH is around 20% which means that Ts

FLY

H

6.4V

3.7V

Flyback
Internally
Shaped Flyback

H drive

Ts

Duty Cycle

Figure 8. PLL2 Timing Diagram

HFLY

12

20KΩ

GND 0V

1.6V

400Ω

Q1

Figure 9. Flyback Input Electrical Diagram

27

DEFLECTION PROCESSOR FOR MULTISYNC MONITORS KB2512

Output Section

The H-drive signal is transmitted to the output through a shaping block ensuring TS and I2C adjustable duty cycle.
In order to secure scanning power part operation, the output is inhibited in the following circumstances:

• Vcc and VDD too low

• XRAY protection activated

• During horizontal Flyback

• H Drive I2C bit control is off.

The output stage is composed of a NPN bipolar transistor. Only the collector is accessible (see Figure 10).

26 H-DRIVE

Figure 10. Output Section

The output NPN is in off-state when the power scanning transistor is also in off-state.
The maximum output current is 30mA, and the corresponding voltage drop of the output V

is 0.4V Max.

CEsat

It is evident that the power scanning transistor cannot be directly driven by the integrated circuit. An interface has
to be designed between the circuit and the power transistor which can be of bipolar or MOS type.

X-RAY Protection

The activation of the X-ray protection is obtained by application of a high level on the X-ray input (8V on pin 25). It
inhibits the H-drive and B+ outputs.
This protection is latched; It may be reset either by Vcc or VDD switch off or by I2C (see Figure 11).

Vertical Dynamic Focus

The KB2512 delivers a vertical parabola wave from on pin 10. Vertical dynamic focus is tracked with VPOS and
VAMP. Its amplitude can be adjusted. It is also affected by S and C corrections. This positive signal once amplified
has to be connected to the CRT focusing grids.

28

KB2512 DEFLECTION PROCESSOR FOR MULTISYNC MONITORS

VSCinh

VSDinh

VCC or VDD off

VERTICAL PART
Geometric Corrections

VCC Checking

V

CC

VDD Checking

V

DD

Horizontal Flyback

-

+

+

-

XRAY

or I2C Reset

0.7V

Figure 11. Safety Functions Block Diagram

XRAY Protection

S

Q

R

­+

I2C Drive on/off

I2C Ramp on/off

Horizontal
Output
Inhibition

Vertical
Output
Inhibition

Bout

The principle is represented in Figure 12.

2

V

Vertical Ramp V

DCMID

(3.5V)

OUT

23

Parabola

Generator

Figure 12. Geometric Corrections Principle

V.Focus amp

I

2

V

DCMID

(3.5V)

V

DCMID

(3.5V)

EW + amp

Corner

Keystone

Side pin amp

Parallelogram

10

+

24

To Horizontal

+

Phase

Dynamic Focus

+

EW Output

Side pin Balance

Output Current

29

DEFLECTION PROCESSOR FOR MULTISYNC MONITORS KB2512

Starting from the vertical ramp, a parabola shaped current is generated for E/W correction, dynamic horizontal
phase control correction, and vertical dynamic focus correction.
The base of the parabola generator is an analog multiplier, the output current of which is equal to:

∆I = k × (V

OUT

- V

Where Vout is the vertical output ramp (typically between 2 and 5V) and V
more multiplier provides a current proportional to (Vout - V

DCMID

2

)

is 3.5V (for V

)4 for corner correction The VOUT sawtooth is

DCMID

DCMID

REF-V

= 8V). One

typically centered on 3.5V. By changing the vertical position, the sawtooth shifts by ±0.3V.
In order to keep a good screen geometry for any end user preference adjustment we implemented the geometry
tracking.

Due to large output stages voltage range (E/W, keystone corner), the combination of tracking function with
maximum vertical amplitude max or min vertical position and maximum gain on the DAC control may lead to the
output stages saturation. This must be avoided by limiting the output voltage by appropriate I2C registers values.
For E/W part and dynamic horizontal phase control part, a sawtooth shaped differential current in the following
form is generated:

∆I’ = k’ × (V

OUT

- V

DCMID

2

)

Then ∆I and ∆I’are added together and converted into voltage for the E/W part.
Each of the three E/W components and the two dynamic horizontal phase control ones may be inhibited by their
own I2C select bit.
The E/W parabola is available on pin 24 by the way of an emitter follower which has to be biased by an external
resistor (10KΩ). It can be DC coupled with external circuitry.

The vertical dynamic focus is available on output pin 10. Dynamic horizontal phase control current drives internally
the H-position, moving the Hfly position on the horizontal sawtooth in the ± 1.4% The both on side pin balance and
parallelogram.

EW

EWOUT = 2.5V + K1 (V

OUT

- V

DCMID

) + K2 (V

OUT

- V

)2 + K3 (Vout - V

DCMID

DCMID

)4
K1 is adjustable by the keystone I2C register
K2 is adjustable by the EW amplitude I2C register
K3 is adjustable by the corner I2C register

Dynamic Horizontal Phase Control

IOUT = K4 (V

OUT

- V

DCMID

) 2 + K5 (V

OUT

- V

DCMID

)
K4 is adjustable by side pin balance I2C register
K5 is adjustable by parallelogram I2C register.

Function

When the Synchronization pulse is not present, an internal current source sets the free running frequency. For an
external capacitor, C

= 150nF, the typical free running frequency is 100Hz.

OSC

Typical free running frequency can be calculated by:

5–

foHz()1.510

1

--------------⋅⋅=

C

OSC

30

KB2512 DEFLECTION PROCESSOR FOR MULTISYNC MONITORS

A negative or positive TTL level pulse applied on pin 2 (VSYNC) as well as a TTL composite sync on pin 1 can
Synchronize the ramp in the range [fmin, fmax]. This frequency range depends on the external capacitor
connected on pin 22. A capacitor in the range [150nF, ± 5%] is recommended for application in the following range:
50Hz to 185Hz.
Typical maximum and minimum frequency, at 25°C and without any correction (S correction or C correction), can
be calculated by:

f

= 3.5 × fo and f

(Max.)

If S or C corrections are applied, these values are slightly affected.
If a Synchronization pulse is applied, the internal oscillator is Automatically caught but the amplitude is no more
constant. An internal correction is activated to adjust it in less than a half a second: the highest voltage of the ramp
pin 22 is sampled on the sampling capacitor connected on pin 20 at each clock pulse and a transconductance
amplifier generates the charge current of the capacitor. The ramp amplitude becomes again constant.

The read status register enables to have the vertical lock-unlock and the vertical sync polarity informations.
It is recommended to use a AGC capacitor with low leakage current. A value lower than 100nA is mandatory.
A good stability of the internal closed loop is reached by a 470nF ± 5% capacitor value on pin 20 (VAGC)

= 0.33 × fo

(Min.)

2

V-SYNC

SYNCHRO OSCILLATOR

POLARITY

Figure 13. AGC Loop Block Diagram

DISCH.

CHARGE CURRENT

-

22

+

SAMPLING

OSC
CAP

-

+

TRANSCONDUCTANCE

AMPLIFIER

REF

20

Vlow

SAMP
CAP

S CORRECTION

C CORRECTION

Switch

Diech

VS_AMP
SUB07/6bits

COR-C
SUB08/6bits

23
18

VERT_AMP
SUB05/7BITS

VMOIRE
SUB0C/5BITS

VOSITION
SUB06/7BITS

VOUT

BREATH

31

DEFLECTION PROCESSOR FOR MULTISYNC MONITORS KB2512

I2C Control Adjustments

Then, S and C correction shapes can be added to this ramp. This frequency independent S and C corrections are
generated internally. Their amplitude are adjustable by their respective I2C register. They can also be inhibited by
their select bit. The amplitude of this S and C corrected ramp can be adjusted by the vertical ramp amplitude
control register. The adjusted ramp is available on pin 23 (VOUT) to drive an external power stage. The gain of this
stage is typically 25% depending on its register value. The mean value of this ramp is driven by its own I2C register
(vertical position). Its value is VPOS = 7/16 • V
Usually VOUT is sent through a resistive divider to the inverting input of the booster. Since VPOS derives from
V

, the bias voltage sent to the non-inverting input of booster should also derive from V

REF-V

accuracy (see application diagram).

Basic Equations

In first approximation, the amplitude of the ramp on pin 23 (Vout) is:
V

- VPOS = (V

OUT

OSC

- V

) • (1 + 0.25 (V

DCMID

with:

• V

• V

= 7/16•V

DCMID

= V22 (ramp with fixed amplitude)

OSC

(typically 3.5V, the middle value of the ramp on pin 22)

REF

• VAMP = - 1 for minimum vertical amplitude register value and +1 for maximum

• VPOS is calculated by: VPOS = V

DCMID

and +1 for maximum

± 300mV.

REF

to optimize the

REF-V

) )

AMP

+ 0.3Vp with Vp equals -1 for minimum vertical position register value

The current available on pin 22 is:

I

OSC

with C

3

= • V

8

: capacitor connected on pin 22

OSC

REF

• C

OSC

• f

f: synchronization frequency.

Vertical Moire

By using the vertical moire, VPOS can be modulated from frame to frame. This function is intended to cancel the
fringes which appear when line to line interval is very close to the CRT vertical pitch. The amplitude of the
modulation is controlled by register VMOIRE on address OC and can be switched - off via the control bit D7.

32

KB2512 DEFLECTION PROCESSOR FOR MULTISYNC MONITORS

DC/DC CONVERTER PART

This unit controls the switch-mode DC/DC converter. It converts a DC constant voltage into the B+ voltage(roughly
proportional to the horizontal frequency) necessary for the horizontal scanning. This DC/DC converter must be
configured in step-up mode. It operates very similarly to the well known UC3842.

Step-up Mode

Operating description

• The power MOS is switched-on at the middle of the horizontal Flyback.

• The power MOS is switched-off when its current reaches predetermined value. For this purpose, a sense
resistor is inserted in its source. The voltage on this resistor is sent to pin16 (ISENSE).

• The feedback (coming either from the EHV or from the Flyback) is divided to a voltage close to 4.8V and com­pared to the internal 4.8V reference (IVREF). The difference is amplified by an error amplifier, the output of
which controls the power MOS switch-off current.

Main Features

• Switching synchronized on the horizontal frequency

• B+ voltage always higher than the DC source

• Current limited on a pulse-by-pulse basis

• The DC/DC converter is disabled:

- When VCC or VDD are too low,

- When X-Ray protection is latched,

- Directly through I2C bus.

• When disabled, BOUT is driven to GND by a 0.5mA current source. This feature allows to implement externally
a soft start circuit.

33

DEFLECTION PROCESSOR FOR MULTISYNC MONITORS KB2512

8V

DAC

adjust

4.8V

± 20%

+
95dB

A

-

Soft
start

Inhibit SMPS

7bits

±I

I2C

+

s

-

1.2V

1/3

1.2V

­C2

+

­C3

+

400ns

S

Q

R

Inhibit SMPS

12V

BOUT

28

COMPREGIN

15 14 16

1MΩ

+

22KΩ

V

B+

L

Figure 14. DC/DC Converter Part

I

SENSE

34

KB2512 DEFLECTION PROCESSOR FOR MULTISYNC MONITORS

APPLICATION BOARD CIRCUIT

VCC=12V

HSYNC

VSYNC

2

AFC

AFC

22K

22K

4.7uF 50V
10nF 100V MP

50K

50K

1K

1K

22nF 100V

1% P

820pF 50V

6.8K

1.8K

+

1uF

2K

10K

4.7uF

0.1uF

+

1M

33K

3.3K

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

HSYNC_IN

VSYNC_IN

H_LOCKOUT

PLL2C

CO

RO

PLL1F

H_LOCKCAP

H MOIRE

FOCUS

HGND

HFLY

H_REF

COMP

REGIN

I_SENSE

KB2512

SDA

SCL

VCC

B+OUT

GND

H_OUT

XRAY

EWOUT

VOUT

VSCAP

V_REF

VAGCCAP

VGND

HBLKOUT

B+GND

5V

32

5V

+

0.1uF

100uF

31

100

30

29

+

100uF

28

27

26

25

24

23

150nF 100V

22

21

470nF 63V P

20

19

18

17

100

10K

10K

1% P

0.1uF

1K

50K

10K

SDA

SCL

22K

10K

+

47uF
50V

HOUT

0.1uF

1K

50K

1K

1

SCLK

2

SDAT

3

ACK

4

1

2

3

4

5

6

7

74HCT125

5V

14

13

12

11

10

9

8

12V

100K

0.1uF+100uF

SCL

SDA

Figure 15. Application Circuit

35

HOUT

47pF

1

2

3

4

5

6

7

8

MC14528

16

47pF

15

14

13

12

11

10

9

10K
33pF

100K

AFC