• Output Current up to 1A with External Transistor
(output3)
• Fixed Precision Output 1 voltage 3.3V ± 2%
• Fixed Precision Output 2 voltage 8V ± 2% (KA7632)
• Fixed Precision Output 2 voltage 9V ± 2% (KA7633)
• Control Signal Generator for Output 3 voltage (5.1V ± 2%)
• Reset Facility for Output Voltage1
• Output 2,3 wit h Disable by TTL Input
• Current Limit Protection at Each Output
• Thermal Shut Down
Internal Block Diagram
Vin1
10uA
-
+
SW
-
+
SCP
Output
Cd
100nF
A614"Y"
DEL.CAP
3
6
RESET
Vsys
10K
7
Control
10
Output3
Description
The KA7632/KA7633 is a multi-output positive voltage
regulator des igned to provide fix e d pr e ci si on output voltages
of 3.3V, 8V (KA7632) / 9V (KA7633) at current up to 0.5A
and 5.1V at current up to 1A with ex ternal PNP transistor.
An internal reset circuit g enerates a reset pulse when the
output 1 decrease below the regulated value. Output2 & 3
can be disabled by TTL input. Protection features include
over voltage protection, short circuit protection and thermal
shutdown.
DC Input VoltageVin20VDisable Input VoltageVc20VOutput Current Io0.5APower DissipationPd1.5WNo Heatsink
Junction TemperatureTj+150°C-
Operating TemperatureTopr0~+125°C-
Electrical Characteristics(KA7632)
(Refer to test circuit Vin1=6V ,Vin2=10.5V ,Tj = +25 °C, unless otherwise specified)
ParameterSymbolConditionsMin.Typ.Max.Unit
Io1=10mA
Output Voltage 1 Vo1
Output Voltage 2Vo2
Dropout Output Voltage 1,2Vd1,2Io1,2=500mA--2.5V
Line Regulation 1,2∆Vo 1,2
Load Regulation 1,2∆Vo 1,2
Output Voltage 3Vo3Vsys=7V, Io3=100mA4.975.15.23V
Line Regulation 3∆Vo313V< Vin2 <18V, Io3 =100mA--50mV
Load Regulation 3∆Vo35mA < Io3 < 1A--110mV
Reset Pulse DelayTrdCd=100nF, Note1-25-ms
Saturation Voltage in Reset
Condition
Leakage Current at Pin 6IrHV6=10V--10µA
Output Voltage Thermal DriftSTt0 °C <Tj < +125 °C , Note 2-100-ppm/°C
Short Circuit Output CurrentIsc1,2Vin1=6V ,Vin2 =10.5V--1.6A
Disable Voltage HighVdisHOutput 2 Active2-V
Disable Voltage LowVdisLOutput 2 Disabled--0.8V
Disable Bias CurrentIdis0V < Vdis < 7V-100-2µA
Junction Temperature for TSDTtsdNote 2-145-°C
Quiescent CurrentIqIo1=10mA, Output2 Disabled--2mA
Reset Threshold VoltageVrK=Vo1K-0.4K-0.25K-0.1V
Reset Threshold HysteresisVrthNote 12050100mA
VrLI6=5mA--0.4V
6V<Vin1<14V
5mA<Io1<500mA
Io2=10mA
10.5V<Vin2<18V
5mA<Io2<500mA
6V <Vin1<14V
10.5V <Vin2<18V
Io1,2 = 200mA
5mA < Io1< 500mA
5mA <Io2< 500mA
3.22
3.14
7.84
7.7
--
--
3.3
3.3
8
8
3.38
3.46
8.16
8.3
40
80
70
160
V
V
mV
mV
Notes:
1. To check the reset circuit ,the re set output is low to discharge th e d ela y c ap acitor(=Cd). if it’ s less than Vo1- 0.2 5V . A nd the
reset output is high when the delay capacitor voltage linearly increased by the interal current source(10µA) if it’s more than
Vo1- 0.2V. The equations of delay time is same as below. Trd = (Cd × 2.5) / 10µA
2. These parameters, although guaranteed, are not 100% tested in production.
2
Page 3
KA7632/KA7633
Electrical Characteristics(KA7633)
(Refer to test circuit Vin1=6V ,Vin2=11.5V ,Tj = +25 °C, unless otherwise specified)
ParameterSymbolConditionsMin.Typ.Max.Unit
Io1=10mA
Output Voltage 1 Vo1
6V<Vin1<14V
5mA<Io1<500mA
Io2=10mA
Output Voltage 2Vo2
11.5V<Vin2<18V
5mA<Io2<500mA
Dropout Output Voltage 1,2Vd1,2Io1,2=500mA--2.5V
6V <Vin1<14V
Line Regulation 1,2∆Vo 1,2
11.5V <Vin2<18V
Io1,2 = 200mA
Load Regulation 1,2∆Vo 1,2
5mA < Io1< 500mA
5mA <Io2< 500mA
Output Voltage 3Vo3Vsys=7V, Io3=100mA4.975.15.23V
Line Regulation 3∆Vo313V< Vin2 <18V, Io3 =100mA--50mV
Load Regulation 3∆Vo35mA < Io3 < 1A--110mV
Reset Pulse DelayTrdCd=100nF, Note1-25-ms
Saturation Voltage in Reset
Condition
VrLI6=5mA--0.4V
Leakage Current at Pin 6IrHV6=10V--10µA
Output Voltage Thermal DriftSTt0 °C <Tj < +125 °C , Note 2-100-ppm/°C
Short Circuit Output CurrentIsc1,2Vin1=6V ,Vin2 =11.5V--1.6A
Disable Voltage HighVdisHOutput 2 Active2-V
Disable Voltage LowVdisLOutput 2 Disabled--0.8V
Disable Bias CurrentIdis0V < Vdis < 7V-100-2µA
Junction Temperature for TSDTtsdNote 2-145-°C
Quiescent CurrentIqIo1=10mA, Output2 Disabled--2mA
Reset Threshold VoltageVrK=Vo1K-0.4K-0.25K-0.1V
Reset Threshold HysteresisVrthNote 12050100mA
3.22
3.14
8.82
8.65
3.3
3.3
9
9
--
--
3.38
3.46
9.18
9.35
40
80
70
160
mV
mV
V
V
Notes:
1. To check the reset circuit ,th e re set output is l ow to discharge the delay capacitor(= Cd ). if it’s less than V o1 -0.2 5V . And the
reset output is high when the delay capacitor voltage linearly increased by the interal current source(10µA) if it’s more than
Vo1- 0.2V. The equations of delay time is same as below. Trd = (Cd × 2.5) / 10µA
2. These parameters, although guaranteed, are not 100% tested in production.
3
Page 4
KA7632/KA7633
Typical Perfomance Characteristics
2.0
TJ = 25oC
Io1 =10mA
1.6
1.2
0.8
0.4
Quiescent current Iq( mA)
0
0155
10
20
Input voltage Vin (V)
Input Voltage Vi n (V)
Figure 1. Quiescent Current vs. Input Vo ltage
14
12
10
8
6
4
Output voltage2 Vo(V)
2
0
0
TJ = 25oC
2
Io1 =10mA
10.5V<Vin1<18V
5mA<Io1<500mA
1015
2
2
205
Input voltage Vin (V)
7
6
5
4
3
2
Output voltage1 Vo(V)
1
TJ = 25oC
Io1 =10mA
6
7.5V<Vin1<14V
5mA<Io1<500mA
0
0
1015
Input Voltage Vin (V)
205
Figure 2. Output Voltage1 vs. Input Voltage
14
12
10
8
6
4
Output volt age Vo(V )
2
0
030.5
1.5
122.5
Disable Voltage ( V)
Figure 3. Output Voltage2 vs. Input Voltage
40
30
20
10
Disable Bias Current( uA)
0
0 0.4 0.8 1.2 1.6 2.0
Disable Voltage(V)
Figure 5. Disable Bias Current vs. Disable Voltage
4
Figure 4. Output Voltage vs. Disable Voltage High(Low)
5.105
5.10
5.095
5.09
5.085
5.08
Output voltage1 Vo(V)
5.075
5.07
02550
-25
Temperature Tj(
75
℃
100
125
)
Figure 6. Output Voltage1 vs. Temperature(Tj)
Page 5
Typical Perfomance Characteristics (continued)
8.07
8.06
8.05
8.04
8.03
8.02
8.01
KA7632/KA7633
8.00
02550
-25
75
100
125
150
Temperature Tj(℃)
Figure 7. Output Voltage2 vs. Temperature(Tj)
5
Page 6
KA7632/KA7633
Mechanical Dimensions
Package
#1
MAX
10-SIP H/S
1.50
0.059
()
Dimensions in millimeters
3.25 ±0.20
0.128 ±0.008
#10
25.75 ±0.10
1.013 ±0.004
26.05
1.026
0.50 ±0.10
0.020 ±0.004
0.50 ±0.10
1.30 ±0.10
0.051 ±0.004
2.54
0.100
1.30
0.051
()
1.65 ±0.10
0.065 ±0.004
0.020 ±0.004
7.00 ±0.30
0.276 ±0.012
1.00 ±0.20
0.039 ±0.008
8.90 ±0.20
0.350 ±0.008
13.65 ±0.30
0.537 ±0.012
16.80
0.661
MAX
23.86 ±0.20
3.80 ±0.20
0.939 ±0.008
0.150 ±0.008
6
Page 7
Ordering Information
Product NumberPackageOperating Temperature
KA7632
KA7633
10-SIP H/S0°C to +125°C
KA7632/KA7633
7
Page 8
KA7632/KA7633
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURT HER NOTICE TO ANY
PRODUCTS HEREI N TO IMPROVE RELIABILITY, FUNCTIO N OR DESIGN. FAIRCH IL D DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER
DOES IT CONVEY ANY LICENSE UNDER IT S PATENT RIGHTS, NOR THE RIGHTS OF OTHE RS.
LIFE SUPPORT POL I CY
FAIRCHILD’S PR ODUCTS ARE NOT AUTH ORIZED FOR USE AS C RITICAL COMPONENT S IN LIFE SUPPORT DE VICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein :
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with
2. A critical component in any component of a life support
device or sy stem whose fai lure to perform can be
reasonably expec ted to cause the failur e of the life support
device or system, or to affect its safety or effec t iv ene ss .
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.
www.fairchildsemi.com
8/1/01 0.0m 001
2001 Fairchild Semiconductor Corporation
Stock#DSxxxxxxxx
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