Datasheet KA555ID, KA555I, KA555D, KA555 Datasheet (Fairchild Semiconductor)

©2002 Fairchild Semiconductor Corporation

www.fairchildsemi.com

Rev. 1.0.2

Features

• High Current Drive Capability (200mA)

• Adjustable Duty Cycle

• Temperature Stability of 0.005%/°C

• Timing From Msec to Hours

• Turn Off Time Less Than 2Msec

Applications

• Precision Timing

• Pulse Generation

• Time Delay Generation

• Sequential Timing

Description

The KA555 is a highly stable controller capable of
producing accurate timing pulses. With monos table
operation, the time delay is controlled by one external
resistor and one capacitor. With astable operation, the
frequency and duty cycle are accurately controlled with two
external resistors and one capacitor.

8-DIP

8-SOP

1

1

Internal Block Diagram

F/F

OutPut

Stage

1

7

5

2

3

4

6

8

RRR

Comp.

Comp.

Discharging Tr.

Vref

Vcc

Discharge

Threshold

Control
Voltage

GND

Trigger

Output

Reset

KA555

Single Timer

KA555

2

Absolute Maximum Ratings (T

A

= 25°°°°C)

Parameter Symbol Value Unit

Supply Voltage V

CC

16 V

Lead Temperature (Soldering 10sec) T

LEAD

300 °C

Power Dissipation P

D

600 mW

Operating Temperature Range
KA555/KA555I

T

OPR

0 ~ +70 / -40 ~ +85 °C

Storage Temperature Range T

STG

- 65 ~ +150 °C

KA555

3

Electrical Characteristics

(TA = 25°C, V

CC

= 5 ~ 15V, unless otherwise specified)

Notes:

1. Supply current when output is high is typically 1mA less at V

CC

= 5V

2. Tested at V

CC

= 5.0V and V

CC

= 15V

3. This will determin e maximum v alue of R

A

+ RB for 15V operation , the max . total R = 20MΩ, and for 5V op eratio n the ma x. total

R = 6.7MΩ

Parameter Symbol Conditions Min. Typ. Max. Unit

Supply Voltage V

CC

-4.5-16V

Supply Current *

1

(Low Stable) I

CC

VCC = 5V, RL = ∞ -36 mA
V

CC

= 15V, RL = ∞ -7.515 mA

Timing Error *

2

(Monos Table)
Initial Accuracy
Drift with Temperature
Drift with Supply Voltage

ACCUR

∆t/∆T

∆t/∆V

CC

RA = 1KΩ to100KΩ
C = 0.1µF

-1.0
50

0.1

3.0

0.5

%

ppm/°C

%/V

Timing Error *

2

(Astable)
Initial Accuracy
Drift with Temperature
Drift with Supply Voltage

ACCUR

∆t/∆T

∆t/∆V

CC

RA = 1KΩ to 100KΩ
C = 0.1µF

-

2.25
150

0.3

-%
ppm/°C

%/V

Control Voltage V

CC

VCC = 15V 9.0 10.0 11.0 V
V

CC

= 5V 2.6 3.33 4.0 V

Threshold Voltage V

TH

VCC = 15 V - 10.0 - V
V

CC

= 5V - 3.33 - V

Threshold Current *

3

I

TH

- - 0.1 0.25 µA

Trigger Voltage

V

TR

V

CC

= 5V 1.1 1.67 2.2 V

V

CC

= 15V 4.5 5 5.6 V

Trigger Current I

TR

V

TR

= 0V 0.01 2.0 µA

Reset Voltage V

RST

- 0.4 0.7 1.0 V

Reset Current I

RST

- 0.1 0.4 mA

Low Output Voltage V

OL

VCC = 15V
I

SINK

= 10mA

I

SINK

= 50mA

-0.06

0.3

0.25

0.75

V
V

V

CC

= 5V

I

SINK

= 5mA

-

0.05 0.35 V

High Output Voltage V

OH

VCC = 15V
I

SOURCE

= 200mA

I

SOURCE

= 100mA 12.75

12.5

13.3

-V

V

V

CC

= 5V

I

SOURCE

= 100mA 2.75 3.3

-

V

Rise Time of Output t

R

- - 100 - ns

Fall Time of Output t

F

- - 100 - ns

Discharge Leakage Current I

LKG

- - 20 100 nA

KA555

4

Application Information

Table1 below is the basic operating table of 555 timer:

When the low signal input is applied to the reset terminal, the timer output remains low regardless of the threshold voltage or
the trigger voltage. Only when the high signal is applied to the reset terminal, timer's output changes according to threshold
voltage and trigger voltage.
When the threshold voltage exceeds 2/3 of the supply voltage while the timer output is high, the timer's internal discharge Tr.
turns on, lowering the threshold voltage to below 1/3 of the supply voltage. During this time, the timer output is maintained
low. Later, if a low signal is applied to the trigger voltage so that it becomes 1/3 of the supply voltage, the timer's internal
discharge Tr. turns off, increasing the threshold voltage and driving the timer output again at high.

1. Monos Table Operation

Table 1. Basic Operating Table

Threshold Voltage

(V

th

)(Pin6)

Trigger Voltage

(Vtr)(Pin2)

Reset(Pin4) Output(Pin3)

Discharging Tr.

(Pin7)

Don't care Don't care Low Low ON

V

th

> 2Vcc / 3 Vth > 2Vcc / 3 High Low ON

Vcc / 3 < V

th

< 2 Vcc / 3 Vcc / 3 < Vth < 2 Vcc / 3 High - -

V

th

< Vcc / 3 Vth < Vcc / 3 High High OFF

10-510-410-310-210-110010110

2

10

-3

10

-2

10

-1

10

0

10

1

10

2

10M

Ω

ΩΩ

Ω

1M

Ω

ΩΩ

Ω

10k

Ω

ΩΩ

Ω

100k

Ω

ΩΩ

Ω

R

A

=1k

Ω

ΩΩ

Ω

Capacitance(uF)

Time Delay(s)

Figure 1. Monoatable Circuit

Figure 2. Resistance and Capacitance vs.

Time delay(td)

Figure 3. Waveform s of Monostable Operation

1

5

6

7

8

4

2

3

RESET

Vcc
DISCH

THRES

CONT

GND

OUT

TRIG

+Vcc

R

A

C1

C2R

L

Trigger

KA555

5

Figure 1 illustrates a monos table circuit. In this mode, the timer generates a fixed pulse whenever the trigger voltage falls
below Vcc/3. When the trigger pulse voltage applied to the #2 pin falls below Vcc/3 while the timer output is low, the timer's
internal flip-flop turns the discharging Tr. off and causes the timer output to become high by charging the external capacitor
C1and setting the flip-flop output at the same time.
The voltage across the external capacitor C1, V

C1

increases exponentially with the time constant t=RA*C and reaches 2Vcc/3

at td=1.1R

A

*C. Hence, capacitor C1 is charged through resistor RA. The greater the time constant RAC, the longer it takes

for the V

C1

to reach 2Vcc/3. In other words, the time constant RAC controls the output pulse width.
When the applied voltage to the capacitor C1 reaches 2Vcc/3, the comparator on the trigger terminal resets the flip-flop,
turning the discharging Tr. on. At this time, C1 begins to discharge and the timer output converts to low.
In this way, the timer operating in monos table repeats the above process. Figure 2 shows the time constant relationship based
on R

A

and C. Figure 3 shows the general waveforms during monos table operation.
It must be noted that, for normal operation, the trigger pulse voltage needs to maintain a minimum of Vcc/3 before the timer
output turns low. That is, alth ough the output remains unaffected even if a different trigger pulse is applied while the output is
high, it may be affected and the waveform not operate properly if the trigger pulse voltage at the end of the output pulse
remains at below Vcc/3. Figure 4 shows such timer output abnormality.

2. Astable Operation

Figure 4. Waveforms of Monos table Operat ion (abnormal)

100m 1 10 100 1k 10k 100k

1E-3

0.01

0.1

1

10

100

10M

Ω

ΩΩ

Ω

1M

Ω

ΩΩ

Ω

100k

Ω

ΩΩ

Ω

10k

Ω

ΩΩ

Ω

1k

Ω

ΩΩ

Ω

(RA+2RB)

Capacitance(uF)

Frequency(Hz)

Figure 5. Astable Ci rcu it

Figure 6. Capac itance and Resist ance vs. Frequency

1

5

6

7

8

4

2

3

RESET

Vcc
DISCH

THRES

CONT

GND

OUT

TRIG

+Vcc

R

A

C1

C2R

L

R

B

KA555

6

An astable timer operation is achieved by adding resistor RB to Figure 1 and configuring as shown on Figure 5. In astable
operation, the trigger terminal and the threshold terminal are connected so that a self-trigger is formed, operating as a multi
vibrator. When the timer output is high, its internal discharging Tr. turns off and the V

C1

increases by exponential

function with the time constant (R

A+RB

)*C.

When the V

C1

, or the threshold voltage, reaches 2Vcc/3, the comparator output on the trigger terminal becomes high,
resetting the F/F and causing the timer output to become low. This in turn turns on the discharging Tr. and the C1 discharges
through the discharging channel formed by R

B

and the discharging Tr. When the VC1 falls below Vcc/3, the comparator
output on the trigger terminal becomes high and the timer output becomes high again. The discharging Tr. turns off and the
V

C1

rises ag ain.

In the above process, the section where the timer output is high is the time it takes for the V

C1

to rise from Vcc/3 to 2Vcc/3,

and the section where the timer output is low is the time it takes for the V

C1

to drop from 2Vc c/3 to Vc c/3. Wh en time r o utpu t

is high, the equivalent circuit for charging capacitor C1 is as follows:

Since the duration of the timer output high state(t

H

) is the amount of time it takes for the VC1(t) to reach 2Vcc/3,

Figure 7. Waveforms of Astable Operation

Vcc

R

A

R

B

C1 Vc1

(0-)=Vcc/

3

C

1

dv

c1

dt

−−−−−−−−

VccV0-()–

RAR

B

+

−−−−−−−−−−−−−−−−−−−

=

1()

VC10+() VCC3⁄= 2()

VC1t() VCC1

2
3

−−e

-

t

RAR

B

+()C1

−−−−−−−−−−−−−−−−−−−−−−

–







–











=

3()

KA555

7

The equivalent circuit for discharging capacitor C1 when timer output is low as follows:

Since the duration of the timer output low state(

t

L

) is the amount of time it takes for the VC1(t) to reach Vcc/3,

Since R

D

is normally RB >> RD although related to the size of discharging Tr.,

t

L

=0.693RBC

1

(10)

Consequently, if the timer operates in astable, the period is the same with
'T=t

H+tL

=0.693(RA+RB)C1+0.693RBC1=0.693(RA+2RB)C1' because the period is the sum of the charge time and discharge

time. And since frequency is the reciprocal of the period, the following applies.

3. Frequency divider

By adjusting the length of the timing cycle, the basic circuit of Figure 1 can be made to operate as a frequency divider. Figure

8. illustrates a divide-by-three circuit that makes use of the fact that retriggering cannot occur during the timing cycle.

VC1t()

2
3

−−V

CC

V=

CC

1

2
3

−−e

-

t

H

RAR

B

+()C1

−−−−−−−−−−−−−−−−−−−−−−

–







–











= 4()

tHC1RAR

B

+()In2 0.693 RAR

B

+()C

1

== 5()

C1

R

B

R

D

VC1(0-)=2Vcc/3

C

1

dv

C1

dt

−−−−−−−−−

1

RAR

B

+

−−−−−−−−−−−−−−V

C1

0=+ 6()

VC1t()

2
3

−−V
CC

e

-

t

RAR

D

+()C1

−−−−−−−−−−−−−−−−−−−−−−

= 7()

1
3

−−V

CC

2
3

−−V
CC

e

-

t

L

RARD+()C1

−−−−−−−−−−−−−−−−−−−−−−

= 8()

tLC1RBRD+()In2 0.693 RBRD+()C

1

== 9()

frequency, f

1
T

−−

1.44

RA2RB+()C

1

−−−−−−−−−−−−−−−−−−−−−−−−

== 11()

KA555

8

4. Pulse Width Modulation

The timer output waveform may be changed by modulating the control voltage applied to the timer's pin 5 and changing the
reference of the timer's internal comparators. Figure 9. illustrates the pulse width modulation circuit.
When the continuous trigger pulse train is applied in the monos table mode, the timer output width is modulated according to
the signal applied to the control terminal. Sine wave as well as other waveforms may be applied as a signal to the control
terminal. Figure 10 shows an example of pulse width modulation waveform.

5. Pulse Position Modulation

If the modulating signal is applied to the control terminal while the timer is connected for astable operation as in Figure 11, the
timer becomes a pulse position modulator.
In the pulse position modulator, the reference of the timer's internal comparators is modulated which in turn modulates the
timer output according to the modulation signal applied to the control terminal.
Figure 12 illustrates a sine wave for modulation signal and the resulting output pulse position modulation : however, any wave
shape could be used.

Figure 8. Waveforms of Frequency Divide r Operation

84

7

1

2

3

5

6

CONT

GND

Vcc

DISCH

THRES

RESET

TRIG

OUT

+Vcc

Trigger

R

A

C

Output

Input

Figure 9. Circuit for Pulse Width Modulation

Figure 10. Waveforms of Pulse Width Modulation

KA555

9

6. Linear Ramp

When the pull-up resistor RA in the monos table circuit shown in Figure 1 is replaced with constant current source, the VC1
increases linearly, generating a linear ramp. Figure 13 shows the linear ramp generating circuit and Figure 14 illustrates the
generated linear ramp waveform s.

In Figure 13, current source is created by PNP transistor Q1 and resistor R1, R2, and R

E

.

For example, if Vcc=15V, R

E

=20kΩ, R1=5kW, R2=10kΩ, and VBE=0.7V,

V

E

=0.7V+10V=10.7V
Ic=(15-10.7)/20k=0.215mA
When the trigger is started in a timer configured as shown in Figure 13, the current flowing to capacitor C1 becomes a constant
current generated by PNP transistor and resistors.

84

7

1

2

3

5

6

CONT

GND

Vcc

DISCH

THRES

RESET

TRIG

OUT

+Vcc

R

A

C

R

B

Modulation

Output

Figure 11. Circuit for Pulse Position Modulation

Figure 12. Waveforms of pulse posit ion modulation

Figure 13. Circuit for Linear Ramp

Figure 14. Waveforms of Linear Ramp

1

5

6

7

8

4

2

3

RESET

Vcc
DISCH

THRES

CONT

GND

OUT

TRIG

+Vcc

C2

R1

R2

C1

Q1

Output

R

E

I

C

VCCV

E

–

R

E

−−−−−−−−−−−−−−−−

= 12()

Here, V

E is

VEV

BE

R

2

R1R

2

+

−−−−−−−−−−−−−V

CC

+= 13()

KA555

10

Hence, the VC is a linear ramp function as shown in Figure 14. The gradient S of the linear ramp function is defined as
follows:

Here the Vp-p is the peak-to-peak voltage.
If the electric charge amount accumulated in the capacitor is divided by the capacitance, the V

C

comes out as follows:

V=Q/C (15)

The above equation divided on both sides by T gives us

and may be simplified into the following equation.

S=I/C (17)

In other words, the gradient of the linear ramp function appearing across the capacitor can be obtained by using the constant
current flowi ng through the capacitor.
If the constant current flow through the capacitor is 0.215mA and the capacitance is 0.02uF, the gradient of the ramp function
at both ends of the capacitor is S=0.215m/0.022u=9.77V/ms.

S

V

pp–

T

−−−−−−−−−−

= 14()

V
T

−−

QT⁄

C

−−−−−−−

= 16()

KA555

11

Mechanical Dimensions

Package

Dimensions in millimeters

6.40 ±0.20

3.30 ±0.30

0.130 ±0.012

3.40 ±0.20

0.134 ±0.008

#1

#4 #5

#8

0.252

±0.008

9.20 ±0.20

0.79

2.54

0.100

0.031

()

0.46

±0.10

0.018 ±0.004

0.060 ±0.004

1.524 ±0.10

0.362 ±0.008

9.60

0.378

MAX

5.08

0.200

0.33

0.013

7.62

0~15°

0.300

MAX

MIN

0.25

+0.10
–0.05

0.010

+0.004

–0.002

8-DIP

KA555

12

Mechanical Dimensions

(Continued)

Package

Dimensions in millimeters

4.92 ±0.20

0.194 ±0.008

0.41 ±0.10

0.016 ±0.004

1.27

0.050

5.72

0.225

1.55 ±0.20

0.061 ±0.008

0.1~0.25

0.004~0.001

6.00 ±0.30

0.236 ±0.012

3.95 ±0.20

0.156 ±0.008

0.50 ±0.20

0.020 ±0.008

5.13

0.202

MAX

#1

#4

#5

0~8°

#8

0.56

0.022

()

1.80

0.071

MAX0.10

MAX0.004

MAX

MIN

+

0.10

-0.05

0.15

+

0.004

-0.002

0.006

8-SOP

KA555

13

Ordering Information

Product Number Package Operating Temperature

KA555 8-DIP

0 ~ +70°C

KA555D 8-SOP

KA555I 8-DIP

-40 ~ +85°C

KA555ID 8-SOP

KA555

7/16/02 0.0m 001

Stock#DSxxxxxxxx

 2002 Fairchild Semiconductor Corporation

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instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.

2. A critical component in any component of a life support
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reasonably expec ted to cause the failur e of the life support
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