Datasheet K9F5616U0B-PIB0, K9F5616U0B-PCB0, K9F5616U0B-HIB0, K9F5616U0B-HCB0, K9F5616U0B-DIB0 Datasheet (Samsung)

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Page 1

K9F5608U0B-VCB0,VIB0,FCB0,FIB0 K9F5608Q0B-DCB0,DIB0,HCB0,HIB0 K9F5616Q0B-DCB0,DIB0,HCB0,HIB0 K9F5608U0B-YCB0,YIB0,PCB0,PIB0 K9F5608U0B-DCB0,DIB0,HCB0,HIB0

K9F5616U0B-YCB0,YIB0,PCB0,PIB0 K9F5616U0B-DCB0,DIB0,HCB0,HIB0

Document Title

32M x 8 Bit , 16M x 16 Bit NAND Flash Memory

Revision History

FLASH MEMORY

Revision No.

0.0

0.1

0.2

0.3

0.4

History

Initial issue.

At Read2 operation in X16 device : A3 ~ A7 are Don’t care ==> A3 ~ A7 are "L"

1. IOL(R/B) of 1.8V device is changed.

-min. Value: 7mA -->3mA

-typ. Value: 8mA -->4mA

2. AC parameter is changed. tRP(min.) : 30ns --> 25ns

3. WP pin provides hardware protection and is recommended to be kept at VIL during power-up and power-down and recovery time of minimum 1µs is required before internal circuit gets ready for any command sequences as shown in Figure 15.

---> WP pin provides hardware protection and is recommended to be kept at VIL during power-up and power-down and recovery time of minimum 10µs is required before internal circuit gets ready for any command sequences as shown in Figure 15.

1. X16 TSOP1 pin is changed. : #36 pin is changed from VccQ to N.C .

1. In X16 device, bad block information location is changed from 256th byte to 256th and 261th byte.

2. tAR1, tAR2 are merged to tAR.(page 12) (before revision) min. tAR1 = 20ns , min. tAR2 = 50ns (after revision) min. tAR = 10ns

3. min. tCLR is changed from 50ns to 10ns.(page12)

4. min. tREA is changed from 35ns to 30ns.(page12)

5. min. tWC is changed from 50ns to 45ns.(page12)

6. Unique ID for Copyright Protection is available

-The device includes one block sized OTP(One Time Programmable), which can be used to increase system security or to provide identification capabilities. Detailed information can be obtained by contact with Samsung.

7. tRHZ is divide into tRHZ and tOH.(page 12)

- tRHZ : RE High to Output Hi-Z

- tOH : RE High to Output Hold

8. tCHZ is divide into tCHZ and tOH.(page 12)

- tCHZ : CE High to Output Hi-Z

- tOH : CE High to Output Hold

Draft Date

May. 15th 2001

Sep. 20th 2001

Nov. 5th 2001

Feb. 15th 2002

Apr. 15th 2002

Remark

Advance

Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site. http://www.intl.samsungsemi.com/Memory/Flash/datasheets.html

The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right

to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the SAMSUNG branch office near you.

Page 2

K9F5608U0B-VCB0,VIB0,FCB0,FIB0 K9F5608Q0B-DCB0,DIB0,HCB0,HIB0 K9F5616Q0B-DCB0,DIB0,HCB0,HIB0 K9F5608U0B-YCB0,YIB0,PCB0,PIB0 K9F5608U0B-DCB0,DIB0,HCB0,HIB0

K9F5616U0B-YCB0,YIB0,PCB0,PIB0 K9F5616U0B-DCB0,DIB0,HCB0,HIB0

Document Title

32M x 8 Bit , 16M x 16 Bit NAND Flash Memory

Revision History

FLASH MEMORY

Revision No.

0.5

0.6

0.7

0.8

0.9

1. Add the Rp vs tr ,tf & Rp vs ibusy graph for 1.8V device (Page 33)

2. Add the data protection Vcc guidence for 1.8V device - below about

1.1V. (Page 34)

The min. Vcc value 1.8V devices is changed. K9F56XXQ0B : Vcc 1.65V~1.95V --> 1.70V~1.95V

Pb-free Package is added. K9F5608U0B-FCB0,FIB0 K9F5608Q0B-HCB0,HIB0 K9F5616U0B-HCB0,HIB0 K9F5616U0B-PCB0,PIB0 K9F5616Q0B-HCB0,HIB0 K9F5608U0B-HCB0,HIB0 K9F5608U0B-PCB0,PIB0

New definition of the number of invalid blocks is added. (Minimum 1004 valid blocks are guaranteed for each contiguous 128Mb

memory space.)

Pin assignment of TBGA A3 ball is changed. (before) N.C --> (after) Vss

Draft Date

Nov. 22.2002

Mar. 6.2003

Mar. 13rd 2003

Apr. 4th 2003

May. 24th 2003

RemarkHistory

Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site. http://www.intl.samsungsemi.com/Memory/Flash/datasheets.html

The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right

to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the SAMSUNG branch office near you.

Page 3

K9F5608U0B-VCB0,VIB0,FCB0,FIB0 K9F5608Q0B-DCB0,DIB0,HCB0,HIB0 K9F5616Q0B-DCB0,DIB0,HCB0,HIB0 K9F5608U0B-YCB0,YIB0,PCB0,PIB0 K9F5608U0B-DCB0,DIB0,HCB0,HIB0

K9F5616U0B-YCB0,YIB0,PCB0,PIB0 K9F5616U0B-DCB0,DIB0,HCB0,HIB0

FLASH MEMORY

32M x 8 Bit / 16M x 16 Bit NAND Flash Memory

PRODUCT LIST

Part Number Vcc Range Organization PKG Type

K9F5608Q0B-D,H K9F5616Q0B-D,H X16 K9F5608U0B-Y,P K9F5608U0B-D,H TBGA

K9F5608U0B-V,F WSOP1 K9F5616U0B-Y,P K9F5616U0B-D,H TBGA

1.70 ~ 1.95V

2.7 ~ 3.6V

FEATURES

• Voltage Supply

- 1.8V device(K9F56XXQ0B) : 1.70~1.95V

- 3.3V device(K9F56XXU0B) : 2.7 ~ 3.6 V

• Organization

- Memory Cell Array

- X8 device(K9F5608X0B) : (32M + 1024K)bit x 8 bit

- X16 device(K9F5616X0B) : (16M + 512K)bit x 16bit

- Data Register

- X8 device(K9F5608X0B) : (512 + 16)bit x 8bit

- X16 device(K9F5616X0B) : (256 + 8)bit x16bit

• Automatic Program and Erase

- Page Program

- X8 device(K9F5608X0B) : (512 + 16)Byte

- X16 device(K9F5616X0B) : (256 + 8)Word

- Block Erase :

- X8 device(K9F5608X0B) : (16K + 512)Byte

- X16 device(K9F5616X0B) : ( 8K + 256)Word

• Page Read Operation

- Page Size

- X8 device(K9F5608X0B) : (512 + 16)Byte

- X16 device(K9F5616X0B) : (256 + 8)Word

- Random Access : 10µs(Max.)

- Serial Page Access : 50ns(Min.)

• Fast Write Cycle Time

- Program time : 200µs(Typ.)

- Block Erase Time : 2ms(Typ.)

• Command/Address/Data Multiplexed I/O Port

• Hardware Data Protection

- Program/Erase Lockout During Power Transitions

• Reliable CMOS Floating-Gate Technology

- Endurance : 100K Program/Erase Cycles

- Data Retention : 10 Years

• Command Register Operation

• Intelligent Copy-Back

• Unique ID for Copyright Protection

• Package

- K9F56XXU0B-YCB0/YIB0 48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)

- K9F56XXX0B-DCB0/DIB0 63- Ball TBGA ( 9 x 11 /0.8mm pitch , Width 1.0 mm)

- K9F5608U0B-VCB0/VIB0 48 - Pin WSOP I (12X17X0.7mm)

- K9F56XXU0B-PCB0/PIB0 48 - Pin TSOP I (12 x 20 / 0.5 mm pitch) - Pb-free Package

- K9F56XXX0B-HCB0/HIB0 63- Ball TBGA ( 9 x 11 /0.8mm pitch , Width 1.0 mm)

- Pb-free Package

- K9F5608U0B-FCB0/FIB0 48 - Pin WSOP I (12X17X0.7mm) - Pb-free Package * K9F5608U0B-V,F(WSOPI ) is the same device as K9F5608U0B-Y,P(TSOP1) except package type.

X16

TBGA

TSOP1

GENERAL DESCRIPTION

Offered in 32Mx8bit or 16Mx16bit, the K9F56XXX0B is 256M bit with spare 8M bit capacity. The device is offered in 1.8V or 3.3V Vcc. Its NAND cell provides the most cost-effective solutIon for the solid state mass storage market. A program operation can be performed in typical 200µs on the 528-byte(X8 device) or 264-word(X16 device) page and an erase operation can be performed in typical 2ms on a 16K-byte(X8 device) or 8K-word(X16 device) block. Data in the page can be read out at 50ns cycle time per word. The I/O pins serve as the ports for address and data input/output as well as command input. The on-chip write control automates all program and erase functions including pulse repetition, where required, and internal verification and margining of data. Even the write-intensive systems can take advantage of the K9F56XXX0B′s extended reliability of 100K program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm. The K9F56XXX0B is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable applications requiring non-volatility.

Page 4

K9F5608U0B-VCB0,VIB0,FCB0,FIB0 K9F5608Q0B-DCB0,DIB0,HCB0,HIB0 K9F5616Q0B-DCB0,DIB0,HCB0,HIB0 K9F5608U0B-YCB0,YIB0,PCB0,PIB0 K9F5608U0B-DCB0,DIB0,HCB0,HIB0

K9F5616U0B-YCB0,YIB0,PCB0,PIB0 K9F5616U0B-DCB0,DIB0,HCB0,HIB0

PIN CONFIGURATION (TSOP1)

K9F56XXU0B-YCB0,PCB0/YIB0,PIB0

X8X16 X16X8

N.C N.C N.C N.C N.C

GND

R/B RE

CE N.C N.C Vcc Vss N.C N.C

CLE ALE

WE WP N.C N.C N.C N.C N.C

N.C N.C N.C N.C N.C

GND

R/B RE

CE N.C N.C Vcc Vss N.C N.C

CLE ALE

WE WP N.C N.C N.C N.C N.C

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25

PACKAGE DIMENSIONS

48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)

FLASH MEMORY

Vss

N.C

I/O15

N.C

I/O7

N.C

I/O14

N.C

I/O6

I/O7

I/O13

I/O6

I/O5

I/O12

I/O4

N.C

Vcc

N.C

Vss

N.C

I/O11

N.C

I/O3

I/O10

I/O2

I/O1

I/O9

I/O0

I/O1

N.C

I/O8

N.C

I/O0

N.C

Vss

N.C

48 - TSOP1 - 1220F

+0.003

-0.001

+0.07

-0.03

0.20

0.008

0.50

0.0197

#24

TYP

0.25

0.010

0~8¡Æ

20.00±0.20

0.787±0.008

18.40±0.10

0.724±0.004

#48

#25

Unit :mm/Inch

MAX

0.10

0.004

0.25

0.010

( )

MAX

12.00

0.472

0.488

12.40

1.00±0.05

0.039±0.002

1.20 MAX

+0.075

0.035 +0.003

-0.001

0.125

0.005

0.047

0.05

0.002

MIN

0.45~0.75

0.018~0.030

0.50

( )

0.020

Page 5

K9F5608U0B-VCB0,VIB0,FCB0,FIB0 K9F5608Q0B-DCB0,DIB0,HCB0,HIB0 K9F5616Q0B-DCB0,DIB0,HCB0,HIB0 K9F5608U0B-YCB0,YIB0,PCB0,PIB0 K9F5608U0B-DCB0,DIB0,HCB0,HIB0

K9F5616U0B-YCB0,YIB0,PCB0,PIB0 K9F5616U0B-DCB0,DIB0,HCB0,HIB0

FLASH MEMORY

PIN CONFIGURATION (TBGA)

K9F56XXX0B-DCB0,HCB0/DIB0,HIB0

DNU DNU

DNU

DNU DNU

DNU

/RE CLE

NC NC

NCNCNC

NC NC

NCNC I/O0

I/O1NC NC VccQ I/O5 I/O7

NC NC NC

NCNC

NC NC

R/B/WE/CEVssALE/WP

Vcc

VssI/O6I/O4I/O3I/O2Vss

(Top View) (Top View)

PACKAGE DIMENSIONS

63-Ball TBGA (measured in millimeters)

Top View

9.00±0.10

DNU DNU

DNU

DNU DNU

DNU

DNUDNU

(Datum A)

DNU DNU

DNU

DNU DNU

DNU

X16

/RE CLE

NC NC

NC NC NC

NC NC

NCNCNC

I/O12 IO14

I/O10I/O8 I/O1

I/O9I/O0 I/O3 VccQ I/O6 I/O15

Bottom View

9.00±0.10

0.80 x9= 7.20

0.80 x5= 4.00

0.80

6 5

DNU DNU

DNU

R/B/WE/CEVssALE/WP

I/O7I/O5

Vcc

VssI/O13I/O4I/O11I/O2Vss

DNU DNU

DNUDNU

4 3 2 1

DNU

#A1

(Datum B)

11.00±0.10

63-∅0.45±0.05

∅

0.20

0.08MAX

0.80

B C D E F

2.80 G

11.00±0.10

0.80 x7= 5.60

0.80 x11= 8.80

A B

2.00

Side View

9.00±0.10

0.45±0.05

0.90±0.10

0.32±0.05

Page 6

K9F5608U0B-VCB0,VIB0,FCB0,FIB0 K9F5608Q0B-DCB0,DIB0,HCB0,HIB0 K9F5616Q0B-DCB0,DIB0,HCB0,HIB0 K9F5608U0B-YCB0,YIB0,PCB0,PIB0 K9F5608U0B-DCB0,DIB0,HCB0,HIB0

K9F5616U0B-YCB0,YIB0,PCB0,PIB0 K9F5616U0B-DCB0,DIB0,HCB0,HIB0

FLASH MEMORY

PIN CONFIGURATION (WSOP1)

K9F5608U0B-VCB0,FCB0/VIB0,FIB0

N.C

N.C N.C

DNU

N.C N.C N.C R/B RE

DNU

N.C Vcc Vss N.C

DNU

CLE ALE

WE WP N.C N.C

DNU

N.C N.C

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

N.C

DNU

N.C

I/O7

I/O6

I/O5

I/O4

N.C

DNU

N.C

Vcc

Vss

N.C

DNU

N.C

I/O3

I/O2

I/O1

I/O0

N.C

DNU

N.C

PACKAGE DIMENSIONS

48-PIN LEAD/LEAD FREE PLASTIC VERY VERY THIN SMALL OUT-LINE PACKAGE TYPE (I)

48 - WSOP1 - 1217F

+0.07

-0.03

0.16

+0.07

-0.03

0.20

0.50TYP

(0.50±0.06)

#24

15.40±0.10

Unit :mm

0.70 MAX

0.58±0.04

#48

12.00±0.10

#25

(0.1Min)

17.00±0.20

+0.075

-0.035

0.10

0.45~0.75

Page 7

K9F5608U0B-VCB0,VIB0,FCB0,FIB0 K9F5608Q0B-DCB0,DIB0,HCB0,HIB0 K9F5616Q0B-DCB0,DIB0,HCB0,HIB0 K9F5608U0B-YCB0,YIB0,PCB0,PIB0 K9F5608U0B-DCB0,DIB0,HCB0,HIB0

K9F5616U0B-YCB0,YIB0,PCB0,PIB0 K9F5616U0B-DCB0,DIB0,HCB0,HIB0

PIN DESCRIPTION

Pin Name Pin Function

I/O0 ~ I/O7

(K9F5608X0B)

I/O0 ~ I/O15

(K9F5616X0B)

CLE

DATA INPUTS/OUTPUTS

The I/O pins are used to input command, address and data, and to output data during read operations. The I/O pins float to high-z when the chip is deselected or when the outputs are disabled. I/O8 ~ I/O15 are used only in X16 organization device. Since command input and address input are x8 operation, I/O8 ~ I/O15 are not used to input command & address. I/O8 ~ I/O15 are used only for data input and output.

COMMAND LATCH ENABLE

The CLE input controls the activating path for commands sent to the command register. When active high, commands are latched into the command register through the I/O ports on the rising edge of the WE signal.

FLASH MEMORY

ALE

R/B

VccQ

Vcc

ADDRESS LATCH ENABLE

The ALE input controls the activating path for address to the internal address registers. Addresses are latched on the rising edge of WE with ALE high.

CHIP ENABLE

The CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and the device does not return to standby mode in program or erase opertion. Regarding CE control during read operation, refer to ’Page read’ section of Device operation.

READ ENABLE

The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge of RE which also increments the internal column address counter by one.

WRITE ENABLE

The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse.

WRITE PROTECT

The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage generator is reset when the WP pin is active low.

READY/BUSY OUTPUT

The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip is deselected or when outputs are disabled.

OUTPUT BUFFER POWER

VCCQ is the power supply for Output Buffer. VccQ is internally connected to Vcc, thus should be biased to Vcc.

POWER

VCC is the power supply for device.

Vss GROUND

N.C

GND

DNU

NOTE : Connect all VCC and VSS pins of each device to common power supply outputs. Do not leave VCC or VSS disconnected.

NO CONNECTION

Lead is not internally connected.

GND INPUT FOR ENABLING SPARE AREA

To do sequential read mode including spare area , connect this input pin to Vss or set to static low state or to do sequential read mode excluding spare area , connect this input pin to Vcc or set to static high state.

DO NOT USE

Leave it disconnected.

Page 8

K9F5608U0B-VCB0,VIB0,FCB0,FIB0 K9F5608Q0B-DCB0,DIB0,HCB0,HIB0 K9F5616Q0B-DCB0,DIB0,HCB0,HIB0 K9F5608U0B-YCB0,YIB0,PCB0,PIB0 K9F5608U0B-DCB0,DIB0,HCB0,HIB0

K9F5616U0B-YCB0,YIB0,PCB0,PIB0 K9F5616U0B-DCB0,DIB0,HCB0,HIB0

Figure 1-1. K9F5608X0B (X8) FUNCTIONAL BLOCK DIAGRAM

VCC VSS

FLASH MEMORY

A9 - A24

A0 - A7

X-Buffers Latches & Decoders

Y-Buffers Latches & Decoders

(512 + 16)Byte x 65536

Page Register & S/A

Command

CE RE WE

Control Logic

& High Voltage

Generator

CLE ALE

I/O Buffers & Latches

Global Buffers

Figure 2-1. K9F5608X0B (X8) ARRAY ORGANIZATION

256M + 8M Bit

NAND Flash

ARRAY

Y-Gating

1 Block =32 Pages = (16K + 512) Byte

Output

Driver

VCC/VCCQ VSS

I/0 0 I/0 7

64K Pages (=2,048 Blocks)

1st half Page Register (=256 Bytes)

512Byte 16 Byte

2nd half Page Register (=256 Bytes)

Page Register

512 Byte

I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7

1st Cycle A0 A1 A2 A3 A4 A5 A6 A7

2nd Cycle A9 A10 A11 A12 A13 A14 A15 A16

3rd Cycle A17 A18 A19 A20 A21 A22 A23 A24

NOTE : Column Address : Starting Address of the Register.

00h Command(Read) : Defines the starting address of the 1st half of the register. 01h Command(Read) : Defines the starting address of the 2nd half of the register. * A8 is set to "Low" or "High" by the 00h or 01h Command.

* The device ignores any additional input of address cycles than reguired.

1 Page = 528 Byte 1 Block = 528 Byte x 32 Pages = (16K + 512) Byte 1 Device = 528Bytes x 32Pages x 2048 Blocks = 264 Mbits

8 bit

I/O 0 ~ I/O 7

16 Byte

Column Address Row Address

(Page Address)

Page 9

K9F5608U0B-VCB0,VIB0,FCB0,FIB0 K9F5608Q0B-DCB0,DIB0,HCB0,HIB0 K9F5616Q0B-DCB0,DIB0,HCB0,HIB0 K9F5608U0B-YCB0,YIB0,PCB0,PIB0 K9F5608U0B-DCB0,DIB0,HCB0,HIB0

K9F5616U0B-YCB0,YIB0,PCB0,PIB0 K9F5616U0B-DCB0,DIB0,HCB0,HIB0

Figure 1-2. K9F5616X0B (X16) FUNCTIONAL BLOCK DIAGRAM

VCC VSS

FLASH MEMORY

A9 - A24

A0 - A7

Command

CE RE WE

X-Buffers Latches & Decoders

Y-Buffers Latches & Decoders

Command

Control Logic

& High Voltage

Generator

CLE ALE

256M + 8M Bit

(256 + 8)Word x 65536

Page Register & S/A

I/O Buffers & Latches

Global Buffers

Figure 2-2. K9F5616X0B (X16) ARRAY ORGANIZATION

NAND Flash

ARRAY

Y-Gating

1 Block =32 Pages = (8K + 256) Word

Output

Driver

VCC/VCCQ VSS

I/0 0 I/0 15

1 Page = 264 Word

64K Pages (=2,048 Blocks)

I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O8 to 15

1st Cycle A0 A1 A2 A3 A4 A5 A6 A7

2nd Cycle A9 A10 A11 A12 A13 A14 A15 A16

3rd Cycle A17 A18 A19 A20 A21 A22 A23 A24

NOTE : Column Address : Starting Address of the Register.

* L must be set to "Low".

Page Register (=256 Words)

256Word 8 Word

Page Register

256 Word

8 Word

I/O 0 ~ I/O 15

1 Block = 264 Word x 32 Pages = (8K + 256) Word 1 Device = 264Words x 32Pages x 2048 Blocks = 264 Mbits

16 bit

L* L* L*

Column Address Row Address

(Page Address)

Page 10

K9F5608U0B-VCB0,VIB0,FCB0,FIB0 K9F5608Q0B-DCB0,DIB0,HCB0,HIB0 K9F5616Q0B-DCB0,DIB0,HCB0,HIB0 K9F5608U0B-YCB0,YIB0,PCB0,PIB0 K9F5608U0B-DCB0,DIB0,HCB0,HIB0

K9F5616U0B-YCB0,YIB0,PCB0,PIB0 K9F5616U0B-DCB0,DIB0,HCB0,HIB0

FLASH MEMORY

PRODUCT INTRODUCTION

The K9F56XXX0B is a 264Mbit(276,824,064 bit) memory organized as 65,536 rows(pages) by 528(X8 device) or 264(X16 device) columns. Spare eight columns are located from column address of 512~527(X8 device) or 256~263(X16 device). A 528-byte(X8 device) or 264-word(X16 device) data register is connected to memory cell arrays accommodating data transfer between the I/O buffers and memory during page read and page program operations. The memory array is made up of 16 cells that are serially connected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of two NAND structures. A NAND structure consists of 16 cells. Total 16896 NAND cells reside in a block. The array organization is shown in Figure 2-1,2-2. The program and read operations are executed on a page basis, while the erase operation is executed on a block basis. The memory array consists of 2048 separately erasable 16K-Byte(X8 device) or 8K-Word(X16 device) blocks. It indicates that the bit by bit erase operation is prohibited on the K9F56XXX0B. The K9F56XXX0B has addresses multiplexed into 8 I/Os(X16 device case: lower 8 I/Os). K9F5616X0B allows sixteen bit wide data transport into and out of page registers. This scheme dramatically reduces pin counts while providing high performance and allows systems upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through I/O′s by bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one bus cycle. For example, Reset command, Read command, Status Read command, etc require just one cycle bus. Some other commands like Page Program and Copy-back Program and Block Erase, require two cycles: one cycle for setup and the other cycle for execution. The 32M-byte(X8 device) or 16M-word(X16 device) physical space requires 24 addresses, thereby requiring three cycles for word-level addressing: column address, low row address and high row address, in that order. Page Read and Page Program need the same three address cycles following the required command input. In Block Erase operation, however, only the two row address cycles are used. Device operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of the K9F56XXX0B.

The device includes one block sized OTP(One Time Programmable), which can be used to increase system security or to provide identification capabilities. Detailed information can be obtained by contact with Samsung.

Table 1. COMMAND SETS

Function 1st. Cycle 2nd. Cycle Acceptable Command during Busy

Read 1 Read 2 50h Read ID 90h Reset FFh - O Page Program 80h 10h Copy-Back Program 00h 8Ah Block Erase 60h D0h Read Status 70h - O

NOTE : 1. The 01h command is available only on X8 device(K9F5608X0B).

Caution : Any undefined command inputs are prohibited except for above command set of Table 1.

00h/01h

(1)

Page 11

K9F5608U0B-VCB0,VIB0,FCB0,FIB0 K9F5608Q0B-DCB0,DIB0,HCB0,HIB0 K9F5616Q0B-DCB0,DIB0,HCB0,HIB0 K9F5608U0B-YCB0,YIB0,PCB0,PIB0 K9F5608U0B-DCB0,DIB0,HCB0,HIB0

K9F5616U0B-YCB0,YIB0,PCB0,PIB0 K9F5616U0B-DCB0,DIB0,HCB0,HIB0

FLASH MEMORY

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol

VIN/OUT -0.6 to + 2.45 -0.6 to + 4.6

Voltage on any pin relative to VSS

Temperature Under Bias

Storage Temperature

Short Circuit Current Ios 5 mA

NOTE:

1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns. Maximum DC voltage on input/output pins is VCC,+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.

2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

K9F56XXX0B-XCB0 K9F56XXX0B-XIB0 -40 to +125 K9F56XXX0B-XCB0 K9F56XXX0B-XIB0

VCC -0.2 to + 2.45 -0.6 to + 4.6

VCCQ -0.2 to + 2.45 -0.6 to + 4.6

TBIAS

TSTG -65 to +150 °C

K9F56XXQ0B(1.8V) K9F56XXU0B(3.3V)

Rating

-10 to +125

Unit

°C

RECOMMENDED OPERATING CONDITIONS

(Voltage reference to GND, K9F56XXX0B-XCB0 :TA=0 to 70°C, K9F56XXX0B-XIB0 :TA=-40 to 85°C)

Parameter Symbol

Supply Voltage VCC 1.70 1.8 1.95 2.7 3.3 3.6 V Supply Voltage VCCQ 1.70 1.8 1.95 2.7 3.3 3.6 V Supply Voltage VSS 0 0 0 0 0 0 V

K9F56XXQ0B(1.8V)

Min Typ. Max Min Typ. Max

K9F56XXU0B(3.3V)

Unit

DC AND OPERATING CHARACTERISTICS(Recommended operating conditions otherwise noted.)

Parameter Symbol Test Conditions

Operat-

Current

Stand-by Current(TTL) ISB1 CE=VIH, WP=0V/VCC - - 1 - - 1 Stand-by Current(CMOS) ISB2 CE=VCC-0.2, WP=0V/VCC - 10 50 - 10 50 Input Leakage Current ILI VIN=0 to Vcc(max) - - ±10 - - ±10 Output Leakage Current ILO VOUT=0 to Vcc(max) - - ±10 - - ±10

Input High Voltage VIH

Input Low Voltage, All inputs VIL - -0.3 - 0.4 -0.3 - 0.8

Output High Voltage Level VOH

Output Low Voltage Level VOL

Output Low Current(R/B) IOL(R/B)

Sequential Read ICC1

ing

Program ICC2 - - 8 15 - 10 20 Erase ICC3 - - 8 15 - 10 20

tRC=50ns, CE=VIL IOUT=0mA

I/O pins VCCQ-0.4 -

Except I/O pins VCC-0.4 -

K9F56XXQ0B :IOH=-100µA K9F56XXU0B :IOH=-400µA

K9F56XXQ0B :IOL=100uA K9F56XXU0B :IOL=2.1mA

K9F56XXQ0B :VOL=0.1V K9F56XXU0B :VOL=0.4V

K9F56XXQ0B(1.8V) K9F56XXU0B(3.3V) Unit

Min Typ Max Min Typ Max

- 8 15 - 10 20

VCCQ

+0.3

VCCQ-0.1 - - 2.4 - -

- - 0.1 - - 0.4

3 4 - 8 10 - mA

2.0 - VCCQ+0.3

VCC

2.0 - VCC+0.3

µA

Page 12

K9F5608U0B-VCB0,VIB0,FCB0,FIB0 K9F5608Q0B-DCB0,DIB0,HCB0,HIB0 K9F5616Q0B-DCB0,DIB0,HCB0,HIB0 K9F5608U0B-YCB0,YIB0,PCB0,PIB0 K9F5608U0B-DCB0,DIB0,HCB0,HIB0

K9F5616U0B-YCB0,YIB0,PCB0,PIB0 K9F5616U0B-DCB0,DIB0,HCB0,HIB0

FLASH MEMORY

VALID BLOCK

Parameter Symbol Min Typ. Max Unit

Valid Block Number NVB 2013 - 2048 Blocks

NOTE :

1. The K9F56XXX0B may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or program factory-marked bad blocks. Refer to the attached technical notes for a appropriate management of invalid blocks.

2. The 1st block, which is placed on 00h block address, is fully guaranteed to be a valid block, does not require Error Correction.

3. The number of initial bad blocks upon shipping does not exceed 20.

4. Minimum 1004 valid blocks are guaranteed for each contiguous 128Mb memory space.

AC TEST CONDITION

(K9F56XXX0B-XCB0 :TA=0 to 70°C, K9F56XXX0B-XIB0 :TA=-40 to 85°C K9F56XXQ0B : Vcc=1.70V~1.95V , K9F56XXU0B : Vcc=2.7V~3.6V unless otherwise noted)

Parameter K9F56XXQ0B K9F56XXU0B

Input Pulse Levels 0V to VccQ 0.4V to 2.4V Input Rise and Fall Times 5ns 5ns Input and Output Timing Levels VccQ/2 1.5V K9F56XXQ0B:Output Load (VccQ:1.8V +/-10%)

K9F56XXU0B:Output Load (VccQ:3.0V +/-10%) K9F56XXU0B:Output Load (VccQ:3.3V +/-10%) - 1 TTL GATE and CL=100pF

1 TTL GATE and CL=30pF 1 TTL GATE and CL=50pF

CAPACITANCE(TA=25°C, VCC=1.8V/3.3V, f=1.0MHz)

Item Symbol Test Condition Min Max Unit

Input/Output Capacitance CI/O VIL=0V - 10 pF Input Capacitance CIN VIN=0V - 10 pF

NOTE : Capacitance is periodically sampled and not 100% tested.

MODE SELECTION

CLE ALE CE WE RE GND WP Mode

H L L H X X L H L H X X Address Input(3clock) H L L H X H L H L H X H Address Input(3clock) L L L H L H Data Input L L L H L X Data Output L L L H H L X During Read(Busy) on K9F5608U0B_Y,P or K9F5608U0B_V,F

X X X X H L X

X X X X X L H During Program(Busy) X X X X X X H During Erase(Busy) X X X H X X 0V

NOTE : 1. X can be VIL or VIH.

(1)

2. WP should be biased to CMOS high or CMOS low for standby.

X X X X L Write Protect

0V/VCC

Read Mode

Write Mode

During Read(Busy) on the devices except K9F5608U0B_Y,P and K9F5608U0B_V,F

(2)

Stand-by

Command Input

Program/Erase Characteristics

Parameter Symbol Min Typ Max Unit

Program Time tPROG - 200 500 µs Number of Partial Program Cycles

in the Same Page Block Erase Time tBERS - 2 3 ms

Main Array

Spare Array - - 3 cycles

Nop

- - 2 cycles

Page 13

K9F5608U0B-VCB0,VIB0,FCB0,FIB0 K9F5608Q0B-DCB0,DIB0,HCB0,HIB0 K9F5616Q0B-DCB0,DIB0,HCB0,HIB0 K9F5608U0B-YCB0,YIB0,PCB0,PIB0 K9F5608U0B-DCB0,DIB0,HCB0,HIB0

K9F5616U0B-YCB0,YIB0,PCB0,PIB0 K9F5616U0B-DCB0,DIB0,HCB0,HIB0

FLASH MEMORY

AC Timing Characteristics for Command / Address / Data Input

Parameter Symbol Min Max Unit

CLE Set-up Time tCLS 0 - ns CLE Hold Time tCLH 10 - ns CE Setup Time tCS 0 .- ns CE Hold Time WE Pulse Width tWP ALE Setup Time tALS 0 - ns ALE Hold Time Data Setup Time tDS 20 - ns Data Hold Time Write Cycle Time tWC 45 - ns WE High Hold Time

NOTE :

1. If tCS is set less than 10ns, tWP must be minimum 35ns, otherwise, tWP may be minimum 25ns.

tCH 10 - ns

(1)

tALH 10 -

tDH 10 - ns

tWH 15 - ns

- ns

AC Characteristics for Operation

Parameter Symbol Min Max Unit

Data Transfer from Cell to Register tR - 10 µs ALE to RE Delay tAR 10 - ns CLE to RE Delay tCLR 10 - ns Ready to RE Low tRR 20 - ns RE Pulse Width tRP 25 - ns WE High to Busy tWB - 100 ns Read Cycle Time tRC 50 - ns CE Access Time tCEA - 45 ns RE Access Time tREA - 30 ns RE High to Output Hi-Z tRHZ - 30 ns CE High to Output Hi-Z RE or CE High to Output hold tOH 15 RE High Hold Time tREH 15 - ns Output Hi-Z to RE Low tIR 0 - ns WE High to RE Low tWHR 60 - ns Device Resetting Time(Read/Program/Erase) tRST -

K9F5608U0BY,P,V,F only

Last RE High to Busy(at sequential read) tRB - 100 ns CE High to Ready(in case of interception by CE at read) CE High Hold Time(at the last serial read)

(2)

tCHZ - 20 ns

5/10/500

tCRY tCEH 100 - ns

50 +tr(R/B)

(1)

(3)

µs

NOTE :

1. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5us.

2. To break the sequential read cycle, CE must be held high for longer time than tCEH.

3. The time to Ready depends on the value of the pull-up resistor tied R/B pin.

Page 14

K9F5608U0B-VCB0,VIB0,FCB0,FIB0 K9F5608Q0B-DCB0,DIB0,HCB0,HIB0 K9F5616Q0B-DCB0,DIB0,HCB0,HIB0 K9F5608U0B-YCB0,YIB0,PCB0,PIB0 K9F5608U0B-DCB0,DIB0,HCB0,HIB0

K9F5616U0B-YCB0,YIB0,PCB0,PIB0 K9F5616U0B-DCB0,DIB0,HCB0,HIB0

FLASH MEMORY

NAND Flash Technical Notes

Invalid Block(s)

Invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by Samsung. The information regarding the invalid block(s) is so called as the invalid block information. Devices with invalid block(s) have the same quality level as devices with all valid blocks and have the same AC and DC characteristics. An invalid block(s) does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a select transistor. The system design must be able to mask out the invalid block(s) via address mapping. The 1st block, which is placed on 00h block address, is fully guaranteed to be a valid block, does not require Error Correction.

Identifying Invalid Block(s)

All device locations are erased(FFh) except locations where the invalid block(s) information is written prior to shipping. The invalid block(s) status is defined by the 6th byte(X8 device) or 1st word(X16 device) in the spare area. Samsung makes sure that either the 1st or 2nd page of every invalid block has non-FFh(X8 device) or non-FFFFh(X16 device) data at the column address of 517(X8 device) or 256 and 261(X16 device). Since the invalid block information is also erasable in most cases, it is impossible to recover the information once it has been erased. Therefore, the system must be able to recognize the invalid block(s) based on the original invalid block information and create the invalid block table via the following suggested flow chart(Figure 3). Any intentional erasure of the original invalid block information is prohibited.

Start

Increment Block Address

Create (or update)

Invalid Block(s) Table

Set Block Address = 0

Check "FFh" at the column address 517(X8 device) or 256 and 261(X16 device)

Figure 3. Flow chart to create invalid block table.

Check "FFh" ?

Yes

Last Block ?

Yes

End

of the 1st and 2nd page in the block

Page 15

K9F5608U0B-VCB0,VIB0,FCB0,FIB0 K9F5608Q0B-DCB0,DIB0,HCB0,HIB0 K9F5616Q0B-DCB0,DIB0,HCB0,HIB0 K9F5608U0B-YCB0,YIB0,PCB0,PIB0 K9F5608U0B-DCB0,DIB0,HCB0,HIB0

K9F5616U0B-YCB0,YIB0,PCB0,PIB0 K9F5616U0B-DCB0,DIB0,HCB0,HIB0

FLASH MEMORY

NAND Flash Technical Notes (Continued)

Error in write or read operation

Within its life time, the additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read failure after erase or program, block replacement should be done. Because program status fail during a page program does not affect the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased empty block and reprogramming the current target data and copying the rest of the replaced block. To improve the efficiency of memory space, it is recommended that the read or verification failure due to single bit error be reclaimed by ECC without any block replacement. The said additional block failure rate does not include those reclaimed blocks.

Failure Mode Detection and Countermeasure sequence

Erase Failure Status Read after Erase --> Block Replacement

Write

Read Single Bit Failure Verify ECC -> ECC Correction

Program Failure

Status Read after Program --> Block Replacement Read back ( Verify after Program) --> Block Replacement

or ECC Correction

ECC

Program Flow Chart

Program Error

: Error Correcting Code --> Hamming Code etc. Example) 1bit correction & 2bit detection

Start

Write 80h

Write Address

Write Data

Write 10h

Read Status Register

I/O 6 = 1 ?

or R/B = 1 ?

Yes

I/O 0 = 0 ?

: If program operation results in an error, map out

the block including the page in error and copy the target data to another block.

If ECC is used, this verification operation is not needed.

Write 00h

Write Address

Wait for tR Time

Verify Data

Program Completed

Yes

Program Error

Yes

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K9F5608U0B-VCB0,VIB0,FCB0,FIB0 K9F5608Q0B-DCB0,DIB0,HCB0,HIB0 K9F5616Q0B-DCB0,DIB0,HCB0,HIB0 K9F5608U0B-YCB0,YIB0,PCB0,PIB0 K9F5608U0B-DCB0,DIB0,HCB0,HIB0

K9F5616U0B-YCB0,YIB0,PCB0,PIB0 K9F5616U0B-DCB0,DIB0,HCB0,HIB0

NAND Flash Technical Notes (Continued)

FLASH MEMORY

Erase Flow Chart

Erase Error

Start

Write 60h

Write Block Address

Write D0h

Read Status Register

I/O 6 = 1 ?

or R/B = 1 ?

Yes

I/O 0 = 0 ?

Yes

Read Flow Chart

Reclaim the Error

Start

Write 00h

Write Address

Read Data

ECC Generation

Verify ECC

Yes

Page Read Completed

Erase Completed

: If erase operation results in an error, map out

the failing block and replace it with another block.

Block Replacement

Block A

1st

∼

{

(n-1)th nth

(page)

1st

∼

(n-1)th nth

(page)

* Step1 When an error happens in the nth page of the Block ’A’ during erase or program operation. * Step2 Copy the nth page data of the Block ’A’ in the buffer memory to the nth page of another free block. (Block ’B’) * Step3 Then, copy the data in the 1st ~ (n-1)th page to the same location of the Block ’B’. * Step4 Do not further erase Block ’A’ by creating an ’invalid Block’ table or other appropriate scheme.

an error occurs.

Block B

{

Buffer memory of the controller.

Page 17

K9F5608U0B-VCB0,VIB0,FCB0,FIB0 K9F5608Q0B-DCB0,DIB0,HCB0,HIB0 K9F5616Q0B-DCB0,DIB0,HCB0,HIB0 K9F5608U0B-YCB0,YIB0,PCB0,PIB0 K9F5608U0B-DCB0,DIB0,HCB0,HIB0

K9F5616U0B-YCB0,YIB0,PCB0,PIB0 K9F5616U0B-DCB0,DIB0,HCB0,HIB0

FLASH MEMORY

Pointer Operation of K9F5608X0B(X8)

Samsung NAND Flash has three address pointer commands as a substitute for the two most significant column addresses. ’00h’ command sets the pointer to ’A’ area(0~255byte), ’01h’ command sets the pointer to ’B’ area(256~511byte), and ’50h’ command sets the pointer to ’C’ area(512~527byte). With these commands, the starting column address can be set to any of a whole page(0~527byte). ’00h’ or ’50h’ is sustained until another address pointer command is inputted. ’01h’ command, however, is effective only for one operation. After any operation of Read, Program, Erase, Reset, Power_Up is executed once with ’01h’ command, the address pointer returns to ’A’ area by itself. To program data starting from ’A’ or ’C’ area, ’00h’ or ’50h’ command must be inputted before ’80h’ command is written. A complete read operation prior to ’80h’ command is not necessary. To program data starting from ’B’ area, ’01h’ command must be inputted right before ’80h’ command is written.

Table 2. Destination of the pointer

Command Pointer position Area

00h 01h 50h

0 ~ 255 byte 256 ~ 511 byte 512 ~ 527 byte

1st half array(A)

2nd half array(B)

spare array(C)

(1) Command input sequence for programming ’A’ area

The address pointer is set to ’A’ area(0~255), and sustained

Address / Data input

00h

’A’,’B’,’C’ area can be programmed. It depends on how many data are inputted.

80h 10h 00h 80h 10h

"A" area

(00h plane)

256 Byte

"A" "B" "C"

Pointer select commnad (00h, 01h, 50h)

"B" area

(01h plane)

256 Byte

Pointer

"C" area

(50h plane)

16 Byte

Figure 4. Block Diagram of Pointer Operation

Address / Data input

’00h’ command can be omitted.

Internal

Page Register

(2) Command input sequence for programming ’B’ area

The address pointer is set to ’B’ area(256~512), and will be reset to ’A’ area after every program operation is executed.

Address / Data input

01h

’B’, ’C’ area can be programmed. It depends on how many data are inputted.

80h 10h 01h 80h 10h

(3) Command input sequence for programming ’C’ area

The address pointer is set to ’C’ area(512~527), and sustained

Address / Data input

50h

Only ’C’ area can be programmed. ’50h’ command can be omitted.

80h 10h

Address / Data input

’01h’ command must be rewritten before every program operation

Address / Data input

50h 80h 10h

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K9F5608U0B-VCB0,VIB0,FCB0,FIB0 K9F5608Q0B-DCB0,DIB0,HCB0,HIB0 K9F5616Q0B-DCB0,DIB0,HCB0,HIB0 K9F5608U0B-YCB0,YIB0,PCB0,PIB0 K9F5608U0B-DCB0,DIB0,HCB0,HIB0

K9F5616U0B-YCB0,YIB0,PCB0,PIB0 K9F5616U0B-DCB0,DIB0,HCB0,HIB0

FLASH MEMORY

Pointer Operation of K9F5616X0B(X16)

Samsung NAND Flash has two address pointer commands as a substitute for the most significant column address. ’00h’ command sets the pointer to ’A’ area(0~255word), and ’50h’ command sets the pointer to ’B’ area(256~263word). With these commands, the starting column address can be set to any of a whole page(0~263word). ’00h’ or ’50h’ is sustained until another address pointer command is inputted. To program data starting from ’A’ or ’B’ area, ’00h’ or ’50h’ command must be inputted before ’80h’ command is written. A complete read operation prior to ’80h’ command is not necessary.

Table 3. Destination of the pointer

Command Pointer position Area

00h 50h

0 ~ 255 word

256 ~ 263 word

main array(A)

spare array(B)

(1) Command input sequence for programming ’A’ area

The address pointer is set to ’A’ area(0~255), and sustained

Address / Data input

00h

’A’,’B’ area can be programmed. It depends on how many data are inputted.

80h 10h 00h 80h 10h

(00h plane)

Pointer select command (00h, 50h)

"A" area

256 Word

"A" "B"

Pointer

"B" area

(50h plane)

8 Word

Figure 5. Block Diagram of Pointer Operation

Address / Data input

’00h’ command can be omitted.

Internal

Page Register

(2) Command input sequence for programming ’B’ area

The address pointer is set to ’B’ area(256~263), and sustained

Address / Data input

50h

Only ’B’ area can be programmed. ’50h’ command can be omitted.

80h 10h 50h 80h 10h

Address / Data input

Page 19

K9F5608U0B-VCB0,VIB0,FCB0,FIB0 K9F5608Q0B-DCB0,DIB0,HCB0,HIB0 K9F5616Q0B-DCB0,DIB0,HCB0,HIB0 K9F5608U0B-YCB0,YIB0,PCB0,PIB0 K9F5608U0B-DCB0,DIB0,HCB0,HIB0

K9F5616U0B-YCB0,YIB0,PCB0,PIB0 K9F5616U0B-DCB0,DIB0,HCB0,HIB0

FLASH MEMORY

System Interface Using CE don’t-care.

For an easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown below. The internal 528byte/264word page registers are utilized as seperate buffers for this operation and the system design gets more flexible. In addition, for voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and reading would provide significant savings in power consumption.

Figure 6. Program Operation with CE don’t-care.

CLE

CE don’t-care

ALE

I/Ox

tCS

Start Add.(3Cycle)80h Data Input

tCH

tWP

Figure 7. Read Operation with CE don’t-care.

CLE

On K9F5608U0B_Y,P or K9F5608U0B_V,F CE must be held low during tR

≈

I/O0~15

tCEA

tREA

CE don’t-care

≈

Data Input

out

10h

ALE

R/B

I/Ox

≈

Start Add.(3Cycle)00h

Data Output(sequential)

Page 20

K9F5608U0B-VCB0,VIB0,FCB0,FIB0 K9F5608Q0B-DCB0,DIB0,HCB0,HIB0 K9F5616Q0B-DCB0,DIB0,HCB0,HIB0 K9F5608U0B-YCB0,YIB0,PCB0,PIB0 K9F5608U0B-DCB0,DIB0,HCB0,HIB0

K9F5616U0B-YCB0,YIB0,PCB0,PIB0 K9F5616U0B-DCB0,DIB0,HCB0,HIB0

FLASH MEMORY

Device

I/O DATA

I/Ox Data In/Out

K9F5608X0B(X8 device) I/O 0 ~ I/O 7 ~528byte K9F5616X0B(X16 device)

NOTE: 1. I/O8~15 must be set to "0" during command or address input.

2. I/O8~15 are used only for data bus.

I/O 0 ~ I/O 15

* Command Latch Cycle

CLE

tCLS

tCS

tWP

tALS tALH

ALE

tDS

tCLH

tCH

tDH

~264word

I/Ox

* Address Latch Cycle

CLE

ALE

tCLS

tCS

tALS

tWP

tWC

tDS

Command

tWH

tALH

tALS

tDH

tWP

tWC

tDS

tWH

tALH tALS

tDH

tWP

tDS

tALH

tDH

I/Ox

AO~A7

A17~A24A9~A16

Page 21

K9F5608U0B-VCB0,VIB0,FCB0,FIB0 K9F5608Q0B-DCB0,DIB0,HCB0,HIB0 K9F5616Q0B-DCB0,DIB0,HCB0,HIB0 K9F5608U0B-YCB0,YIB0,PCB0,PIB0 K9F5608U0B-DCB0,DIB0,HCB0,HIB0

K9F5616U0B-YCB0,YIB0,PCB0,PIB0 K9F5616U0B-DCB0,DIB0,HCB0,HIB0

* Input Data Latch Cycle

tCLH

CLE

tCH

FLASH MEMORY

tWP

tWC

tDS

DIN 0

tDH

tWH

tWP

tDS

DIN 1

≈

tDH

tALS

ALE

I/Ox

* Serial access Cycle after Read(CLE=L, WE=H, ALE=L)

tREA

tRC

tREH

tREA

tRP

tWP

tDH

tDS

≈

DIN n

≈

≈≈≈≈

tREA

tCHZ*

tOH

I/Ox

R/B

tRHZ*

Dout

tRR

NOTES : Transition is measured ±200mV from steady state voltage with load.

This parameter is sampled and not 100% tested.

Dout

tRHZ*

tOH

Dout

Page 22

K9F5608U0B-VCB0,VIB0,FCB0,FIB0 K9F5608Q0B-DCB0,DIB0,HCB0,HIB0 K9F5616Q0B-DCB0,DIB0,HCB0,HIB0 K9F5608U0B-YCB0,YIB0,PCB0,PIB0 K9F5608U0B-DCB0,DIB0,HCB0,HIB0

K9F5616U0B-YCB0,YIB0,PCB0,PIB0 K9F5616U0B-DCB0,DIB0,HCB0,HIB0

* Status Read Cycle

tCLR

CLE

tCLS

tCS

tCLH

tCH

tWP

tWHR

tDH tREA

tDS

tCEA

tIR

FLASH MEMORY

tCHZ

tOH

tRHZ

tOH

I/Ox

70h

READ1 OPERATION(READ ONE PAGE)

CLE

tWC

tWB

ALE

I/Ox

R/B

X8 device : m = 528 , Read CMD = 00h or 01h X16 device : m = 264 , Read CMD = 00h

Read CMD

N Address

A0~A7

Column Address

A9~A16

Page(Row) Address

A17~A24

On K9F5608U0B_Y,P or K9F5608U0B_V,F CE must be held low during tR

tAR

tRC

tRR

Dout N

Busy

Dout N+1

NOTES : 1) is only valid on K9F5608U0B_Y,P or K9F5608U0B_V,F

Status Output

Dout N+2 Dout N+3

1) tCEH

tCHZ tOH

tCRY

tRHZ

tOH

≈

≈≈

Dout m

tRB

Page 23

K9F5608U0B-VCB0,VIB0,FCB0,FIB0 K9F5608Q0B-DCB0,DIB0,HCB0,HIB0 K9F5616Q0B-DCB0,DIB0,HCB0,HIB0 K9F5608U0B-YCB0,YIB0,PCB0,PIB0 K9F5608U0B-DCB0,DIB0,HCB0,HIB0

K9F5616U0B-YCB0,YIB0,PCB0,PIB0 K9F5616U0B-DCB0,DIB0,HCB0,HIB0

READ1 OPERATION (INTERCEPTED BY CE)

CLE

On K9F5608U0B_Y,P or K9F5608U0B_V,F CE must be held

tWB

ALE

low during tR

tAR

FLASH MEMORY

tCHZ tOH

I/Ox

Read

CMD

N Address

Col. Add

Column Address

Row Add1 Row Add2

Page(Row) Address

R/B

READ2 OPERATION (READ ONE PAGE)

CLE

ALE

tWB

tRR

Busy

Dout N

tRC

Dout N+1

Dout N+2 Dout N+3

On K9F5608U0B_Y,P or K9F5608U0B_V,F CE must be held low during tR

tAR

tRR

≈

I/Ox

R/B

50h

Col. Add

Row Add1

Row Add2

M Address

X8 device : A0~A3 are Valid Address & A4~A7 are Don′t care

X16 device : A0~A2 are Valid Address & A3~A7 are "L"

X8 device : n = 512, m = 16 X16 device : n = 256, m = 8

Dout

n+M

Selected Row

Dout

n+M+1

Dout n+m

≈

Start address M

Page 24

K9F5608U0B-VCB0,VIB0,FCB0,FIB0 K9F5608Q0B-DCB0,DIB0,HCB0,HIB0 K9F5616Q0B-DCB0,DIB0,HCB0,HIB0 K9F5608U0B-YCB0,YIB0,PCB0,PIB0 K9F5608U0B-DCB0,DIB0,HCB0,HIB0

K9F5616U0B-YCB0,YIB0,PCB0,PIB0 K9F5616U0B-DCB0,DIB0,HCB0,HIB0

FLASH MEMORY

SEQUENTIAL ROW READ OPERATION (only for K9F5608U0B-Y,P and K9F5608U0B-V,F, Valid with in a block)

CLE

ALE

I/Ox

00h

Row Add1 Row Add2

Col. Add

R/B

PAGE PROGRAM OPERATION

CLE

tWC

≈

DoutNDout

Ready

Busy Busy

tWC

N+1

Dout

N+2

M+1

Output

tWC

≈≈

Dout

≈

527

≈

Dout0Dout1Dout2Dout

527

≈

Output

ALE

I/Ox

R/B

tPROG

tWB

N Address

≈

80h 70h I/O0

Sequential Data Input Command

Col. Add

Column Address

Row Add1 Row Add2

Page(Row)

Address

DinNDin

1 up to m Data Serial Input

X8 device : m = 528 byte X16 device : m = 264 word

N+1

Din

10h

≈

Program Command

≈

Read Status Command

I/O0=0 Successful Program I/O0=1 Error in Program

Page 25

K9F5608U0B-VCB0,VIB0,FCB0,FIB0 K9F5608Q0B-DCB0,DIB0,HCB0,HIB0 K9F5616Q0B-DCB0,DIB0,HCB0,HIB0 K9F5608U0B-YCB0,YIB0,PCB0,PIB0 K9F5608U0B-DCB0,DIB0,HCB0,HIB0

K9F5616U0B-YCB0,YIB0,PCB0,PIB0 K9F5616U0B-DCB0,DIB0,HCB0,HIB0

COPY-BACK PROGRAM OPERATION

CLE

tWC

FLASH MEMORY

tWB

ALE

I/Ox

R/B

00h 70h I/O0

Col. Add

Column

Address

Page(Row)

Address

Busy

Row Add2

Row Add1

8Ah

Program

Command

≈

BLOCK ERASE OPERATION (ERASE ONE BLOCK)

CLE

tWC

A0~A7 A17~A24A9~A16

Column Address

Page(Row)

Address

tWB

tPROG

≈

Busy

Read Status Command

I/O0=0 Successful Program I/O0=1 Error in Program

ALE

I/Ox

R/B

A9~A16

60h

Auto Block Erase Setup Command

A17~A24

Page(Row)

Address

tWB

DOh 70h I/O 0

tBERS

Busy

≈

Erase Command Read Status

Command

I/O0=0 Successful Erase I/O0=1 Error in Erase

Page 26

K9F5608U0B-VCB0,VIB0,FCB0,FIB0 K9F5608Q0B-DCB0,DIB0,HCB0,HIB0 K9F5616Q0B-DCB0,DIB0,HCB0,HIB0 K9F5608U0B-YCB0,YIB0,PCB0,PIB0 K9F5608U0B-DCB0,DIB0,HCB0,HIB0

K9F5616U0B-YCB0,YIB0,PCB0,PIB0 K9F5616U0B-DCB0,DIB0,HCB0,HIB0

MANUFACTURE & DEVICE ID READ OPERATION

CLE

ALE

tAR

tREA

I/Ox

Read ID Command Maker Code Device Code

90h

00h

Address. 1cycle

ECh

FLASH MEMORY

Device Code*

Device Device Code*

K9F5608Q0B 35h K9F5608U0B 75h K9F5616Q0B XX45h K9F5616U0B XX55h

Page 27

K9F5608U0B-VCB0,VIB0,FCB0,FIB0 K9F5608Q0B-DCB0,DIB0,HCB0,HIB0 K9F5616Q0B-DCB0,DIB0,HCB0,HIB0 K9F5608U0B-YCB0,YIB0,PCB0,PIB0 K9F5608U0B-DCB0,DIB0,HCB0,HIB0

K9F5616U0B-YCB0,YIB0,PCB0,PIB0 K9F5616U0B-DCB0,DIB0,HCB0,HIB0

FLASH MEMORY

DEVICE OPERATION

PAGE READ

Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00h to the command register along with three address cycles. Once the command is latched, it does not need to be written for the following page read operation. Two types of operations are available : random read, serial page read. The random read mode is enabled when the page address is changed. The 528 bytes(X8 device) or 264 words(X16 device) of data within the selected page are transferred to the data registers in less than 10µs(tR). The system controller can detect the completion of this data transfer(tR) by analyzing the output of R/B pin. Once the data in a page is loaded into the registers, they may be read out in 50ns cycle time by sequentially pulsing RE. High to low transitions of the RE clock output the data starting from the selected column address up to the last column address[column 511/ 527(X8 device) 255 /263(X16 device) depending on the state of GND input pin]. The way the Read1 and Read2 commands work is like a pointer set to either the main area or the spare area. The spare area of 512 ~527 bytes(X8 device) or 256~263 words(X16 device) may be selectively accessed by writing the Read2 command with GND input pin low. Addresses A0~A3(X8 device) or A0~A2(X16 device) set the starting address of the spare area while addresses A4~A7 are ignored in X8 device case or A3~A7 must be "L" in X16 device case. The Read1 command is needed to move the pointer back to the main area. Figures 8, 9 show typical sequence and timings for each read operation.

Sequential Row Read is available only for K9F5608U0B_Y,P and K9F5608U0B_V,F :

After the data of last column address is clocked out, the next page is automatically selected for sequential row read. Waiting 10µs again allows reading the selected page. The sequential row read operation is terminated by bringing CE high. Unless the operation is aborted, the page address is automatically incremented for sequential row read as in Read1 operation and spare sixteen bytes of each page may be sequentially read. The Sequential Read 1 and 2 operation is allowed only within a block and after the last page of a block is readout, the sequential read operation must be terminated by bringing CE high. When the page address moves onto the next block, read command and address must be given. Figures 8-1, 9-1 show typical sequence and timings for sequential row read operation.

Figure 8. Read1 Operation

CLE

ALE

R/B

I/Ox

Start Add.(3Cycle)

00h

X8 device : A0 ~ A7 & A9 ~ A24

X16 device : A0 ~ A7 & A9 ~ A24

(00h Command)

Main array

On K9F5608U0B_Y,P or K9F5608U0B_V,F CE must be held low during tR

Data Output(Sequential)

(01h Command)

1st half array 2st half array

Data Field Spare Field

NOTE: 1) After data access on 2nd half array by 01h command, the start pointer is automatically moved to 1st half array (00h) at next cycle. 01h command is only available on X8 device(K9F5608X0B).

Data Field Spare Field

Page 28

K9F5608U0B-VCB0,VIB0,FCB0,FIB0 K9F5608Q0B-DCB0,DIB0,HCB0,HIB0 K9F5616Q0B-DCB0,DIB0,HCB0,HIB0 K9F5608U0B-YCB0,YIB0,PCB0,PIB0 K9F5608U0B-DCB0,DIB0,HCB0,HIB0

K9F5616U0B-YCB0,YIB0,PCB0,PIB0 K9F5616U0B-DCB0,DIB0,HCB0,HIB0

Figure 9. Read2 Operation

CLE

On K9F5608U0B_Y,P or K9F5608U0B_V,F CE must be held

low during tR

ALE

FLASH MEMORY

R/B

I/Ox

X8 device : A4 ~ A7 Don’t care

X16 device : A3 ~ A7 are "L"

Start Add.(3Cycle)

50h

X8 device : A0 ~ A3 & A9 ~ A24 X16 device : A0 ~ A2 & A9 ~ A24

Data Output(Sequential)

Spare Field

Main array

Data Field Spare Field

Figure 8-1. Sequential Row Read1 Operation (only for K9F5608U0B-Y,P and K9F5608U0B-V,F Valid with in a block )

R/B

≈

I/Ox

Block

00h

01h

(GND input=L, 00h Command)

1st half array 2nd half array

Start Add.(3Cycle)

A0 ~ A7 & A9 ~ A24

Data Field Spare Field

1st 2nd Nth

Data Output Data Output Data Output

1st 2nd Nth

(GND input=L, 01h Command)

1st half array 2nd half array

Data Field Spare Field

(528 Byte) (528 Byte)

(GND input=H, 00h Command)

1st half array 2nd half array

1st 2nd Nth

Data Field Spare Field

1st 2nd Nth

Page 29

K9F5608U0B-VCB0,VIB0,FCB0,FIB0 K9F5608Q0B-DCB0,DIB0,HCB0,HIB0 K9F5616Q0B-DCB0,DIB0,HCB0,HIB0 K9F5608U0B-YCB0,YIB0,PCB0,PIB0 K9F5608U0B-DCB0,DIB0,HCB0,HIB0

K9F5616U0B-YCB0,YIB0,PCB0,PIB0 K9F5616U0B-DCB0,DIB0,HCB0,HIB0

Figure 9-1. Sequential Row Read2 Operation (GND Input=Fixed Low)

(only for K9F5608U0B-Y,P and K9F5608U0B-V,F Valid with in a block)

FLASH MEMORY

R/B

I/Ox

50h

(A4 ~ A7 : Don′t Care)

Start Add.(3Cycle)

A0 ~ A3 & A9 ~ A24

Data Output

1st

Data Field Spare Field

≈

Data Output

2nd Nth

(16Byte) (16Byte)

1st Block

Nth

Data Output

Page 30

K9F5608U0B-VCB0,VIB0,FCB0,FIB0 K9F5608Q0B-DCB0,DIB0,HCB0,HIB0 K9F5616Q0B-DCB0,DIB0,HCB0,HIB0 K9F5608U0B-YCB0,YIB0,PCB0,PIB0 K9F5608U0B-DCB0,DIB0,HCB0,HIB0

K9F5616U0B-YCB0,YIB0,PCB0,PIB0 K9F5616U0B-DCB0,DIB0,HCB0,HIB0

FLASH MEMORY

PAGE PROGRAM

The device is programmed basically on a page basis, but it does allow multiple partial page programing of a byte/word or consecutive bytes/words up to 528(X8 device) or 264(X16 device), in a single page program cycle. The number of consecutive partial page programming operation within the same page without an intervening erase operation should not exceed 2 for main array and 3 for spare array. The addressing may be done in any random order in a block. A page program cycle consists of a serial data loading period in which up to 528 bytes(X8 device) or 264 words(X16 device) of data may be loaded into the page register, followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell. About the pointer operation, please refer to the attached technical notes. The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the three address cycles input and then serial data loading. The words other than those to be programmed do not need to be loaded.The Page Program confirm command(10h) initiates the programming process. Writing 10h alone without previously entering the serial data will not initiate the programming process. The internal write controller automatically executes the algorithms and timings necessary for program and verify, thereby freeing the system controller for other tasks. Once the program process starts, the Read Status Register command may be entered, with RE and CE low, to read the status register. The system controller can detect the completion of a program cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset command are valid while programming is in progress. When the Page Program is complete, the Write Status Bit(I/O 0) may be checked(Figure

10). The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains in Read Status command mode until another valid command is written to the command register.

Figure 10. Program Operation

R/B

tPROG

I/Ox

80h

Address & Data Input I/O0

10h 70h

Fail

Pass

COPY-BACK PROGRAM

The copy-back program is configured to quickly and efficiently rewrite data stored in one page within the array to another page within the same array without utilizing an external memory. Since the time-consuming sequently-reading and its re-loading cycles are removed, the system performance is improved. The benefit is especially obvious when a portion of a block is updated and the rest of the block also need to be copied to the newly assigned free block. The operation for performing a copy-back is a sequential execution of page-read without burst-reading cycle and copying-program with the address of destination page. A normal read operation with "00h" command with the address of the source page moves the whole 528bytes/264words(X8 device:528bytes, X16 device:264words) data into the internal buffer. As soon as the Flash returns to Ready state, copy-back programming command "8Ah" may be given with three address cycles of target page followed. The data stored in the internal buffer is then programmed directly into the memory cells of the destination page. Once the Copy-Back Program is finished, any additional partial page programming into the copied pages is prohibited before erase. Since the memory array is internally partitioned into two different planes, copy-back program is allowed only within the same memory plane. Thus, A14, the plane address, of source and destination page address must be the same. "When there is a program-failure at Copy-Back operation, error is reported by pass/fail status. But, if Copy-Back

operations are accumulated over time, bit error due to charge loss is not checked by external error detection/correction scheme. For this reason, two bit error correction is recommended for the use of Copy-Back operation."

Figure 11. Copy-Back Program Operation

R/B

I/Ox

00h

Add.(3Cycles)

Source Address

Add.(3Cycles)

8Ah 70h

Destination Address

tPROG

I/O0

Fail

Pass

Page 31

K9F5608U0B-VCB0,VIB0,FCB0,FIB0 K9F5608Q0B-DCB0,DIB0,HCB0,HIB0 K9F5616Q0B-DCB0,DIB0,HCB0,HIB0 K9F5608U0B-YCB0,YIB0,PCB0,PIB0 K9F5608U0B-DCB0,DIB0,HCB0,HIB0

K9F5616U0B-YCB0,YIB0,PCB0,PIB0 K9F5616U0B-DCB0,DIB0,HCB0,HIB0

FLASH MEMORY

BLOCK ERASE

The Erase operation is done on a block basis. Block address loading is accomplished in two cycles initiated by an Erase Setup command(60h). Only address A14 to A24 is valid while A9 to A13 is ignored. The Erase Confirm command(D0h) following the block address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external noise conditions. At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-verify. When the erase operation is completed, the Write Status Bit(I/O 0) may be checked. Figure 12 details the sequence.

Figure 12. Block Erase Operation

R/B

tBERS

I/Ox

60h

Address Input(2Cycle)

Block Add. : A9 ~ A24

D0h

70h

I/O0

Fail

Pass

READ STATUS

The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE does not need to be toggled for updated status. Refer to table 4 for specific Status Register definitions. The command register remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read cycle, a read command(00h or 50h) should be given before sequential page read cycle.

Table4. Read Status Register Definition

I/O # Status Definition

I/O 0 Program / Erase

I/O 1 I/O 2 "0" I/O 3 "0" I/O 4 "0" I/O 5 "0" I/O 6 Device Operation "0" : Busy "1" : Ready I/O 7 Write Protect "0" : Protected "1" : Not Protected

I/O 8~15 Not use Don’t care

Reserved for Future

Use

"0" : Successful Program / Erase "1" : Error in Program / Erase "0"

Page 32

K9F5608U0B-VCB0,VIB0,FCB0,FIB0 K9F5608Q0B-DCB0,DIB0,HCB0,HIB0 K9F5616Q0B-DCB0,DIB0,HCB0,HIB0 K9F5608U0B-YCB0,YIB0,PCB0,PIB0 K9F5608U0B-DCB0,DIB0,HCB0,HIB0

K9F5616U0B-YCB0,YIB0,PCB0,PIB0 K9F5616U0B-DCB0,DIB0,HCB0,HIB0

FLASH MEMORY

READ ID

The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of 00h. Two read cycles sequentially output the manufacture code(ECh), and the device code respectively. The command register remains in Read ID mode until further commands are issued to it. Figure 13 shows the operation sequence.

Figure 13. Read ID Operation

CLE

tCEA

tAR

ALE

I/Ox

90h

00h

Address. 1cycle Maker code Device code

tWHR

tREA

ECh

Device Device Code* K9F5608Q0B 35h K9F5608U0B 75h K9F5616Q0B 45h K9F5616U0B 55h

Device Code*

RESET

The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and the Status Register is cleared to value C0h when WP is high. Refer to table 5 for device status after reset operation. If the device is already in reset state a new reset command will not be accepted by the command register. The R/B pin transitions to low for tRST after the Reset command is written. Refer to Figure 14 below.

Figure 14. RESET Operation

tRST

R/B

I/Ox

FFh

Table5. Device Status

Operation Mode Read 1 Waiting for next command

After Power-up After Reset

Page 33

K9F5608U0B-VCB0,VIB0,FCB0,FIB0 K9F5608Q0B-DCB0,DIB0,HCB0,HIB0 K9F5616Q0B-DCB0,DIB0,HCB0,HIB0 K9F5608U0B-YCB0,YIB0,PCB0,PIB0 K9F5608U0B-DCB0,DIB0,HCB0,HIB0

K9F5616U0B-YCB0,YIB0,PCB0,PIB0 K9F5616U0B-DCB0,DIB0,HCB0,HIB0

FLASH MEMORY

READY/BUSY

The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command register or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. Because pull-up resistor value is related to tr(R/B) and current drain during busy(ibusy) , an appropriate value can be obtained with the following reference chart(Fig 15). Its value can be determined by the following guidance.

VCC

R/B

open drain output

ibusy

1.8V device - VOL : 0.1V, VOH : VCCq-0.1V

3.3V device - VOL : 0.4V, VOH : 2.4V

Ready Vcc

VOH

GND

Device

Fig 15 Rp vs tr ,tf & Rp vs ibusy

@ Vcc = 1.8V, Ta = 25

1.7

Ibusy

0.85

1.7

300n 3m

tr,tf [s]

200n

100n

1K 2K 3K

C , CL = 30pF

1.7

Rp(ohm)

0.57

120

0.43

1.7

Rp value guidance

VOL

Busy

@ Vcc = 3.3V, Ta = 25

2.4

300n 3m

tr,tf [s]

200n

Ibusy [A]

Ibusy

1.2

200

C , CL = 100pF

300

0.8

400

100n

100

3.6

1K 2K 3K

0.6

3.6

Rp(ohm)

Ibusy [A]

Rp(min, 1.8V part) =

Rp(min, 3.3V part) =

VCC(Max.) - VOL(Max.)

IOL + ΣIL

VCC(Max.) - VOL(Max.)

IOL + ΣIL

where IL is the sum of the input currents of all devices tied to the R/B pin.

Rp(max) is determined by maximum permissible limit of tr

1.85V

3mA + ΣIL

3.2V

8mA + ΣIL

Page 34

K9F5608U0B-VCB0,VIB0,FCB0,FIB0 K9F5608Q0B-DCB0,DIB0,HCB0,HIB0 K9F5616Q0B-DCB0,DIB0,HCB0,HIB0 K9F5608U0B-YCB0,YIB0,PCB0,PIB0 K9F5608U0B-DCB0,DIB0,HCB0,HIB0

Data Protection & Powerup sequence

The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below about 1.3V. WP pin provides hardware protection and is recommended to be kept at VIL during power-up and power-down and recovery time of minimum 10µs is required before internal circuit gets ready for any command sequences as shown in Figure 16. The two step command sequence for program/erase provides additional software protection.

Figure 16. AC Waveforms for Power Transition

K9F5616U0B-YCB0,YIB0,PCB0,PIB0 K9F5616U0B-DCB0,DIB0,HCB0,HIB0

FLASH MEMORY

VCC

1.8V device : ~ 1.5V

3.3V device : ~ 2.5V

10µs

High

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1.8V device : ~ 1.5V

3.3V device : ~ 2.5V

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