Datasheet K9F2808U0C-YCB0, K9F2808U0C-VIB0, K9F2808U0C-VCB0, K9F2808U0C-DIB0, K9F2808U0C-DCB0 Datasheet (Samsung)

K9F2816U0C-YCB0,YIB0

FLASH MEMORY

1

K9F2816U0C-DCB0,DIB0

K9F2808U0C-YCB0,YIB0
K9F2808U0C-DCB0,DIB0

K9F2808Q0C-DCB0,DIB0 K9F2816Q0C-DCB0,DIB0

K9F2808U0C-VCB0,VIB0

Document Title

16M x 8 Bit , 8M x 16 Bit NAND Flash Memory

Revision History

The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right

to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near you.

Revision No.

0.0

1.0

2.0

2.1

2.2

2.3

2.4

Remark

Advance

Advance

Preliminary

History

Initial issue.

TBGA PKG Dimension Change
48-Ball, 6.0mm x 8.5mm --> 63-Ball, 9.0mm x 11.0mm

1.A3 Pin assignment of TBGA Package is changed.(Page 4)
(before) NC --> (after) Vss

2. Add the Rp vs tr ,tf & Rp vs ibusy graph for 1.8V device (Page 32)

3. Add the data protection Vcc guidence for 1.8V device - below about

1.1V. (Page 33)

The min. Vcc value 1.8V devices is changed.
K9F28XXQ0C : Vcc 1.65V~1.95V --> 1.70V~1.95V

Pb-free Package is added.
K9F2808U0C-FCB0,FIB0
K9F2808Q0C-HCB0,HIB0
K9F2816U0C-HCB0,HIB0
K9F2816U0C-PCB0,PIB0
K9F2816Q0C-HCB0,HIB0
K9F2808U0C-HCB0,HIB0
K9F2808U0C-PCB0,PIB0

Some AC parameter is changed(K9F28XXQ0C).
tWC tWH tWP tRC tREH tRP tREA tCEA

Before 45 15 25 50 15 25 30 45
After 60 20 40 60 20 40 40 55

New definition of the number of invalid blocks is added.

(Minimum 502 valid blocks are guaranteed for each contiguous 64Mb

memory space)

Draft Date

Apr. 15th 2002

Sep. 5th 2002

Dec.10th 2002

Mar. 6th 2003

Mar. 13rd 2003

Mar. 26th 2003

May. 24th 2003

Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site.
http://www.intl.samsungsemi.com/Memory/Flash/datasheets.html

K9F2816U0C-YCB0,YIB0

FLASH MEMORY

2

K9F2816U0C-DCB0,DIB0

K9F2808U0C-YCB0,YIB0
K9F2808U0C-DCB0,DIB0

K9F2808Q0C-DCB0,DIB0 K9F2816Q0C-DCB0,DIB0

K9F2808U0C-VCB0,VIB0

GENERAL DESCRIPTION

FEATURES

• Voltage Supply

- 1.8V device(K9F28XXQ0C) : 1.7~1.95V

- 3.3V device(K9F28XXU0C) : 2.7 ~ 3.6 V

• Organization

- Memory Cell Array

- X8 device(K9F2808X0C) : (16M + 512K)bit x 8bit

- X16 device(K9F2816X0C) : (8M + 256K)bit x 16bit

- Data Register

- X8 device(K9F2808X0C) : (512 + 16)bit x 8bit

- X16 device(K9F2816X0C) : (256 + 8)bit x16bit

• Automatic Program and Erase

- Page Program

- X8 device(K9F2808X0C) : (512 + 16)Byte

- X16 device(K9F2816X0C) : (256 + 8)Word

- Block Erase :

- X8 device(K9F2808X0C) : (16K + 512)Byte

- X16 device(K9F2816X0C) : ( 8K + 256)Word

• Page Read Operation

- Page Size

- X8 device(K9F2808X0C) : (512 + 16)Byte

- X16 device(K9F2816X0C) : (256 + 8)Word

- Random Access : 10µs(Max.)

- Serial Page Access : 50ns(Min.)

16M x 8 Bit / 8M x 16 Bit NAND Flash Memory

• Fast Write Cycle Time

- Program time : 200µs(Typ.)

- Block Erase Time : 2ms(Typ.)

• Command/Address/Data Multiplexed I/O Port

• Hardware Data Protection

- Program/Erase Lockout During Power Transitions

• Reliable CMOS Floating-Gate Technology

- Endurance : 100K Program/Erase Cycles

- Data Retention : 10 Years

• Command Register Operation

• Unique ID for Copyright Protection

• Package

- K9F28XXU0C-YCB0/YIB0
48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)

- K9F28XXU0C-PCB0/PIB0
48 - Pin TSOP I (12 x 20 / 0.5 mm pitch) - Pb-free Package

- K9F28XXX0C-DCB0/DIB0
63 - Ball TBGA ( 9 x 11 /0.8mm pitch , Width 1.0 mm)

- K9F28XXX0C-HCB0/HIB0
63 - Ball TBGA ( 9 x 11 /0.8mm pitch , Width 1.0 mm)

- Pb-free Package

- K9F2808U0C-VCB0/VIB0
48 - Pin WSOP I (12X17X0.7mm)

- K9F2808U0C-FCB0/FIB0
48 - Pin WSOP I (12X17X0.7mm) - Pb-free Package
* K9F2808U0C-V/F(WSOPI ) is the same device as

K9F2808U0C-Y/P(TSOP1) except package type.

Offered in 16Mx8bit or 8Mx16bit, the K9F28XXX0C is 128M bit with spare 4M bit capacity. The device is offered in 1.8V or 3.3V Vcc.
Its NAND cell provides the most cost-effective solutIon for the solid state mass storage market. A program operation can be per­formed in typical 200µs on the 528-byte(X8 device) or 264-word(X16 device) page and an erase operation can be performed in typ­ical 2ms on a 16K-byte(X8 device) or 8K-word(X16 device) block. Data in the page can be read out at 50ns cycle time per word. The
I/O pins serve as the ports for address and data input/output as well as command input. The on-chip write control automates all pro­gram and erase functions including pulse repetition, where required, and internal verification and margining of data. Even the write­intensive systems can take advantage of the K9F28XXX0C’s extended reliability of 100K program/erase cycles by providing
ECC(Error Correcting Code) with real time mapping-out algorithm.
The K9F28XXX0C is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable
applications requiring non-volatility.

PRODUCT LIST

Part Number Vcc Range Organization PKG Type

K9F2808Q0C-D,H

1.7 ~ 1.95V

X8

TBGA

K9F2816Q0C-D,H X16
K9F2808U0C-Y,P

2.7 ~ 3.6V

X8

TSOP1

K9F2808U0C-D,H TBGA

K9F2808U0C-V,F WSOP1

K9F2816U0C-Y,P

X16

TSOP1

K9F2816U0C-D,H TBGA

K9F2816U0C-YCB0,YIB0

FLASH MEMORY

3

K9F2816U0C-DCB0,DIB0

K9F2808U0C-YCB0,YIB0
K9F2808U0C-DCB0,DIB0

K9F2808Q0C-DCB0,DIB0 K9F2816Q0C-DCB0,DIB0

K9F2808U0C-VCB0,VIB0

PIN CONFIGURATION (TSOP1)

K9F28XXU0C-YCB0,PCB0/YIB0,PIB0

N.C
N.C
N.C
N.C
N.C

GND

R/B
RE

CE
N.C
N.C
Vcc
Vss
N.C
N.C

CLE
ALE

WE

WP
N.C
N.C
N.C
N.C
N.C

Vss
I/O15
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
N.C
N.C
Vcc
N.C
N.C
N.C
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
Vss

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

N.C
N.C
N.C
N.C
N.C

GND

R/B
RE

CE
N.C
N.C
Vcc
Vss
N.C
N.C

CLE
ALE

WE
WP
N.C
N.C
N.C
N.C
N.C

N.C
N.C
N.C
N.C
I/O7
I/O6
I/O5
I/O4
N.C
N.C
N.C
Vcc
Vss
N.C
N.C
N.C
I/O3
I/O2
I/O1
I/O0
N.C
N.C
N.C
N.C

X8X16 X16X8

PACKAGE DIMENSIONS

48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)

48 - TSOP1 - 1220F

Unit :mm/Inch

0.787±0.008

20.00±0.20

#1

#24

0.20

+0.07

-0.03

0.008

+0.003

-0.001

0.50

0.0197

#48

#25

0.488

12.40

MAX

12.00

0.472

0.10

0.004

MAX

0.25

0.010

( )

0.039±0.002

1.00±0.05

0.002

0.05
MIN

0.047

1.20
MAX

0.45~0.75

0.018~0.030

0.724±0.004

18.40±0.10

0~8°

0.010

0.25

TYP

0.125

+0.075

0.035

0.005

+0.003

-0.001

0.50

0.020

( )

K9F2816U0C-YCB0,YIB0

FLASH MEMORY

4

K9F2816U0C-DCB0,DIB0

K9F2808U0C-YCB0,YIB0
K9F2808U0C-DCB0,DIB0

K9F2808Q0C-DCB0,DIB0 K9F2816Q0C-DCB0,DIB0

K9F2808U0C-VCB0,VIB0

K9F28XXX0C-DCB0,HCB0/DIB0,HIB0

R/B/WE/CEVssALE/WP

/RE CLE

NCNC

NC NC

Vcc

NCNC I/O0

I/O1NC NC VccQ I/O5 I/O7

VssI/O6I/O4I/O3I/O2Vss

NC

NC

NC

NC NC

NC

NC NC

NCNCNC

NC

NC NC NC

NC

NC

NC

NC

NC

NC

NC NC

NC

NC NC

NC

NC

NC NC

NCNC

NC NC

NC

NC

NC NC

NC

DNU DNU

DNU

NC

NC NC

NCNC

NC NC

NC

R/B/WE/CEVssALE/WP

/RE CLE

I/O7I/O5

I/O12 IO14

Vcc

I/O10I/O8 I/O1

I/O9I/O0 I/O3 VccQ I/O6 I/O15

VssI/O13I/O4I/O11I/O2Vss

NC

NC

NC

NC NC

NC

NC NC

NCNCNC

NC

NC NC NC

NC

NC

NC

NC

NC

X16

X8

PIN CONFIGURATION (TBGA)

(Top View) (Top View)

63-Ball TBGA (measured in millimeters)

PACKAGE DIMENSIONS

9.00±0.10

#A1

Side View

Top View

0.90±0.10

0.45±0.05

4 3 2 1

A
B
C
D

G

Bottom View

11.00±0.10

63-∅0.45±0.05

0.80 x7= 5.60

11.00±0.10

0.80 x5= 4.00

0.80

0.32±0.05

0.08MAX

B

A

2.80

2.00

9.00±0.10

(Datum B)

(Datum A)

0.20

M

A B

∅

0.80

0.80 x11= 8.80

0.80 x9= 7.20

6 5

9.00±0.10

E
F

H

K9F2816U0C-YCB0,YIB0

FLASH MEMORY

5

K9F2816U0C-DCB0,DIB0

K9F2808U0C-YCB0,YIB0
K9F2808U0C-DCB0,DIB0

K9F2808Q0C-DCB0,DIB0 K9F2816Q0C-DCB0,DIB0

K9F2808U0C-VCB0,VIB0

PIN CONFIGURATION (WSOP1)

K9F2808U0C-VCB0,FCB0/VIB0,FIB0

PACKAGE DIMENSIONS

48-PIN LEAD/LEAD FREE PLASTIC VERY VERY THIN SMALL OUT-LINE PACKAGE TYPE (I)

48 - WSOP1 - 1217F

Unit :mm

15.40±0.10

#1

#24

0.20

+0.07

-0.03

0.16

+0.07

-0.03

0.50TYP

(0.50±0.06)

#48

#25

12.00±0.10

0.10

+0.075

-0.035

0.58±0.04

0.70 MAX

(0.1Min)

17.00±0.20

0

°

~

8

°

0.45~0.75

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

N.C
N.C

DNU

N.C
N.C
N.C
R/B
RE

CE

DNU

N.C
Vcc
Vss
N.C

DNU

CLE
ALE

WE
WP
N.C
N.C

DNU

N.C
N.C

N.C
N.C
DNU
N.C
I/O7
I/O6
I/O5
I/O4
N.C
DNU
N.C
Vcc
Vss
N.C
DNU
N.C
I/O3
I/O2
I/O1
I/O0
N.C
DNU
N.C
N.C

K9F2816U0C-YCB0,YIB0

FLASH MEMORY

6

K9F2816U0C-DCB0,DIB0

K9F2808U0C-YCB0,YIB0
K9F2808U0C-DCB0,DIB0

K9F2808Q0C-DCB0,DIB0 K9F2816Q0C-DCB0,DIB0

K9F2808U0C-VCB0,VIB0

PIN DESCRIPTION

Pin Name Pin Function

I/O0 ~ I/O7

(K9F2808X0C)

I/O0 ~ I/O15

(K9F2816X0C)

DATA INPUTS/OUTPUTS

The I/O pins are used to input command, address and data, and to output data during read operations. The
I/O pins float to high-z when the chip is deselected or when the outputs are disabled.
I/O8 ~ I/O15 are used only in X16 organization device. Since command input and address input are x8 oper­ation, I/O8 ~ I/O15 are not used to input command & address. I/O8 ~ I/O15 are used only for data input and
output.

CLE

COMMAND LATCH ENABLE

The CLE input controls the activating path for commands sent to the command register. When active high,
commands are latched into the command register through the I/O ports on the rising edge of the WE signal.

ALE

ADDRESS LATCH ENABLE

The ALE input controls the activating path for address to the internal address registers. Addresses are
latched on the rising edge of WE with ALE high.

CE

CHIP ENABLE

The CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and
the device does not return to standby mode in program or erase opertion. Regarding CE control during read
operation, refer to ’Page read’ section of Device operation .

RE

READ ENABLE

The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid
tREA after the falling edge of RE which also increments the internal column address counter by one.

WE

WRITE ENABLE

The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of
the WE pulse.

WP

WRITE PROTECT

The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage
generator is reset when the WP pin is active low.

R/B

READY/BUSY OUTPUT

The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or
random read operation is in process and returns to high state upon completion. It is an open drain output and
does not float to high-z condition when the chip is deselected or when outputs are disabled.

VccQ

OUTPUT BUFFER POWER

VCCQ is the power supply for Output Buffer.
VccQ is internally connected to Vcc, thus should be biased to Vcc.

Vcc

POWER

VCC is the power supply for device.

Vss GROUND

N.C

NO CONNECTION

Lead is not internally connected.

GND

GND INPUT FOR ENABLING SPARE AREA

To do sequential read mode including spare area , connect this input pin to Vss or set to static low state
or to do sequential read mode excluding spare area , connect this input pin to Vcc or set to static high state.

DNU

DO NOT USE

Leave it disconnected.

NOTE : Connect all VCC and VSS pins of each device to common power supply outputs.
Do not leave VCC or VSS disconnected.

K9F2816U0C-YCB0,YIB0

FLASH MEMORY

7

K9F2816U0C-DCB0,DIB0

K9F2808U0C-YCB0,YIB0
K9F2808U0C-DCB0,DIB0

K9F2808Q0C-DCB0,DIB0 K9F2816Q0C-DCB0,DIB0

K9F2808U0C-VCB0,VIB0

512Byte 16 Byte

Figure 1-1. K9F2808X0C (X8) FUNCTIONAL BLOCK DIAGRAM

Figure 2-1. K9F2808X0C (X8) ARRAY ORGANIZATION

NOTE : Column Address : Starting Address of the Register.

00h Command(Read) : Defines the starting address of the 1st half of the register.
01h Command(Read) : Defines the starting address of the 2nd half of the register.
* A8 is set to "Low" or "High" by the 00h or 01h Command.
* The device ignores any additional input of address cycles than reguired.

* L must be set to "Low".

I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7

1st Cycle A0 A1 A2 A3 A4 A5 A6 A7

2nd Cycle A9 A10 A11 A12 A13 A14 A15 A16

3rd Cycle A17 A18 A19 A20 A21 A22 A23 L*

VCC

X-Buffers

128M + 4M Bit

Command

NAND Flash

ARRAY

(512 + 16)Byte x 32768

Y-Gating

Page Register & S/A

I/O Buffers & Latches

Latches
& Decoders

Y-Buffers
Latches
& Decoders

Register

Control Logic

& High Voltage

Generator

Global Buffers

Output

Driver

VSS

A9 - A23

A0 - A7

Command

CE
RE
WE

WP

I/0 0
I/0 7

VCC/VCCQ
VSS

A8

1st half Page Register
(=256 Bytes)

2nd half Page Register
(=256 Bytes)

32K Pages
(=1,024 Blocks)

512 Byte

8 bit

16 Byte

1 Block =32 Pages
= (16K + 512) Byte

I/O 0 ~ I/O 7

1 Page = 528 Byte
1 Block = 528 Byte x 32 Pages
= (16K + 512) Byte
1 Device = 528Bytes x 32Pages x 1024 Blocks
= 132 Mbits

Column Address
Row Address

(Page Address)

Page Register

CLE ALE

K9F2816U0C-YCB0,YIB0

FLASH MEMORY

8

K9F2816U0C-DCB0,DIB0

K9F2808U0C-YCB0,YIB0
K9F2808U0C-DCB0,DIB0

K9F2808Q0C-DCB0,DIB0 K9F2816Q0C-DCB0,DIB0

K9F2808U0C-VCB0,VIB0

256Word 8 Word

Figure 2-2. K9F2816X0C (X16) ARRAY ORGANIZATION

NOTE : Column Address : Starting Address of the Register.

* L must be set to "Low".

I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O8 to 15

1st Cycle A0 A1 A2 A3 A4 A5 A6 A7

L*

2nd Cycle A9 A10 A11 A12 A13 A14 A15 A16

L*

3rd Cycle A17 A18 A19 A20 A21 A22 A23 L*

L*

Page Register
(=256 Words)

32K Pages
(=1,024 Blocks)

256 Word

16 bit

8 Word

1 Block =32 Pages
= (8K + 256) Word

I/O 0 ~ I/O 15

1 Page = 264 Word
1 Block = 264 Word x 32 Pages
= (8K + 256) Word
1 Device = 264Words x 32Pages x 1024 Blocks
= 132 Mbits

Column Address
Row Address

(Page Address)

Page Register

Figure 1-2. K9F2816X0C (X16) FUNCTIONAL BLOCK DIAGRAM

VCC

X-Buffers

128M + 4M Bit

Command

NAND Flash

ARRAY

(256 + 8)Word x 32768

Y-Gating

Page Register & S/A

I/O Buffers & Latches

Latches
& Decoders

Y-Buffers
Latches
& Decoders

Register

Control Logic

& High Voltage

Generator

Global Buffers

Output

Driver

VSS

A9 - A23

A0 - A7

Command

CE
RE
WE

WP

I/0 0
I/0 15

VCC/VCCQ
VSS

CLE ALE

K9F2816U0C-YCB0,YIB0

FLASH MEMORY

9

K9F2816U0C-DCB0,DIB0

K9F2808U0C-YCB0,YIB0
K9F2808U0C-DCB0,DIB0

K9F2808Q0C-DCB0,DIB0 K9F2816Q0C-DCB0,DIB0

K9F2808U0C-VCB0,VIB0

PRODUCT INTRODUCTION

The K9F28XXX0C is a 132Mbit(138,412,032 bit) memory organized as 32,768 rows(pages) by 528(X8 device) or 264(X16 device)
columns. Spare eight columns are located from column address of 512~527(X8 device) or 256~263(X16 device). A 528-byte(X8
device) or 264-word(X16 device) data register is connected to memory cell arrays accommodating data transfer between the I/O
buffers and memory during page read and page program operations. The memory array is made up of 16 cells that are serially con­nected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of two NAND structures. A NAND
structure consists of 16 cells. Total 16896 NAND cells reside in a block. The array organization is shown in Figure 2-1,2-2. The pro­gram and read operations are executed on a page basis, while the erase operation is executed on a block basis. The memory array
consists of 1024 separately erasable 16K-Byte(X8 device) or 8K-Word(X16 device) blocks. It indicates that the bit by bit erase oper­ation is prohibited on the K9F28XXX0C.
The K9F28XXX0C has addresses multiplexed into 8 I/Os(X16 device case : lower 8 I/Os). K9F2816X0C allows sixteen bit wide data
transport into and out of page registers. This scheme dramatically reduces pin counts while providing high performance and allows
systems upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written
through I/O’s by bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and
Address Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one
bus cycle. For example, Reset command, Read command, Status Read command, etc require just one cycle bus. Some other com­mands like Page Program and Copy-back Program and Block Erase, require two cycles: one cycle for setup and the other cycle for
execution. The 16K-byte(X8 device) or 32K-word(X16 device) physical space requires 24 addresses, thereby requiring three cycles
for word-level addressing: column address, low row address and high row address, in that order. Page Read and Page Program
need the same three address cycles following the required command input. In Block Erase operation, however, only the two row
address cycles are used. Device operations are selected by writing specific commands into the command register. Table 1 defines
the specific commands of the K9F28XXX0C.

The device includes one block sized OTP(One Time Programmable), which can be used to increase system security or to provide
identification capabilities. Detailed information can be obtained by contact with Samsung.

Table 1. COMMAND SETS

NOTE: 1. The 00h command defines starting address of the 1st half of registers.

The 01h command defines starting address of the 2nd half of registers.
After data access on 2nd half of register by the 01h command, start pointer is automatically moved to
1st half register(00h) on the next cycle.

Function 1st. Cycle 2nd. Cycle Acceptable Command during Busy

Read 1

00h/01h

(1)

-

Read 2

50h

­Read ID 90h ­Reset FFh - O
Page Program 80h 10h
Block Erase 60h D0h
Read Status 70h - O

Caution : Any undefined command inputs are prohibited except for above command set of Table 1.

K9F2816U0C-YCB0,YIB0

FLASH MEMORY

10

K9F2816U0C-DCB0,DIB0

K9F2808U0C-YCB0,YIB0
K9F2808U0C-DCB0,DIB0

K9F2808Q0C-DCB0,DIB0 K9F2816Q0C-DCB0,DIB0

K9F2808U0C-VCB0,VIB0

DC AND OPERATING CHARACTERISTICS(Recommended operating conditions otherwise noted.)

Parameter Symbol Test Conditions

K9F28XXQ0C(1.8V) K9F28XXU0C(3.3V) Unit

Min Typ Max Min Typ Max

Operat-

ing

Current

Sequential Read ICC1

tRC=50ns, CE=VIL
IOUT=0mA

- 8 15 - 10 20

mA

Program ICC2 - - 8 15 - 10 20

Erase ICC3 - - 8 15 - 10 20
Stand-by Current(TTL) ISB1 CE=VIH, WP=0V/VCC - - 1 - - 1
Stand-by Current(CMOS) ISB2 CE=VCC-0.2, WP=0V/VCC - 10 50 - 10 50

µA

Input Leakage Current ILI VIN=0 to Vcc(max) - - ±10 - - ±10
Output Leakage Current ILO VOUT=0 to Vcc(max) - - ±10 - - ±10

Input High Voltage VIH

I/O pins VCCQ-0.4 -

VCCQ

+0.3

2.0 - VCCQ+0.3

V

Except I/O pins VCC-0.4 -

VCC

+0.3

2.0 - VCC+0.3

Input Low Voltage, All inputs VIL - -0.3 - 0.4 -0.3 - 0.8

Output High Voltage Level VOH

K9F28XXQ0C :IOH=-100µA
K9F28XXU0C :IOH=-400µA

VCCQ-0.1 - - 2.4 - -

Output Low Voltage Level VOL

K9F28XXQ0C :IOL=100uA
K9F28XXU0C :IOL=2.1mA

- - 0.1 - - 0.4

Output Low Current(R/B) IOL(R/B)

K9F28XXQ0C :VOL=0.1V
K9F28XXU0C :VOL=0.4V

3 4 - 8 10 - mA

RECOMMENDED OPERATING CONDITIONS

(Voltage reference to GND, K9F28XXX0C-XCB0 :TA=0 to 70°C, K9F28XXX0C-XIB0:TA=-40 to 85°C)

Parameter Symbol

K9F28XXQ0C(1.8V)

K9F28XXU0C(3.3V)

Unit

Min Typ. Max Min Typ. Max

Supply Voltage VCC 1.7 1.8 1.95 2.7 3.3 3.6 V
Supply Voltage VCCQ 1.7 1.8 1.95 2.7 3.3 3.6 V
Supply Voltage VSS 0 0 0 0 0 0 V

ABSOLUTE MAXIMUM RATINGS

NOTE :

1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns.
Maximum DC voltage on input/output pins is VCC,+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.

2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions
as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Parameter Symbol

Rating

Unit

K9F28XXQ0C(1.8V) K9F28XXU0C(3.3V)

Voltage on any pin relative to VSS

VIN/OUT -0.6 to + 2.45 -0.6 to + 4.6

V

VCC -0.2 to + 2.45 -0.6 to + 4.6

VCCQ -0.2 to + 2.45 -0.6 to + 4.6

Temperature Under Bias

K9F28XXX0C-XCB0

TBIAS

-10 to +125
°C

K9F28XXX0C-XIB0 -40 to +125

Storage Temperature

K9F28XXX0C-XCB0

TSTG -65 to +150 °C

K9F28XXX0C-XIB0

Short Circuit Current Ios 5 mA

K9F2816U0C-YCB0,YIB0

FLASH MEMORY

11

K9F2816U0C-DCB0,DIB0

K9F2808U0C-YCB0,YIB0
K9F2808U0C-DCB0,DIB0

K9F2808Q0C-DCB0,DIB0 K9F2816Q0C-DCB0,DIB0

K9F2808U0C-VCB0,VIB0

CAPACITANCE(TA=25°C, VCC=1.8V/3.3V, f=1.0MHz)

NOTE : Capacitance is periodically sampled and not 100% tested.

Item Symbol Test Condition Min Max Unit

Input/Output Capacitance CI/O VIL=0V - 10 pF
Input Capacitance CIN VIN=0V - 10 pF

VALID BLOCK

NOTE :

1. The K9F28XXX0C may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid
blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase
or program factory-marked bad blocks. Refer to the attached technical notes for a appropriate management of invalid blocks.

2. The 1st block, which is placed on 00h block address, is fully guaranteed to be a valid block, does not require Error Correction.

3. Minimum 502 valid blocks are guaranteed for each contiguous 64Mb memory space.

Parameter Symbol Min Typ. Max Unit

Valid Block Number NVB 1004 - 1024 Blocks

Program/Erase Characteristics

Parameter Symbol Min Typ Max Unit

Program Time tPROG - 200 500 µs
Number of Partial Program Cycles

in the Same Page

Main Array

Nop

- - 2 cycles

Spare Array - - 3 cycles

Block Erase Time tBERS - 2 3 ms

AC TEST CONDITION

(K9F28XXX0C-XCB0 :TA=0 to 70°C, K9F28XXX0C-XIB0:TA=-40 to 85°C
K9F28XXQ0C : Vcc=1.7V~1.95V , K9F28XXU0C : Vcc=2.7V~3.6V unless otherwise noted)

Parameter K9F28XXQ0C K9F28XXU0C

Input Pulse Levels 0V to VccQ 0.4V to 2.4V
Input Rise and Fall Times 5ns 5ns
Input and Output Timing Levels VccQ/2 1.5V
K9F28XXQ0C:Output Load (VccQ:1.8V +/-10%)

K9F28XXU0C:Output Load (VccQ:3.0V +/-10%)

1 TTL GATE and CL=30pF 1 TTL GATE and CL=50pF

K9F28XXU0C:Output Load (VccQ:3.3V +/-10%) - 1 TTL GATE and CL=100pF

MODE SELECTION

NOTE : 1. X can be VIL or VIH.

2. WP should be biased to CMOS high or CMOS low for standby.

CLE ALE CE WE RE GND WP Mode

H L L H X X

Read Mode

Command Input
L H L H X X Address Input(3clock)
H L L H X H

Write Mode

Command Input
L H L H X H Address Input(3clock)
L L L H L H Data Input
L L L H L X Data Output
L L L H H

L

X During Read(Busy) on K9F2808U0C_Y,P or K9F2808U0C_V,F

X X X X H

L

X

During Read(Busy) on the devices except K9F2808U0C_Y,P
and K9F2808U0C_V,F

X X X X X L H During Program(Busy)
X X X X X X H During Erase(Busy)
X

X

(1)

X X X X L Write Protect

X X H X X 0V

0V/VCC

(2)

Stand-by

K9F2816U0C-YCB0,YIB0

FLASH MEMORY

12

K9F2816U0C-DCB0,DIB0

K9F2808U0C-YCB0,YIB0
K9F2808U0C-DCB0,DIB0

K9F2808Q0C-DCB0,DIB0 K9F2816Q0C-DCB0,DIB0

K9F2808U0C-VCB0,VIB0

AC Timing Characteristics for Command / Address / Data Input

NOTE :

1. If tCS is set less than 10ns, tWP must be minimum 35ns, otherwise, tWP may be minimum 25ns.

Parameter Symbol

K9F2808Q0C K9F2808U0C

Unit

Min Max Min Max

CLE Set-up Time tCLS 0 - 0 - ns
CLE Hold Time tCLH 10 - 10 - ns
CE Setup Time tCS 0 - 0 - ns
CE Hold Time

tCH 10 - 10 - ns

WE Pulse Width tWP 40 -

25

- ns
ALE Setup Time tALS 0 - 0 - ns
ALE Hold Time

tALH 10 - 10 -

ns
Data Setup Time tDS 20 - 20 - ns
Data Hold Time

tDH 10 - 10 - ns
Write Cycle Time tWC 60 - 45 - ns
WE High Hold Time tWH 20 - 15 - ns

AC Characteristics for Operation

NOTE :

1. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5us.

2. To break the sequential read cycle, CE must be held high for longer time than tCEH.

3. The time to Ready depends on the value of the pull-up resistor tied R/B pin.

Parameter Symbol

K9F2808Q0C

K9F2808U0C

Unit

Min Max Min Max

Data Transfer from Cell to Register tR - 10 - 10 µs
ALE to RE Delay tAR 10 - 10 - ns
CLE to RE Delay tCLR 10 - 10 - ns
Ready to RE Low tRR 20 - 20 - ns
RE Pulse Width tRP 40 - 25 - ns
WE High to Busy tWB - 100 - 100

ns
Read Cycle Time tRC 60 - 50 - ns
CE Access Time tCEA - 55 - 45 ns
RE Access Time tREA - 40 - 30 ns
RE High to Output Hi-Z tRHZ

-

30

-

30 ns
CE High to Output Hi-Z tCHZ - 20 - 20 ns
RE or CE High to Output hold tOH 15 - 15 - ns
RE High Hold Time tREH 20 - 15 - ns
Output Hi-Z to RE Low tIR 0 - 0 - ns
WE High to RE Low tWHR 60 - 60 - ns
Device Resetting Time(Read/Program/Erase) tRST -

5/10/500

(1)

-

5/10/500

(1)

µs

K9F2808U0C­Y,P,V,F only

Last RE High to Busy
(at sequential read)

tRB - 100 - 100 ns

CE High to Ready(in case of inter­ception by CE at read)

tCRY

-

50 +tr(R/B)

(3)

-

50 +tr(R/B)

(3)

ns

CE High Hold Time(at the last
serial read)

(2)

tCEH 100 - 100 - ns

K9F2816U0C-YCB0,YIB0

FLASH MEMORY

13

K9F2816U0C-DCB0,DIB0

K9F2808U0C-YCB0,YIB0
K9F2808U0C-DCB0,DIB0

K9F2808Q0C-DCB0,DIB0 K9F2816Q0C-DCB0,DIB0

K9F2808U0C-VCB0,VIB0

NAND Flash Technical Notes

Identifying Invalid Block(s)

Invalid Block(s)

Invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by Samsung. The infor­mation regarding the invalid block(s) is so called as the invalid block information. Devices with invalid block(s) have the same quality
level as devices with all valid blocks and have the same AC and DC characteristics. An invalid block(s) does not affect the perfor­mance of valid block(s) because it is isolated from the bit line and the common source line by a select transistor. The system design
must be able to mask out the invalid block(s) via address mapping. The 1st block, which is placed on 00h block address, is fully guar­anteed to be a valid block, does not require Error Correction.

All device locations are erased(FFh) except locations where the invalid block(s) information is written prior to shipping. The invalid
block(s) status is defined by the 6th byte(X8 device) or 1st & 6th word(X16 device) in the spare area. Samsung makes sure that
either the 1st or 2nd page of every invalid block has non-FFh(X8 device) or non-FFFFh(X16 device) data at the column address of
517(X8 device) or 256 and 261(X16 device). Since the invalid block information is also erasable in most cases, it is impossible to
recover the information once it has been erased. Therefore, the system must be able to recognize the invalid block(s) based on the
original invalid block information and create the invalid block table via the following suggested flow chart(Figure 3). Any intentional
erasure of the original invalid block information is prohibited.

*

Check "FFh" at the column address

Figure 3. Flow chart to create invalid block table.

Start

Set Block Address = 0

Check "FFh" ?

Increment Block Address

Last Block ?

End

No

Yes

Yes

Create (or update)

No

Invalid Block(s) Table

of the 1st and 2nd page in the block

517(X8 device) or 256 and 261(X16 device)

K9F2816U0C-YCB0,YIB0

FLASH MEMORY

14

K9F2816U0C-DCB0,DIB0

K9F2808U0C-YCB0,YIB0
K9F2808U0C-DCB0,DIB0

K9F2808Q0C-DCB0,DIB0 K9F2816Q0C-DCB0,DIB0

K9F2808U0C-VCB0,VIB0

NAND Flash Technical Notes (Continued)

Program Flow Chart

Start

I/O 6 = 1 ?

Write 00h

I/O 0 = 0 ?

No

*

If ECC is used, this verification

Write 80h

Write Address

Write Data

Write 10h

Read Status Register

Write Address

Wait for tR Time

Verify Data

No

Program Completed

or R/B = 1 ?

Program Error

Yes

No

Yes

*

Program Error

Yes

: If program operation results in an error, map out
the block including the page in error and copy the
target data to another block.

*

operation is not needed.

Error in write or read operation

Over its life time, the additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual
data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read fail­ure after erase or program, block replacement should be done. Because program status fail during a page program does not affect
the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased
empty block and reprogramming the current target data and copying the rest of the replaced block. To improve the efficiency of
memory space, it is recommended that the read or verification failure due to single bit error be reclaimed by ECC without any block
replacement. The said additional block failure rate does not include those reclaimed blocks.

Failure Mode Detection and Countermeasure sequence

Write

Erase Failure Status Read after Erase --> Block Replacement

Program Failure

Status Read after Program --> Block Replacement
Read back ( Verify after Program) --> Block Replacement

or ECC Correction

Read Single Bit Failure Verify ECC -> ECC Correction

ECC

: Error Correcting Code --> Hamming Code etc.
Example) 1bit correction & 2bit detection

K9F2816U0C-YCB0,YIB0

FLASH MEMORY

15

K9F2816U0C-DCB0,DIB0

K9F2808U0C-YCB0,YIB0
K9F2808U0C-DCB0,DIB0

K9F2808Q0C-DCB0,DIB0 K9F2816Q0C-DCB0,DIB0

K9F2808U0C-VCB0,VIB0

Erase Flow Chart

Start

I/O 6 = 1 ?

I/O 0 = 0 ?

No

*

Write 60h

Write Block Address

Write D0h

Read Status Register

or R/B = 1 ?

Erase Error

Yes

No

: If erase operation results in an error, map out

the failing block and replace it with another block.

*

Erase Completed

Yes

Read Flow Chart

Start

Verify ECC

No

Write 00h

Write Address

Read Data

ECC Generation

Reclaim the Error

Page Read Completed

Yes

NAND Flash Technical Notes (Continued)

Block Replacement

* Step1
When an error happens in the nth page of the Block ’A’ during erase or program operation.
* Step2
Copy the nth page data of the Block ’A’ in the buffer memory to the nth page of another free block. (Block ’B’)
* Step3
Then, copy the data in the 1st ~ (n-1)th page to the same location of the Block ’B’.
* Step4
Do not further erase Block ’A’ by creating an ’invalid Block’ table or other appropriate scheme.

Buffer memory of the controller.

1st

Block A

Block B

(n-1)th
nth

(page)

1

2

{

∼

1st
(n-1)th

nth
(page)

{

∼

an error occurs.

K9F2816U0C-YCB0,YIB0

FLASH MEMORY

16

K9F2816U0C-DCB0,DIB0

K9F2808U0C-YCB0,YIB0
K9F2808U0C-DCB0,DIB0

K9F2808Q0C-DCB0,DIB0 K9F2816Q0C-DCB0,DIB0

K9F2808U0C-VCB0,VIB0

Samsung NAND Flash has three address pointer commands as a substitute for the two most significant column addresses. ’00h’
command sets the pointer to ’A’ area(0~255byte), ’01h’ command sets the pointer to ’B’ area(256~511byte), and ’50h’ command sets
the pointer to ’C’ area(512~527byte). With these commands, the starting column address can be set to any of a whole
page(0~527byte). ’00h’ or ’50h’ is sustained until another address pointer command is inputted. ’01h’ command, however, is effec­tive only for one operation. After any operation of Read, Program, Erase, Reset, Power_Up is executed once with ’01h’ command,
the address pointer returns to ’A’ area by itself. To program data starting from ’A’ or ’C’ area, ’00h’ or ’50h’ command must be input­ted before ’80h’ command is written. A complete read operation prior to ’80h’ command is not necessary. To program data starting
from ’B’ area, ’01h’ command must be inputted right before ’80h’ command is written.

00h

(1) Command input sequence for programming ’A’ area

Address / Data input

80h 10h 00h 80h 10h

Address / Data input

The address pointer is set to ’A’ area(0~255), and sustained

01h

(2) Command input sequence for programming ’B’ area

Address / Data input

80h 10h 01h 80h 10h

Address / Data input

’B’, ’C’ area can be programmed.
It depends on how many data are inputted.

’01h’ command must be rewritten before
every program operation

The address pointer is set to ’B’ area(256~512), and will be reset to
’A’ area after every program operation is executed.

50h

(3) Command input sequence for programming ’C’ area

Address / Data input

80h 10h

50h 80h 10h

Address / Data input

Only ’C’ area can be programmed. ’50h’ command can be omitted.

The address pointer is set to ’C’ area(512~527), and sustained

’00h’ command can be omitted.

It depends on how many data are inputted.

’A’,’B’,’C’ area can be programmed.

Pointer Operation of K9F2808X0C(X8)

Table 2. Destination of the pointer

Command Pointer position Area

00h
01h
50h

0 ~ 255 byte
256 ~ 511 byte
512 ~ 527 byte

1st half array(A)

2nd half array(B)

spare array(C)

"A" area

256 Byte

(00h plane)

"B" area

(01h plane)

"C" area

(50h plane)

256 Byte

16 Byte

"A" "B" "C"

Internal

Page Register

Pointer select
commnad
(00h, 01h, 50h)

Pointer

Figure 4. Block Diagram of Pointer Operation

K9F2816U0C-YCB0,YIB0

FLASH MEMORY

17

K9F2816U0C-DCB0,DIB0

K9F2808U0C-YCB0,YIB0
K9F2808U0C-DCB0,DIB0

K9F2808Q0C-DCB0,DIB0 K9F2816Q0C-DCB0,DIB0

K9F2808U0C-VCB0,VIB0

Samsung NAND Flash has two address pointer commands as a substitute for the most significant column address. ’00h’ command
sets the pointer to ’A’ area(0~255word), and ’50h’ command sets the pointer to ’B’ area(256~263word). With these commands, the
starting column address can be set to any of a whole page(0~263word). ’00h’ or ’50h’ is sustained until another address pointer com­mand is inputted. To program data starting from ’A’ or ’B’ area, ’00h’ or ’50h’ command must be inputted before ’80h’ command is
written. A complete read operation prior to ’80h’ command is not necessary.

00h

(1) Command input sequence for programming ’A’ area

Address / Data input

80h 10h 00h 80h 10h

Address / Data input

The address pointer is set to ’A’ area(0~255), and sustained

50h

(2) Command input sequence for programming ’B’ area

Address / Data input

80h 10h 50h 80h 10h

Address / Data input

Only ’B’ area can be programmed. ’50h’ command can be omitted.

The address pointer is set to ’B’ area(256~263), and sustained

’00h’ command can be omitted.

It depends on how many data are inputted.

’A’,’B’ area can be programmed.

Pointer Operation of K9F2816X0C(X16)

Table 3. Destination of the pointer

Command Pointer position Area

00h
50h

0 ~ 255 word

256 ~ 263 word

main array(A)

spare array(B)

"A" area

256 Word

(00h plane)

"B" area

(50h plane)

8 Word

"A" "B"

Internal

Page Register

Pointer select
command
(00h, 50h)

Pointer

Figure 5. Block Diagram of Pointer Operation

K9F2816U0C-YCB0,YIB0

FLASH MEMORY

18

K9F2816U0C-DCB0,DIB0

K9F2808U0C-YCB0,YIB0
K9F2808U0C-DCB0,DIB0

K9F2808Q0C-DCB0,DIB0 K9F2816Q0C-DCB0,DIB0

K9F2808U0C-VCB0,VIB0

System Interface Using CE don’t-care.

CE

WE

tWP

tCH

tCS

Start Add.(3Cycle)80h Data Input

CE

CLE

ALE

WE

Data Input

CE don’t-care

≈

≈

10h

For an easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown below. The internal
528byte/264word page registers are utilized as seperate buffers for this operation and the system design gets more flexible. In addi­tion, for voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading
and reading would provide significant savings in power consumption.

Start Add.(3Cycle)00h

CE

CLE

ALE

WE

Data Output(sequential)

CE don’t-care

≈

R/B

tR

RE

tCEA

out

tREA

CE

RE

I/O0~15

Figure 6. Program Operation with CE don’t-care.

Figure 7. Read Operation with CE don’t-care.

On K9F2808U0C_Y,P or K9F2808U0C_V,F

I/Ox

I/Ox

CE must be held
low during tR

K9F2816U0C-YCB0,YIB0

FLASH MEMORY

19

K9F2816U0C-DCB0,DIB0

K9F2808U0C-YCB0,YIB0
K9F2808U0C-DCB0,DIB0

K9F2808Q0C-DCB0,DIB0 K9F2816Q0C-DCB0,DIB0

K9F2808U0C-VCB0,VIB0

CE

WE

CLE

ALE

I/Ox

AO~A7

tCLS

tCS

tWC

tWP

tALS

tDS

tDH

tALH

tALS

tWH

tWC

tWP

tDS

tDH

tALH tALS

tWH

tWP

tDS

tDH

tALH

* Command Latch Cycle

CE

WE

CLE

ALE

I/Ox

Command

* Address Latch Cycle

tCLS

tCS

tCLH

tCH

tWP

tALS tALH

tDS

tDH

A17~A23A9~A16

NOTE: 1. I/O8~15 must be set to "0" during command or address input.

2. I/O8~15 are used only for data bus.

Device

I/O DATA

I/Ox Data In/Out

K9F2808X0C(X8 device) I/O 0 ~ I/O 7 ~528byte
K9F2816X0C(X16 device)

I/O 0 ~ I/O 15

1)

~264word

K9F2816U0C-YCB0,YIB0

FLASH MEMORY

20

K9F2816U0C-DCB0,DIB0

K9F2808U0C-YCB0,YIB0
K9F2808U0C-DCB0,DIB0

K9F2808Q0C-DCB0,DIB0 K9F2816Q0C-DCB0,DIB0

K9F2808U0C-VCB0,VIB0

* Input Data Latch Cycle

CE

CLE

WE

DIN 0

DIN 1

DIN n

ALE

tALS

tCLH

tWC

tCH

tDS

tDH

tDS

tDH

tDS

tDH

tWP

tWH

tWP

tWP

* Serial access Cycle after Read(CLE=L, WE=H, ALE=L)

RE

CE

R/B

Dout

Dout

Dout

tRC

tREA

tRR

tOH

tREA

tREH

tREA

tOH

tRHZ*

≈

≈

≈

≈≈≈≈

NOTES : Transition is measured ±200mV from steady state voltage with load.

This parameter is sampled and not 100% tested.

I/Ox

I/Ox

tRHZ*

tCHZ*

tRP

K9F2816U0C-YCB0,YIB0

FLASH MEMORY

21

K9F2816U0C-DCB0,DIB0

K9F2808U0C-YCB0,YIB0
K9F2808U0C-DCB0,DIB0

K9F2808Q0C-DCB0,DIB0 K9F2816Q0C-DCB0,DIB0

K9F2808U0C-VCB0,VIB0

tOH

* Status Read Cycle

CE

WE

CLE

RE

I/Ox

70h

Status Output

tCLR

tCLH

tCS

tWP

tCH

tDS

tDH tREA

tIR

tOH

tOH

tWHR

tCEA

tCLS

READ1 OPERATION(READ ONE PAGE)

CE

CLE

R/B

WE

ALE

RE

Busy

Read

A0~A7

A9~A16

A17~A23

Dout N

Dout N+1

Dout N+2 Dout N+3

Column
Address

Page(Row)
Address

tWB

tAR

tR

tRC

tRR

Dout m

tWC

≈≈

≈

X8 device : m = 528 , Read CMD = 00h or 01h
X16 device : m = 264 , Read CMD = 00h

tOH

tCHZ

tCEH

tRB

tCRY

N Address

CMD

1)

1)

NOTES : 1) is only valid on K9F2808U0C_Y,P or K9F2808U0C_V,F

I/Ox

On K9F2808U0C_Y,P or K9F2808U0C_V,F
CE must be held
low during tR

tRHZ

tCHZ

tRHZ

K9F2816U0C-YCB0,YIB0

FLASH MEMORY

22

K9F2816U0C-DCB0,DIB0

K9F2808U0C-YCB0,YIB0
K9F2808U0C-DCB0,DIB0

K9F2808Q0C-DCB0,DIB0 K9F2816Q0C-DCB0,DIB0

K9F2808U0C-VCB0,VIB0

READ1 OPERATION (INTERCEPTED BY CE)

CE

CLE

R/B

WE

ALE

RE

Busy

Dout N

Dout N+1

Dout N+2 Dout N+3

Page(Row)
Address

Address

Column

tWB

tAR

tCHZ

tR

tRR

tRC

READ2 OPERATION (READ ONE PAGE)

CE

CLE

R/B

WE

ALE

RE

50h

Dout

Dout n+m

M Address

n+M

Dout

n+M+1

Selected
Row

Start
address M

n

m

tAR

tR

tWB

tRR

X8 device : A0~A3 are Valid Address & A4~A7 are Don′t care

≈

≈

X8 device : n = 512, m = 16
X16 device : n = 256, m = 8

N Address

CMD

Read

I/Ox

I/Ox

Col. Add

Row Add1

Row Add2

Col. Add

Row Add1 Row Add2

On K9F2808U0C_Y,P or K9F2808U0C_V,F
CE must be held
low during tR

On K9F2808U0C_Y,P or K9F2808U0C_V,F
CE must be held
low during tR

X16 device : A0~A2 are Valid Address & A3~A7 are "L"

tOH

K9F2816U0C-YCB0,YIB0

FLASH MEMORY

23

K9F2816U0C-DCB0,DIB0

K9F2808U0C-YCB0,YIB0
K9F2808U0C-DCB0,DIB0

K9F2808Q0C-DCB0,DIB0 K9F2816Q0C-DCB0,DIB0

K9F2808U0C-VCB0,VIB0

PAGE PROGRAM OPERATION

CE

CLE

R/B

WE

ALE

RE

80h 70h I/O0

DinNDin

Din

10h

m

N+1
Sequential Data
Input Command

Column
Address

Page(Row)

Address

1 up to m Data
Serial Input

Program
Command

Read Status
Command

I/O0=0 Successful Program
I/O0=1 Error in Program

tPROG

tWB

tWC

tWC

tWC

≈
≈

≈

X8 device : m = 528 byte
X16 device : m = 264 word

N Address

SEQUENTIAL ROW READ OPERATION (only for K9F2808U0C-Y,P and K9F2808U0C-V,F valid wihin a block)

CE

CLE

R/B

I/Ox

WE

ALE

RE

00h

M

Output

DoutNDout

N+1

Dout
N+2

Dout

527

Dout0Dout1Dout2Dout

527

M+1

Output

N

≈≈

≈

≈

Busy Busy

Ready

≈

≈

I/Ox

Col. Add

Row Add1 Row Add2

Col. Add

Row Add1 Row Add2

K9F2816U0C-YCB0,YIB0

FLASH MEMORY

24

K9F2816U0C-DCB0,DIB0

K9F2808U0C-YCB0,YIB0
K9F2808U0C-DCB0,DIB0

K9F2808Q0C-DCB0,DIB0 K9F2816Q0C-DCB0,DIB0

K9F2808U0C-VCB0,VIB0

BLOCK ERASE OPERATION (ERASE ONE BLOCK)

CE

CLE

R/B

WE

ALE

RE

60h

Auto Block Erase

Erase Command Read Status

Command

I/O0=1 Error in Erase

DOh 70h I/O 0

Busy

tWB

tBERS

I/O0=0 Successful Erase

Page(Row)

Address

tWC

≈

Setup Command

I/Ox

A9~A16

A17~A23

K9F2816U0C-YCB0,YIB0

FLASH MEMORY

25

K9F2816U0C-DCB0,DIB0

K9F2808U0C-YCB0,YIB0
K9F2808U0C-DCB0,DIB0

K9F2808Q0C-DCB0,DIB0 K9F2816Q0C-DCB0,DIB0

K9F2808U0C-VCB0,VIB0

MANUFACTURE & DEVICE ID READ OPERATION

CE

CLE

WE

ALE

RE

90h

Read ID Command Maker Code Device Code

00h

tREA

Address. 1cycle

tAR

I/Ox

ECh

Device

Device Device Code*

K9F2808Q0C 33h
K9F2808U0C 73h
K9F2816Q0C XX43h
K9F2816U0C XX53h

Code*

K9F2816U0C-YCB0,YIB0

FLASH MEMORY

26

K9F2816U0C-DCB0,DIB0

K9F2808U0C-YCB0,YIB0
K9F2808U0C-DCB0,DIB0

K9F2808Q0C-DCB0,DIB0 K9F2816Q0C-DCB0,DIB0

K9F2808U0C-VCB0,VIB0

DEVICE OPERATION

PAGE READ

Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00h to the command reg­ister along with three address cycles. Once the command is latched, it does not need to be written for the following page read opera­tion. Two types of operations are available : random read, serial page read.
The random read mode is enabled when the page address is changed. The 528 bytes(X8 device) or 264 words(X16 device) of data
within the selected page are transferred to the data registers in less than 10µs(tR). The system controller can detect the completion
of this data transfer(tR) by analyzing the output of R/B pin. Once the data in a page is loaded into the registers, they may be read out
in 50ns cycle time by sequentially pulsing RE. High to low transitions of the RE clock output the data starting from the selected col­umn address up to the last column address[column 511/ 527(X8 device) 255 /263(X16 device) depending on the state of GND input
pin].
The way the Read1 and Read2 commands work is like a pointer set to either the main area or the spare area. The spare area of 512
~527 bytes(X8 device) or 256~263 words(X16 device) may be selectively accessed by writing the Read2 command with GND input
pin low. Addresses A0~A3(X8 device) or A0~A2(X16 device) set the starting address of the spare area while addresses A4~A7 are
ignored in X8 device case or A3~A7 must be "L" in X16 device case. The Read1 command is needed to move the pointer back to the
main area. Figures 8, 9 show typical sequence and timings for each read operation.

Sequential Row Read is available only on K9F2808U0C_Y,P or K9F2808U0C_V,F :

After the data of last column address is clocked out, the next page is automatically selected for sequential row read. Waiting 10µs
again allows reading the selected page. The sequential row read operation is terminated by bringing CE high. Unless the operation
is aborted, the page address is automatically incremented for sequential row read as in Read1 operation and spare sixteen bytes of
each page may be sequentially read. The Sequential Read 1 and 2 operation is allowed only within a block and after the last page
of a block is readout, the sequential read operation must be terminated by bringing CE high. When the page address moves onto the
next block, read command and address must be given. Figures 8-1, 9-1 show typical sequence and timings for sequential row read
operation.

Figure 8. Read1 Operation

Start Add.(3Cycle)

00h

X8 device : A0 ~ A7 & A9 ~ A23

Data Output(Sequential)

(00h Command)

Data Field Spare Field

CE

CLE

ALE

R/B

WE

RE

tR

Main array

(01h Command)

Data Field Spare Field

1st half array 2st half array

NOTE: 1) After data access on 2nd half array by 01h command, the start pointer is automatically moved to 1st half
array (00h) at next cycle. 01h command is only available on X8 device(K9F2808X0C).

I/Ox

X16 device : A0 ~ A7 & A9 ~ A23

On K9F2808U0C_Y,P or K9F2808U0C_V ,F
CE must be held
low during tR

1)

K9F2816U0C-YCB0,YIB0

FLASH MEMORY

27

K9F2816U0C-DCB0,DIB0

K9F2808U0C-YCB0,YIB0
K9F2808U0C-DCB0,DIB0

K9F2808Q0C-DCB0,DIB0 K9F2816Q0C-DCB0,DIB0

K9F2808U0C-VCB0,VIB0

Figure 9. Read2 Operation

50h

Data Output(Sequential)

Spare Field

CE

CLE

ALE

R/B

WE

Start Add.(3Cycle)

RE

tR

X8 device : A0 ~ A3 & A9 ~ A23

Main array

Data Field Spare Field

Figure 8-1. Sequential Row Read1 Operation (only for K9F2808U0C-Y,P and K9F2808U0C-V,F valid wihin a block )

00h

01h

A0 ~ A7 & A9 ~ A23

I/Ox

R/B

Start Add.(3Cycle)

Data Output Data Output Data Output

1st 2nd Nth

(528 Byte) (528 Byte)

tR

tR

tR

≈

(GND input=L, 00h Command)

Data Field Spare Field

(GND input=L, 01h Command)

Data Field Spare Field

(GND input=H, 00h Command)

Data Field Spare Field

1st half array 2nd half array

1st
2nd
Nth

1st half array 2nd half array

1st
2nd
Nth

Block

1st half array 2nd half array

1st
2nd
Nth

X16 device : A0 ~ A2 & A9 ~ A23

X8 device : A4 ~ A7 Don’t care

X16 device : A3 ~ A7 are "L"

I/Ox

On K9F2808U0C_Y,P or K9F2808U0C_V ,F
CE must be held
low during tR

K9F2816U0C-YCB0,YIB0

FLASH MEMORY

28

K9F2816U0C-DCB0,DIB0

K9F2808U0C-YCB0,YIB0
K9F2808U0C-DCB0,DIB0

K9F2808Q0C-DCB0,DIB0 K9F2816Q0C-DCB0,DIB0

K9F2808U0C-VCB0,VIB0

Figure 9-1. Sequential Row Read2 Operation (GND Input=Fixed Low)

50h

A0 ~ A3 & A9 ~ A23

I/Ox

R/B

Start Add.(3Cycle)

Data Output

Data Output

Data Output

2nd Nth

(16Byte) (16Byte)

Data Field Spare Field

1st
Block

(A4 ~ A7 :
Don′t Care)

1st

tR

tR

tR

≈

Nth

(only for K9F2808U0C-Y,P and K9F2808U0C-V,F valid wihin a block)

K9F2816U0C-YCB0,YIB0

FLASH MEMORY

29

K9F2816U0C-DCB0,DIB0

K9F2808U0C-YCB0,YIB0
K9F2808U0C-DCB0,DIB0

K9F2808Q0C-DCB0,DIB0 K9F2816Q0C-DCB0,DIB0

K9F2808U0C-VCB0,VIB0

PAGE PROGRAM

The device is programmed basically on a page basis, but it does allow multiple partial page programing of a byte/word or consecutive
bytes/words up to 528(X8 device) or 264(X16 device), in a single page program cycle. The number of consecutive partial page program­ming operation within the same page without an intervening erase operation should not exceed 2 for main array and 3 for spare
array. The addressing may be done in any random order in a block. A page program cycle consists of a serial data loading period in
which up to 528 bytes(X8 device) or 264 words(X16 device) of data may be loaded into the page register, followed by a non-volatile pro­gramming period where the loaded data is programmed into the appropriate cell. About the pointer operation, please refer to the
attached technical notes.
The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the three cycle address input and
then serial data loading. The words other than those to be programmed do not need to be loaded.The Page Program confirm com­mand(10h) initiates the programming process. Writing 10h alone without previously entering the serial data will not initiate the pro­gramming process. The internal write controller automatically executes the algorithms and timings necessary for program and verify,
thereby freeing the system controller for other tasks. Once the program process starts, the Read Status Register command may be
entered, with RE and CE low, to read the status register. The system controller can detect the completion of a program cycle by
monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset command are
valid while programming is in progress. When the Page Program is complete, the Write Status Bit(I/O 0) may be checked(Figure 10).
The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains in
Read Status command mode until another valid command is written to the command register.

Figure 10. Program Operation

80h

R/B

Address & Data Input I/O0

Pass

10h 70h

Fail

tPROG

I/Ox

K9F2816U0C-YCB0,YIB0

FLASH MEMORY

30

K9F2816U0C-DCB0,DIB0

K9F2808U0C-YCB0,YIB0
K9F2808U0C-DCB0,DIB0

K9F2808Q0C-DCB0,DIB0 K9F2816Q0C-DCB0,DIB0

K9F2808U0C-VCB0,VIB0

Figure 11. Block Erase Operation

BLOCK ERASE

The Erase operation is done on a block basis. Block address loading is accomplished in two cycles initiated by an Erase Setup com­mand(60h). Only address A14 to A23 is valid while A9 to A13 is ignored. The Erase Confirm command(D0h) following the block address
loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that memory
contents are not accidentally erased due to external noise conditions.
At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-verify. When
the erase operation is completed, the Write Status Bit(I/O 0) may be checked. Figure 11 details the sequence.

60h

Block Add. : A9 ~ A23

R/B

Address Input(2Cycle)

I/O0

Pass

D0h

70h

Fail

tBERS

READ STATUS

The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether
the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs
the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows
the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE
does not need to be toggled for updated status. Refer to table 4 for specific Status Register definitions. The command register
remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read
cycle, a read command(00h or 50h) should be given before sequential page read cycle.

Table4. Read Status Register Definition

I/O # Status Definition

I/O 0 Program / Erase

"0" : Successful Program / Erase
"1" : Error in Program / Erase

I/O 1

Reserved for Future

Use

"0"
I/O 2 "0"
I/O 3 "0"
I/O 4 "0"
I/O 5 "0"
I/O 6 Device Operation "0" : Busy "1" : Ready
I/O 7 Write Protect "0" : Protected "1" : Not Protected

I/O 8~15 Not use Don’t care

I/Ox

K9F2816U0C-YCB0,YIB0

FLASH MEMORY

31

K9F2816U0C-DCB0,DIB0

K9F2808U0C-YCB0,YIB0
K9F2808U0C-DCB0,DIB0

K9F2808Q0C-DCB0,DIB0 K9F2816Q0C-DCB0,DIB0

K9F2808U0C-VCB0,VIB0

Figure 12. Read ID Operation

CE

CLE

ALE

RE

WE

90h

00h

Address. 1cycle Maker code Device code

tCEA

tAR

tREA

READ ID

The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of
00h. Two read cycles sequentially output the manufacture code(ECh), and the device code respectively. The command register
remains in Read ID mode until further commands are issued to it. Figure 12 shows the operation sequence.

tWHR

Figure 13. RESET Operation

RESET

The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random
read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no
longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and
the Status Register is cleared to value C0h when WP is high. Refer to table 5 for device status after reset operation. If the device is
already in reset state a new reset command will not be accepted by the command register. The R/B pin transitions to low for tRST
after the Reset command is written. Refer to Figure 13 below.

After Power-up After Reset

Operation Mode Read 1 Waiting for next command

FFh

R/B

Table5. Device Status

tRST

ECh

Device

I/Ox

I/Ox

Device Device Code*
K9F2808Q0C 33h
K9F2808U0C 73h
K9F2816Q0C 43h
K9F2816U0C 53h

Code*

K9F2816U0C-YCB0,YIB0

FLASH MEMORY

32

K9F2816U0C-DCB0,DIB0

K9F2808U0C-YCB0,YIB0
K9F2808U0C-DCB0,DIB0

K9F2808Q0C-DCB0,DIB0 K9F2816Q0C-DCB0,DIB0

K9F2808U0C-VCB0,VIB0

READY/BUSY

The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random
read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command reg­ister or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin
is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. Because pull-up resistor value is related to tr(R/B)
and current drain during busy(ibusy) , an appropriate value can be obtained with the following reference chart(Fig 14). Its value can
be determined by the following guidance.

VCC

R/B

open drain output

Device

GND

Rp

tr,tf [s]

Ibusy [A]

Rp(ohm)

Fig 14 Rp vs tr ,tf & Rp vs ibusy

Ibusy

tr

ibusy

Busy

Ready Vcc

@ Vcc = 3.3V, Ta = 25

°

C , CL = 100pF

VOH

tf

tr

1K 2K 3K

4K

100n

200n

300n 3m

2m

1m

100

tf

200

300

400

3.6

3.6

3.6

3.6

2.4

1.2

0.8

0.6

VOL

Rp(min, 1.8V part) =

VCC(Max.) - VOL(Max.)

IOL + ΣIL

=

1.85V

3mA + ΣIL

where IL is the sum of the input currents of all devices tied to the R/B pin.

Rp value guidance

Rp(max) is determined by maximum permissible limit of tr

Rp(min, 3.3V part) =

VCC(Max.) - VOL(Max.)

IOL + ΣIL

=

3.2V

8mA + ΣIL

1.8V device - VOL : 0.1V, VOH : VCCq-0.1V

3.3V device - VOL : 0.4V, VOH : 2.4V

tr,tf [s]

Ibusy [A]

Rp(ohm)

Ibusy

tr

@ Vcc = 1.8V, Ta = 25

°

C , CL = 30pF

1K 2K 3K

4K

100n

200n

300n 3m

2m

1m

30

tf

60

90

120

1.7

1.7

1.7

1.7

1.7

0.85

0.57

0.43

CL

K9F2816U0C-YCB0,YIB0

FLASH MEMORY

33

K9F2816U0C-DCB0,DIB0

K9F2808U0C-YCB0,YIB0
K9F2808U0C-DCB0,DIB0

K9F2808Q0C-DCB0,DIB0 K9F2816Q0C-DCB0,DIB0

K9F2808U0C-VCB0,VIB0

The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector
disables all functions whenever Vcc is below about 1.1V(1.8V device) or 2V(3.3V device). WP pin provides hardware protection and
is recommended to be kept at VIL during power-up and power-down and recovery time of minimum 10µs is required before internal
circuit gets ready for any command sequences as shown in Figure 15. The two step command sequence for program/erase provides
additional software protection.

Figure 15. AC Waveforms for Power Transition

VCC

WP

High

≈

≈

1.8V device : ~ 1.5V

WE

Data Protection & Power up sequence

3.3V device : ~ 2.5V

1.8V device : ~ 1.5V

3.3V device : ~ 2.5V

10µs

≈≈