Datasheet K6X1008C2D55 Specification

Document Title

128Kx8 bit Low Power CMOS Static RAM

Revision History

CMOS SRAMK6X1008C2D Family

Revision No.

0.0

0.1

0.2

0.3

1.0

History

Initial draft

Revised

- Deleted 32-TSOP1-0820R Package Type.

- Added Commercial product.

Revised

- Added Lead Free 32-SOP-525 Product

Revised

- Added Lead Free 32-TSOP1-0820F Product

Finalized

- Changed ICC from 10mA to 5mA

- Changed ICC2 from 35mA to 25mA

- Changed ISB from 3mA to 0.4mA

- Changed IDR(industrial) from 15µA to 10µA

- Changed IDR(Automotive) from 25µA to 20µA

Draft Data

July 15, 2002

December 4, 2002

May 13, 2003

June 21, 2003

September 16, 2003

Remark

Preliminary

Preliminary

Preliminary

Preliminary

Final

The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserves the right to change the specifications and

products. SAMSUNG Electronics will answer to your questions. If you have any questions, please contact the SAMSUNG branch offices.

1

Revision 1.0

September 2003

128Kx8 bit Low Power full CMOS Static RAM

CMOS SRAMK6X1008C2D Family

FEATURES

• Process Technology: Full CMOS

• Organization: 128K x 8

• Power Supply Voltage: 4.5~5.5V

• Low Data Retention Voltage: 2V(Min)

• Three state output and TTL Compatible

• Package Type: 32-DIP-600, 32-SOP-525,

32-SOP-525, 32-TSOP1-0820F

GENERAL DESCRIPTION

The K6X1008C2D families are fabricated by SAMSUNG′s
advanced CMOS process technology. The families support
verious operating temperature ranges and have various pack­age types for user flexibility of system design. The families
also support low data retention voltage for battery back-up
operation with low data retention current.

PRODUCT FAMILY

Product Family

Operating

Temperature

Vcc Range Speed

K6X1008C2D-B Commercial(0~70°C)
K6X1008C2D-F Industrial(-40~85°C) 15µA

4.5~5.5V

551)/70ns

K6X1008C2D-Q Automotive(-40~125°C) 25µA 32-SOP-525, 32-TSOP1-0820F

1. The parameters are tested with 50pF test load

PIN DESCRIPTION

VCC
A16
A14
A12

I/O1
I/O2
I/O3

VSS

1

NC

2
3
4
5

A7

6

A6

32-SOP

7

A5

32-DIP

A4

8
9

A3

10

A2
A1

11
12

A0

13
14
15
16

32

A15

31

CS2

30
29
28
27
26
25
24
23
22
21
20
19
18
17

WE

A13

A8

A9

A11

OE

A10

CS1

I/O8

I/O7

I/O6

I/O5

I/O4

A11

A13

WE
CS2
A15

VCC

A16
A14
A12

1

A9

2

A8

3
4
5
6
7
8

NC

9
10
11
12

A7

13

A6

14

A5

15

A4

16

32-TSOP

Type1-Forward

32

OE

31

A10

30

CS1

29

I/O8

28

I/O7

27

I/O6

26

I/O5

25

I/O4

24

VSS

23

I/O3

22

I/O2

21

I/O1

20

A0

19

A1

18

A2

17

A3

Power Dissipation

Standby

(ISB1, Max)

10µA

Operating
(ICC2, Max)

PKG Type

32-DIP-600, 32-SOP-525,

32-SOP-525

25mA

32-TSOP1-0820F

FUNCTIONAL BLOCK DIAGRAM

Row
addresses

I/O1
I/O8

Clk gen.

Row
select

Data
cont

Data
cont

Precharge circuit.

Memory array

I/O Circuit

Column select

Column Addresses

Name Function

CS1, CS2 Chip Select Input

OE Output Enable Input
WE Write Enable Input

I/O1~I/O8 Data Inputs/Outputs

CS1
CS2
WE

Control
logic

OE

A0~A16 Address Inputs

Vcc Power
Vss Ground

NC No Connection

SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.

2

Revision 1.0

September 2003

CMOS SRAMK6X1008C2D Family

PRODUCT LIST

Commercial Products(0~70°C) Industrial Products(-40~85°C) Automotive Products(-40~125°C)

Part Name Function Part Name Function Part Name Function

K6X1008C2D-DB55
K6X1008C2D-DB70
K6X1008C2D-GB55
K6X1008C2D-GB70
K6X1008C2D-BB55
K6X1008C2D-BB70
K6X1008C2D-TB55
K6X1008C2D-TB70
K6X1008C2D-PB55
K6X1008C2D-PB70

1. Lead Free Product

FUNCTIONAL DESCRIPTION

CS1 CS2 OE WE I/O Mode Power

H

1)

X

L H H H High-Z Output Disabled Active
L H L H Dout Read Active
L H

1. X means don′t care (Must be in high or low states)

32-DIP, 55ns, LL
32-DIP, 70ns, LL
32-SOP, 55ns, LL
32-SOP, 70ns, LL

1)

32-SOP, 55ns, LL

1)

32-SOP, 70ns, LL
32-TSOP-F, 55ns, LL
32-TSOP-F, 70ns, LL

1)

32-TSOP-F, 55ns, LL

1)

32-TSOP-F, 70ns, LL

1)

X

L

K6X1008C2D-DF55
K6X1008C2D-DF70
K6X1008C2D-GF55
K6X1008C2D-GF70
K6X1008C2D-BF55
K6X1008C2D-BF70
K6X1008C2D-TF55
K6X1008C2D-TF70
K6X1008C2D-PF55
K6X1008C2D-PF70

1)

X

1)

X

1)

X

1)

X

1)

X

L Din Write Active

32-DIP, 55ns, LL
32-DIP, 70ns, LL
32-SOP, 55ns, LL
32-SOP, 70ns, LL

1)

32-SOP, 55ns, LL

1)

32-SOP, 70ns, LL
32-TSOP-F, 55ns, LL
32-TSOP-F, 70ns, LL

1)

32-TSOP-F, 55ns, LL

1)

32-TSOP-F, 70ns, LL

K6X1008C2D-GQ55
K6X1008C2D-GQ70
K6X1008C2D-TQ55
K6X1008C2D-TQ70

32-SOP, 55ns, L
32-SOP, 70ns, L
32-TSOP-F, 55ns, L
32-TSOP-F, 70ns, L

High-Z Deselected Standby
High-Z Deselected Standby

ABSOLUTE MAXIMUM RATINGS

1)

Item Symbol Ratings Unit Remark

Voltage on any pin relative to Vss VIN,VOUT -0.5 to VCC+0.5V(Max. 7.0V) V ­Voltage on Vcc supply relative to Vss VCC -0.3 to 7.0 V ­Power Dissipation PD 1.0 W ­Storage temperature TSTG -65 to 150 °C -

0 to 70 °C K6X1008C2D-B

Operating Temperature TA

-40 to 85 °C K6X1008C2D-F

-40 to 125 °C K6X1008C2D-Q

1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

3

Revision 1.0

September 2003

CMOS SRAMK6X1008C2D Family

RECOMMENDED DC OPERATING CONDITIONS

1)

Item Symbol Min Typ Max Unit

Supply voltage Vcc 4.5 5.0 5.5 V
Ground Vss 0 0 0 V
Input high voltage VIH 2.2 ­Input low voltage VIL

Note:

1. Commercial Product: TA=0 to 70°C, Otherwise specified
Industrial Product: TA=-40 to 85°C, Otherwise specified
Automotive Product: TA=-40 to 125°C, Otherwise specified

2. Overshoot: Vcc+3.0V in case of pulse width≤30ns.

3. Undershoot: -3.0V in case of pulse width≤30ns.

4. Overshoot and undershoot are sampled, not 100% tested.

1

CAPACITANCE

)

(f=1MHz, TA=25°C)

-0.5

3)

- 0.8 V

Vcc+0.5

2)

V

Item Symbol Test Condition Min Max Unit

Input capacitance CIN VIN=0V - 8 pF
Input/Output capacitance CIO VIO=0V - 10 pF

1. Capacitance is sampled, not 100% tested

DC AND OPERATING CHARACTERISTICS

Item Symbol Test Conditions Min Typ Max Unit

Input leakage current ILI VIN=Vss to Vcc -1 - 1 µA
Output leakage current ILO CS1=VIH or CS2=VIL or OE=VIH or WE=VIL, VIO=Vss to Vcc -1 - 1 µA
Operating power supply current ICC IIO=0mA, CS1=VIL, CS2=VIH, VIN=VIH or VIL, Read - - 5 mA

Cycle time=1µs, 100%duty, IIO=0mA, CS1≤0.2V, CS2≥Vcc-0.2V,

ICC1

Average operating current

VIN≤0.2V or VIN≥VCC-0.2V
Cycle time=Min, 100% duty, IIO=0mA, CS1=VIL, CS2=VIH,

ICC2

VIN=VIH or VIL

Output low voltage VOL IOL=2.1mA - - 0.4 V
Output high voltage VOH IOH=-1.0mA 2.4 - - V
Standby Current(TTL) ISB CS1=VIH, CS2=VIL, Other inputs=VIH or VIL - - 0.4 mA

K6X1008C2D-B - - 10 µA
K6X1008C2D-F - - 15 µA

Standby Current(CMOS) ISB1

CS1≥Vcc-0.2V, CS2≥Vcc-0.2V or
CS2≤0.2V, Other inputs=0~Vcc

K6X1008C2D-Q - - 25 µA

- - 7 mA

- - 25 mA

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Revision 1.0

September 2003

CMOS SRAMK6X1008C2D Family

AC OPERATING CONDITIONS

TEST CONDITIONS( Test Load and Input/Output Reference)

Input pulse level: 0.8 to 2.4V
Input rising and falling time: 5ns
Input and output reference voltage:1.5V
Output load(see right): CL=100pF+1TTL

CL=50pF+1TTL

AC CHARACTERISTICS

(VCC=4.5~5.5V, Commercial product: TA=0 to 70°C, Industrial product: TA=-40 to 85°C, Automotive product: TA=-40~125°C)

Parameter List Symbol

Read Cycle Time tRC 55 - 70 - ns
Address Access Time tAA - 55 - 70 ns
Chip Select to Output tCO - 55 - 70 ns
Output Enable to Valid Output tOE - 25 - 35 ns

Read

Write

Chip Select to Low-Z Output tLZ 10 - 10 - ns
Output Enable to Low-Z Output tOLZ 5 - 5 - ns
Chip Disable to High-Z Output tHZ 0 20 0 25 ns
Output Disable to High-Z Output tOHZ 0 20 0 25 ns
Output Hold from Address Change tOH 10 - 10 - ns
Write Cycle Time tWC 55 - 70 - ns
Chip Select to End of Write tCW 45 - 60 - ns
Address Set-up Time tAS 0 - 0 - ns
Address Valid to End of Write tAW 45 - 60 - ns
Write Pulse Width tWP 40 - 50 - ns
Write Recovery Time tWR 0 - 0 - ns
Write to Output High-Z tWHZ 0 20 0 25 ns
Data to Write Time Overlap tDW 20 - 25 - ns
Data Hold from Write Time tDH 0 - 0 - ns
End Write to Output Low-Z tOW 5 - 5 - ns

1)

CL

1. Including scope and jig capacitance

Speed Bins

55ns 70ns

Min Max Min Max

Units

DATA RETENTION CHARACTERISTICS

Item Symbol Test Condition Min Typ Max Unit

Vcc for data retention VDR

Data retention current IDR

Data retention set-up time tSDR
Recovery time tRDR 5 - -

1. CS1≥Vcc-0.2V, CS2≥VCC-0.2V, or CS2≤0.2V

CS1≥Vcc-0.2V

Vcc=3.0V, CS1≥Vcc-0.2V

See data retention waveform

1)

K6X1008C2D-B - - 10 µA

1)

K6X1008C2D-F - - 10 µA

K6X1008C2D-Q - - 20 µA

2.0 - 5.5 V

0 - -

5

September 2003

ms

Revision 1.0

TIMING DIAGRAMS

TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1=OE=VIL, CS2=WE=VIH)

tRC

Address

tOH

Data Out

Previous Data Valid

TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)

Address

CS1

tAA

tRC

tAA

tCO1

CMOS SRAMK6X1008C2D Family

Data Valid

tOH

tHZ(1,2)

CS2

OE

Data out

NOTES (READ CYCLE)

1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage

levels.

2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device

interconnection.

High-Z

tLZ

tOLZ

tCO2

tOE

tOHZ

Data Valid

6

Revision 1.0

September 2003

TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)

Address

CS1

tAW

CS2

tWC

tCW(2)

tCW(2)

CMOS SRAMK6X1008C2D Family

tWR(4)

WE

tAS(3)

Data in

tWHZ

Data out

Data Undefined

TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 Controlled)

Address

tAS(3)

CS1

CS2

WE

Data in

tWC

tCW(2)

tAW

tWP(1)

tWP(1)

tDW

Data Valid

tDW

Data Valid

tDH

tOW

tWR(4)

tDH

Data out

High-Z

High-Z

7

Revision 1.0

September 2003

TIMING WAVEFORM OF WRITE CYCLE(3) (CS2 Controlled)

Address

CMOS SRAMK6X1008C2D Family

tWC

tAS(3)

CS1

CS2

WE

Data in

Data out

NOTES (WRITE CYCLE)

1. A write occurs during the overlap of a low CS1, a high CS2 and a low WE. A write begins at the latest transition among CS1 goes low,
CS2 going high and WE going low: A write end at the earliest transition among CS1 going high, CS2 going low and WE going high,
tWP is measured from the begining of write to the end of write.

2. tCW is measured from the CS1 going low or CS2 going high to the end of write.

3. tAS is measured from the address valid to the beginning of write.

4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS1 or WE going high tWR2 applied
in case a write ends as CS2 going to low.

High-Z

tAW

tCW(2)

tCW(2)

tWP(1)

tDW

Data Valid

tWR(4)

tDH

High-Z

DATA RETENTION WAVE FORM

CS1 controlled

VCC

4.5V

tSDR

Data Retention Mode

tRDR

2.2V

VDR

CS1
GND

CS2 controlled

VCC

4.5V

CS2

VDR

0.4V

GND

tSDR

CS≥VCC - 0.2V

Data Retention Mode

CS2≤0.2V

8

tRDR

Revision 1.0

September 2003

CMOS SRAMK6X1008C2D Family

PACKAGE DIMENSIONS

32 DUAL INLINE PACKAGE (600mil)

#32

13.60±0.20

0.535±0.008

#1

1.91

( )

0.075

42.31

1.666

41.91±0.20

1.650±0.008

0.46±0.10

0.018±0.004

1.52±0.10

0.060±0.004

MAX

2.54

0.100

#17

#16

15.24

0.600

3.81±0.20

0.150±0.008

0.200

0.38

MIN

0.015

Units: millimeters(inches)

0.25

0.010

0~15°

5.08

MAX

3.30±0.30

0.130±0.012

+0.10

-0.05
+0.004

-0.002

32 PLASTIC SMALL OUTLINE PACKAGE (525mil)

#32

0.71

( )

0.028

#1

0.41

0.016

20.87

0.822

20.47±0.20

0.806±0.008

+0.100

-0.050
+0.004

-0.002

MAX

1.27

0.050

#17

#16

14.12±0.30

0.556±0.012

2.74±0.20

0.108±0.008

0.05

MIN

0.002

3.00

0.118

MAX

11.43±0.20

0.450±0.008

0.10 MAX

0.004 MAX

0.20

0.008

+0.10

-0.05
+0.004

-0.002

0~8°

13.34

0.525

0.80±0.20

0.031±0.008

9

Revision 1.0

September 2003

CMOS SRAMK6X1008C2D Family

PACKAGE DIMENSIONS

32 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0820F)

0.50

0.0197

0~8°

+0.10

0.20

-0.05
+0.004

0.008

-0.002

#16

0.25

TYP

0.010

0.45 ~0.75

0.018 ~0.030

#1

20.00±0.20

0.787±0.008

18.40±0.10

0.724±0.004

#32

#17

( )

0.020

Units: millimeters(inches)

8.40

MAX

1.00±0.10

0.039±0.004

1.20

MAX

0.047
+0.10

-0.05
+0.004

-0.002

8.00

0.315

0.331

0.15

0.006

0.50

0.10 MAX

0.05

0.002

0.004 MAX

0.25

( )

0.010

MIN

10

Revision 1.0

September 2003