Datasheet K6T4008C1C-GL70, K6T4008C1C-GL55, K6T4008C1C-GF70, K6T4008C1C-GF55, K6T4008C1C-GB70 Datasheet (Samsung)

K6T4008C1C Family

Document Title

512Kx8 bit Low Power CMOS Static RAM

Revision History

CMOS SRAM

Revision No.

0.0

1.0

History

Initial draft

Finalize

Draft Date

October 20,1998

April 12, 1999

Remark

Preliminary

Final

The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.

1

Revision 1.0

April 1999

K6T4008C1C Family

512Kx8 bit Low Power CMOS Static RAM

CMOS SRAM

FEATURES

• Process Technology: TFT

• Organization: 512Kx8

• Power Supply Voltage: 4.5~5.5V

• Low Data Retention Voltage: 2V(Min)

• Three state output and TTL Compatible

• Package Type: 32-DIP-600, 32-SOP-525,

32-TSOP2-400F/R

GENERAL DESCRIPTION

The K6T4008C1C families are fabricated by SAMSUNG′s
advanced CMOS process technology. The families support
various operating temperature ranges and various package
types for user flexibility of system design. The family also
support low data retention voltage for battery back-up oper­ation with low data retention current.

PRODUCT FAMILY

Power Dissipation

Product Family Operating Temperature Vcc Range Speed

K6T4008C1C-L
K6T4008C1C-B 20µA
K6T4008C1C-P

Commercial (0~70°C)

Inderstrial (-40~85°C)

4.5~5.5V

551)/70ns

K6T4008C1C-F 30µA

1. The parameter is measured with 50pF test load.

PIN DESCRIPTION

A18
A16
A14
A12

I/O1
I/O2
I/O3
VSS

A7
A6
A5
A4
A3
A2
A1
A0

1

2

3

4

5

6

32-DIP

7

32-SOP

8

32-TSOP2

9

(Forward)

10

11

12

13

14

15

16

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

VCC
A15
A17
WE
A13
A8
A9
A11
OE
A10
CS
I/O8
I/O7
I/O6
I/O5
I/O4

VCC

A15
A17

WE

A13

A11

OE

A10

CS
I/O8
I/O7
I/O6
I/O5
I/O4

32

31

30

29

28

A8

27

A9

26

32-TSOP2

25

(Reverse)

24

23

22

21

20

19

18

17

1

A18
A16

2

A14

3

A12

4

5

6

7

8

9

10

11

12

13

14

15

VSS

16

FUNCTIONAL BLOCK DIAGRAM

A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3

Standby

(ISB1, Max)

80µA

100µA

I/O1 Data
I/O8

Clk gen.

(ICC2, Max)

Row
select

cont

Data
cont

Operating

55mA

PKG Type

32-DIP,32-SOP
32-TSOP2-F/R

32-SOP
32-TSOP2-F/R

Precharge circuit.

Memory array
1024 rows
512×8 columns

I/O Circuit

Column select

Pin Name Function

WE Write Enable Input

CS Chip Select Input

OE Output Enable Input

A0~A18 Address Inputs

CS

WE

OE

Control
logic

I/O1~I/O8 Data Inputs/Outputs

Vcc Power
Vss Ground

SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.

2

Revision 1.0

April 1999

K6T4008C1C Family

PRODUCT LIST

Commercial Temperature Products(0~70°C) Industrial Temperature Products(-40~85°C)

Part Name Function Part Name Function

K6T4008C1C-DL55
K6T4008C1C-DB55
K6T4008C1C-DL70
K6T4008C1C-DB70

32-DIP, 55ns, Low Power
32-DIP, 55ns, Low Low Power
32-DIP, 70ns, Low Power
32-DIP, 70ns, Low Low Power

K6T4008C1C-GP55
K6T4008C1C-GF55
K6T4008C1C-GP70
K6T4008C1C-GF70

32-SOP, 55ns, Low Power
32-SOP, 55ns, Low Low Power
32-SOP, 70ns, Low Power
32-SOP, 70ns, Low Low Power

CMOS SRAM

K6T4008C1C-GL55
K6T4008C1C-GB55
K6T4008C1C-GL70
K6T4008C1C-GB70

K6T4008C1C-VB55
K6T4008C1C-VB70
K6T4008C1C-MB55
K6T4008C1C-MB70

32-SOP, 55ns, Low Power
32-SOP, 55ns, Low Low Power
32-SOP, 70ns, Low Power
32-SOP, 70ns, Low Low Power

32-TSOP2-F, 55ns, Low Low Power
32-TSOP2-F, 70ns, Low Low Power
32-TSOP2-R, 55ns, Low Low Power
32-TSOP2-R, 70ns, Low Low Power

K6T4008C1C-VF55
K6T4008C1C-VF70
K6T4008C1C-MF55
K6T4008C1C-MF70

32-TSOP2-F, 55ns, Low Low Power
32-TSOP2-F, 70ns, Low Low Power
32-TSOP2-R, 55ns, Low Low Power
32-TSOP2-R, 70ns, Low Low Power

FUNCTIONAL DESCRIPTION

CS OE WE I/O Pin Mode Power

H
L H H High-Z Output disbaled Active
L L H Dout Read Active
L

1. X means don′t care.( Must be in low or high state.)

1)

X

1)

X

ABSOLUTE MAXIMUM RATINGS

Item Symbol Ratings Unit Remark

Voltage on any pin relative to Vss VIN,VOUT -0.5 to 7.0 V ­Voltage on Vcc supply relative to Vss VCC -0.5 to 7.0 V ­Power Dissipation PD 1.0 W ­Storage temperature TSTG -65 to 150 °C -

Operating Temperature TA

1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

1)

X

L Din Write Active

1)

High-Z Deselected Standby

0 to 70 °C K6T4008C1C-L/-B

-40 to 85 °C K6T4008C1C-P/-F

3

Revision 1.0

April 1999

K6T4008C1C Family

CMOS SRAM

-0.5

1)

2)

Vcc+0.5

3)

- 0.8 V

V

RECOMMENDED DC OPERATING CONDITIONS

Item Symbol Min Typ Max Unit

Supply voltage Vcc 4.5 5.0 5.5 V
Ground Vss 0 0 0 V
Input high voltage VIH 2.2 ­Input low voltage VIL

Note:

1. Commercial Product : TA=0 to 70°C, otherwise specified

Industrial Product : TA=-40 to 85°C, otherwise specified

2. Overshoot : VCC+3.0V in case of pulse width ≤ 30ns

3. Undershoot : -3.0V in case of pulse width ≤ 30ns

4. Overshoot and undershoot are sampled, not 100% tested.

CAPACITANCE

Input capacitance CIN VIN=0V - 8 pF
Input/Output capacitance CIO VIO=0V - 10 pF

1. Capacitance is sampled, not 100% tested

1)

(f=1MHz, TA=25°C)

Item Symbol Test Condition Min Max Unit

DC AND OPERATING CHARACTERISTICS

Item Symbol Test Conditions Min Typ Max Unit

Input leakage current ILI VIN=Vss to Vcc -1 - 1 µA
Output leakage current ILO CS=VIH or OE=VIH or WE=VIL, VIO=Vss to Vcc -1 - 1 µA
Operating power supply current ICC IIO=0mA, CS=VIL, VIN=VIL or VIH, Read - - 10 mA

Cycle time=1µs, 100% duty, IIO=0mA

ICC1

Average operating current

Output low voltage VOL IOL=2.1mA - - 0.4 V
Output high voltage VOH IOH=-1.0mA 2.4 - - V
Standby Current(TTL) ISB CS=VIH, Other inputs = VIL or VIH - - 3 mA

Standby Current(CMOS) ISB1 CS≥Vcc-0.2V, Other inputs=0~Vcc

CS≤0.2V, VIN≥0.2V or VIN≥Vcc-0.2V

Cycle time=Min, 100% duty, IIO=0mA, CS=VIL, VIN=VIH or VIL

ICC2

K6T4008C1C-L - - 80
K6T4008C1C-B - - 20
K6T4008C1C-P - - 100
K6T4008C1C-F - - 30

- - 8 mA

- - 55 mA

µA

4

Revision 1.0

April 1999

K6T4008C1C Family

CMOS SRAM

AC OPERATING CONDITIONS

TEST CONDITIONS (Test Load and Test Input/Output Reference)

Input pulse level : 0.8 to 2.4V
Input rising and falling time : 5ns
Input and output reference voltage : 1.5V
Output load (See right) :CL=100pF+1TTL

CL=50pF+1TTL

1)

CL

1. Including scope and jig capacitance

AC CHARACTERISTICS (Vcc=4.5~5.5V, K6T4008C1C-C Family:TA=0 to 70°C, K6T4008C1C-I Family:TA=-40 to 85°C)

Speed Bins

Read

Write

Parameter List Symbol

Read cycle time tRC 55 - 70 - ns
Address access time tAA - 55 - 70 ns
Chip select to output tCO - 55 - 70 ns
Output enable to valid output tOE - 25 - 35 ns
Chip select to low-Z output tLZ 10 - 10 - ns
Output enable to low-Z output tOLZ 5 - 5 - ns
Chip disable to high-Z output tHZ 0 20 0 25 ns
Output disable to high-Z output tOHZ 0 20 0 25 ns
Output hold from address change tOH 10 - 10 - ns
Write cycle time tWC 55 - 70 - ns
Chip select to end of write tCW 45 - 60 - ns
Address set-up time tAS 0 - 0 - ns
Address valid to end of write tAW 45 - 60 - ns
Write pulse width tWP 40 - 50 - ns
Write recovery time tWR 0 - 0 - ns
Write to output high-Z tWHZ 0 20 0 25 ns
Data to write time overlap tDW 25 - 30 - ns
Data hold from write time tDH 0 - 0 - ns
End write to output low-Z tOW 5 - 5 - ns

55ns 70ns

Min Max Min Max

Units

DATA RETENTION CHARACTERISTICS

Item Symbol Test Condition Min Typ Max Unit

Vcc for data retention VDR CS≥Vcc-0.2V 2.0 - 5.5 V

K6T4008C1C-L - - 40

Data retention current IDR Vcc=3.0V, CS≥Vcc-0.2V

Data retention set-up time tSDR
Recovery time tRDR 5 - -

See data retention waveform

K6T4008C1C-B - - 15
K6T4008C1C-P - - 50
K6T4008C1C-F - - 20

0 - -

5

Revision 1.0

April 1999

µA

ms

K6T4008C1C Family

TIMMING DIAGRAMS

TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH)

tRC

Address

tOH

Data Out

Previous Data Valid

TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)

Address

CS

OE

tOLZ

Data out

High-Z

tLZ

tAA

tRC

tAA

tCO1

tOE

CMOS SRAM

Data Valid

tOH

tHZ

tOHZ

Data Valid

NOTES (READ CYCLE)

1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage

levels.

2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device

interconnection.

6

Revision 1.0

April 1999

K6T4008C1C Family

TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)

Address

CS

WE

tAS(3)

Data in

Data out

TIMING WAVEFORM OF WRITE CYCLE(2) (CS Controlled)

Address

CS

Data Undefined

tAS(3)

tAW

tWHZ

tWC

tCW(2)

tAW

tWC

tCW(2)

CMOS SRAM

tWR(4)

tWP(1)

tDW tDH

Data Valid

tOW

tWR(4)

tWP(1)

WE

tDW

Data in

Data out

NOTES (WRITE CYCLE)

1. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition among CS going Low and WE
going low : A write end at the earliest transition among CS going high and WE going high, tWP is measured from the begining of write
to the end of write.

2. tCW is measured from the CS going low to end of write.

3. tAS is measured from the address valid to the beginning of write.

4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.

High-Z

Data Valid

tDH

High-Z

DATA RETENTION WAVE FORM

CS controlled

VCC

4.5V

2.2V

VDR

tSDR

Data Retention Mode

tRDR

CS
GND

CS≥VCC - 0.2V

7

Revision 1.0

April 1999

K6T4008C1C Family

CMOS SRAM

PACKAGE DIMENSIONS Units : millimeter(Inch)

32 PIN DUAL INLINE PACKAGE (600mil)

+0.10

0.25

-0.05
+0.004

0.010

-0.002

#32

13.60±0.20

0.535±0.008

#1

42.31

MAX

1.666

41.91±0.20

1.650±0.008

0.46±0.10

1.91

( )

0.075

0.018±0.004

1.52±0.10

0.060±0.004

32 PIN PLASTIC SMALL OUTLINE PACKAGE (525mil)

#32

#17

2.54

0.100

#17

#16

15.24

0.600

3.81±0.20

0.150±0.008

0.200

0.38

MIN

0.015

5.08

MAX

3.30±0.30

0.130±0.012

0~15°

0~8°

0.71

( )

0.028

0.118

MIN

3.00

11.43±0.20

0.450±0.008

MAX

+0.10

0.20

-0.05
+0.004

0.008

-0.002

0.10 MAX

0.004 MAX

13.34

0.525

0.80±0.20

0.031±0.008

Revision 1.0

14.12±0.30

0.556±0.012

#1

0.41

0.016

20.47±0.20

0.806±0.008

+0.100

-0.050
+0.004

-0.002

20.87

0.822

MAX

1.27

0.050

#16

2.74±0.20

0.108±0.008

0.05

0.002

8

April 1999

K6T4008C1C Family

CMOS SRAM

PACKAGE DIMENSIONS

32 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400F)

#32

#1

21.35

MAX

0.841

20.95±0.10

0.825±0.004

#17

#16

11.76±0.20

0.463±0.008

1.00±0.10

0.039±0.004

1.20

0.047

MAX

0.25

( )

0.010

10.16

0.400

+0.10

0.15

-0.05
+0.004

0.006

-0.002

0.10 MAX

0.004 MAX

Units : millimeter(Inch)

0~8°

0.45 ~0.75

0.018 ~ 0.030

0.50

( )

0.020

0.95

( )

0.037

0.40±0.10

0.016±0.004

1.27

0.050

32 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400R)

#1

#32

21.35

MAX

0.841

20.95±0.10

0.825±0.004

#16

#17

0.05

MIN

0.002

11.76±0.20

0.463±0.008

1.00 ±0.10

0.039±0.004

1.20

0.047

MAX

( )

0.010

10.16

0.400

0.15

0.006

0.10 MAX

0.004 MAX

0.25

+0.10

-0.05

+0.004

-0.002

0~8°

0.45 ~0.75

0.018 ~ 0.030

0.50

( )

0.020

0.95

( )

0.037

0.40±0.10

0.016±0.004

1.27

0.050

0.05

MIN

0.002

9

Revision 1.0

April 1999