Datasheet K6R1008C1A-TI20, K6R1008C1A-TI15, K6R1008C1A-TI12, K6R1008C1A-TC20, K6R1008C1A-TC12 Datasheet (Samsung)

K6R1008C1A-C, K6R1008C1A-I

CMOS SRAM

PRELIMINARY

Rev 4.0

- 1 -

February 1998

Document Title

128Kx8 High Speed Static RAM(5V Operating), Revolutionary Pin out.
Operated at Commercial and Industrial Temperature Ranges.

Revision History

The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques­tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.

Rev. No.

Rev. 0.0

Rev. 1.0

Rev. 2.0

Rev. 3.0

Rev. 4.0

Remark

Preliminary

Final

Final

Final

Final

History

Initial release with Preliminary.

Release to final Data Sheet.

1.1. Delete Preliminary

Update D.C parameters.

2.1. Update D.C parameters

Add Industrial Temperature Range parts and 300mil-SOJ PKG.

3.1. Add 32-Pin 300mil-SOJ Package.

3.2. Add Industrial Temperature Range parts with the same parame­ ters as Commercial Temperature Range parts.

3.2.1. Add K6R1008C1A parts for Industrial Temperature Range.

3.2.2. Add ordering information.

3.2.3. Add the condition for operating at Industrial Temp. Range.

3.3. Add the test condition for VOH1 with VCC=5V±5% at 25°C

3.4. Add timing diagram to define tWP as ″(Timing Wave Form of

Write Cycle(CS=Controlled)″

4.1. Delete 17ns Part

ITEMS

Previous spec.

(12/15/17/20ns part)

Updated spec.

(12/15/17/20ns part)
ICC 200/190/180/170mA 170/165/165/160mA
ISB 30mA 25mA
ISB1 10mA 8mA

Draft Data

Apr. 22th, 1995

Feb. 29th, 1996

Jul. 16th, 1996

Jun. 2nd, 1997

Feb. 25th, 1998

K6R1008C1A-C, K6R1008C1A-I

CMOS SRAM

PRELIMINARY

Rev 4.0

- 2 -

February 1998

128K x 8 Bit High-Speed CMOS Static RAM

GENERAL DESCRIPTIONFEATURES

• Fast Access Time 12, 15, 20ns(Max.)

• Low Power Dissipation
Standby (TTL) : 25mA(Max.)
(CMOS) : 8mA(Max.)
Operating K6R1008C1A-12 : 170mA(Max.)
K6R1008C1A-15 : 165mA(Max.)
K6R1008C1A-20 : 160mA(Max.)

• Single 5.0V±10% Power Supply

• TTL Compatible Inputs and Outputs

• I/O Compatible with 3.3V Device

• Fully Static Operation

- No Clock or Refresh required

• Three State Outputs

• Center Power/Ground Pin Configuration

• Standard Pin Configuration
K6R1008C1A-J : 32-SOJ-400
K6R1008C1A-T: 32-TSOP2-400CF

K6R1008C1A-C12/C15/C20 Commercial Temp.
K6R1008C1A-I12/I15/I20 Industrial Temp.

ORDERING INFORMATION

Clk Gen.

I/O1~I/O8

CS
WE
OE

FUNCTIONAL BLOCK DIAGRAM

Row Select

Data

Cont.

Column Select

A9 A10 A11 A12 A13 A14 A15 A16

CLK

Gen.

Pre-Charge Circuit

Memory Array

512 Rows

256x8 Columns

I/O Circuit

PIN FUNCTION

Pin Name Pin Function

A0 - A16 Address Inputs

WE Write Enable

CS Chip Select

OE Output Enable

I/O1 ~ I/O8 Data Inputs/Outputs

VCC Power(+5.0V)
VSS Ground

The K6R1008C1A is a 1,048,576-bit high-speed Static Random
Access Memory organized as 131,072 words by 8 bits. The
K6R1008C1A uses 8 common input and output lines and has
an output enable pin which operates faster than address access
time at read cycle. The device is fabricated using SAMSUNG′s
advanced CMOS process and designed for high-speed circuit
technology. It is particularly well suited for use in high-density
high-speed system applications. The K6R1008C1A is packaged
in a 400mil 32-pin plastic SOJ or TSOP2 forward.

PIN CONFIGURATION(Top View)

SOJ/

TSOP2

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

A16
A15
A14
A13

OE
I/O8
I/O7
Vss
Vcc
I/O6
I/O5

A12

A11

A10

A9
A8

A0
A1
A2
A3

CS
I/O1
I/O2
Vcc
Vss
I/O3
I/O4

WE

A4
A5
A6
A7

A0
A1
A2
A3
A4
A5
A6
A7
A8

K6R1008C1A-C, K6R1008C1A-I

CMOS SRAM

PRELIMINARY

Rev 4.0

- 3 -

February 1998

ABSOLUTE MAXIMUM RATINGS*

* Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and

functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Parameter Symbol Rating Unit

Voltage on Any Pin Relative to VSS VIN, VOUT -0.5 to 7.0 V
Voltage on VCC Supply Relative to VSS VCC -0.5 to 7.0 V
Power Dissipation PD 1.0 W
Storage Temperature TSTG -65 to 150 °C
Operating Temperature Commercial TA 0 to 70 °C

Industrial TA -40 to 85 °C

RECOMMENDED DC OPERATING CONDITIONS*(TA=0 to 70°C)

* The above parameters are also guaranteed at industrial temperature range.

** VIL(Min) = -2.0V a.c(Pulse Width ≤ 10ns) for I ≤ 20mA.
*** VIH(Max) = VCC + 2.0V a.c (Pulse Width ≤ 10ns) for I ≤ 20mA.

Parameter

Symbol

Min

Typ Max Unit

Supply Voltage VCC 4.5 5.0 5.5 V
Ground VSS 0 0 0 V
Input High Voltage VIH 2.2 - VCC + 0.5***

V

Input Low Voltage VIL -0.5** - 0.8

V

DC AND OPERATING CHARACTERISTICS*(TA=0 to 70°C, Vcc=5.0V±10%, unless otherwise specified)

* The above parameters are also guaranteed at industrial temperature range.
** VCC=5.0V±5%, Temp.=25°C

Parameter Symbol Test Conditions Min Max Unit

Input Leakage Current ILI VIN=VSS to VCC -2 2 µA
Output Leakage Current ILO CS=VIH or OE=VIH or WE=VIL

VOUT=VSS to VCC

-2 2 µA

Operating Current ICC Min. Cycle, 100% Duty

CS=VIL, VIN=VIH or VIL,
IOUT=0mA

12ns - 170 mA
15ns - 165
20ns - 160

Standby Current ISB Min. Cycle, CS=VIH - 25 mA

ISB1 f=0MHz, CS ≥VCC-0.2V,

VIN≥VCC-0.2V or VIN≤0.2V

- 8 mA

Output Low Voltage Level VOL IOL=8mA - 0.4 V
Output High Voltage Level VOH IOH=-4mA 2.4 - V

VOH1** IOH1=-0.1mA - 3.95 V

CAPACITANCE*(TA=25°C, f=1.0MHz)

* Capacitance is sampled and not 100% tested.

Item Symbol Test Conditions MIN Max Unit

Input/Output Capacitance CI/O VI/O=0V - 8 pF
Input Capacitance CIN VIN=0V - 6 pF

K6R1008C1A-C, K6R1008C1A-I

CMOS SRAM

PRELIMINARY

Rev 4.0

- 4 -

February 1998

TEST CONDITIONS*

* The above test conditions are also applied at industrial temperature range.

Parameter Value

Input Pulse Levels 0V to 3V
Input Rise and Fall Times 3ns
Input and Output timing Reference Levels 1.5V
Output Loads See below

AC CHARACTERISTICS(TA=0 to 70°C, VCC=5.0V±10%, unless otherwise noted.)

READ CYCLE*

* The above parameters are also guaranteed at industrial temperature range.

Parameter Symbol

K6R1008C1A-12 K6R1008C1A-15 K6R1008C1A-20

Unit

Min Max Min Max Min Max

Read Cycle Time tRC 12 - 15 - 20 - ns
Address Access Time tAA - 12 - 15 - 20 ns
Chip Select to Output tCO - 12 - 15 - 20 ns
Output Enable to Valid Output tOE - 6 - 7 - 9 ns
Chip Enable to Low-Z Output tLZ 3 - 3 - 3 - ns
Output Enable to Low-Z Output tOLZ 0 - 0 - 0 - ns
Chip Disable to High-Z Output tHZ 0 6 0 7 0 9 ns
Output Disable to High-Z Output

tOHZ

0 6 0 7 0 9 ns
Output Hold from Address Change tOH 3 - 3 - 3 - ns
Chip Selection to Power Up Time tPU 0 - 0 - 0 - ns
Chip Selection to Power DownTime tPD - 12 - 15 - 20 ns

Output Loads(A) Output Loads(B)

DOUT

5pF*

480Ω

255Ω

for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ

+5.0V

DOUT

30pF*

480Ω

255Ω

+5.0V

* Including Scope and Jig Capacitance

K6R1008C1A-C, K6R1008C1A-I

CMOS SRAM

PRELIMINARY

Rev 4.0

- 5 -

February 1998

WRITE CYCLE*

* The above parameters are also guaranteed at industrial temperature range.

Parameter Symbol

K6R1008C1A-12 K6R1008C1A-15 K6R1008C1A-20

Unit

Min Max Min Max Min Max

Write Cycle Time tWC 12 - 15 - 20 -

ns

Chip Select to End of Write tCW 8 - 10 - 12 -

ns
Address Set-up Time tAS 0 - 0 - 0 - ns
Address Valid to End of Write tAW 8 - 10 - 12 - ns
Write Pulse Width(OE High) tWP 8 - 10 - 12 - ns
Write Pulse Width(OE Low) tWP1 12 - 15 - 20 - ns
Write Recovery Time tWR 0 - 0 - 0 - ns
Write to Output High-Z tWHZ 0 6 0 7 0 9 ns
Data to Write Time Overlap tDW 6 - 7 - 9 -

ns
Data Hold from Write Time tDH 0 - 0 - 0 -

ns
End Write to Output Low-Z tOW 3 - 3 - 3 -

ns

Address

Data Out

Previous Valid Data

Valid Data

TIMMING DIAGRAMS

TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH)

tAA

tRC

tOH

TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)

CS

Address

OE

Data out

tAA

tOLZ

tLZ(4,5)

tOH

tOHZ

tRC

tOE

tCO

tPU

tPD

Valid Data

tHZ(3,4,5)

50%

50%

VCC
Current

ICC
ISB

K6R1008C1A-C, K6R1008C1A-I

CMOS SRAM

PRELIMINARY

Rev 4.0

- 6 -

February 1998

NOTES(READ CYCLE)

1. WE is high for read cycle.

2. All read cycle timing is referenced from the last valid address to the first transition address.

3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or
VOL levels.

4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to
device.

5. Transition is measured ±200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.

6. Device is continuously selected with CS=VIL.

7. Address valid prior to coincident with CS transition low.

8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.

TIMING WAVEFORM OF WRITE CYCLE(1) (OE= Clock)

Address

CS

tWP(2)

tDW tDH

Valid Data

WE

Data in

Data out

tWC

tWR(5)

tAW

tCW(3)

High-Z(8)

High-Z

OE

tOHZ(6)

tAS(4)

TIMING WAVEFORM OF WRITE CYCLE(2) (OE=Low Fixed)

Address

CS

tWP1(2)

tDW tDH

tOWtWHZ(6)

Valid Data

WE

Data in

Data out

tWC

tAS(4)

tWR(5)

tAW

tCW(3)

(10)

(9)

High-Z(8)

High-Z

K6R1008C1A-C, K6R1008C1A-I

CMOS SRAM

PRELIMINARY

Rev 4.0

- 7 -

February 1998

NOTES(WRITE CYCLE)

1. All write cycle timing is referenced from the last valid address to the first transition address.

2. A write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low

A write ends at the earliest transition CS going high or WE going high. tWP is measured from the beginning of write to the end of
write.

3. tCW is measured from the later of CS going low to end of write.

4. tAS is measured from the address valid to the beginning of write.

5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.

6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase

of the output must not be applied because bus contention can occur.

7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.

8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state.

9. Dout is the read data of the new address.

10. When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be

applied.

FUNCTIONAL DESCRIPTION

* X means Don′t Care.

CS WE OE Mode I/O Pin Supply Current

H X X* Not Select High-Z ISB, ISB1

L H H Output Disable High-Z ICC
L H L Read DOUT ICC
L L X Write DIN ICC

TIMING WAVEFORM OF WRITE CYCLE(3) (CS = Controlled)

Address

CS

tAW

tDW

tDH

Data Valid

WE

Data in

Data out

High-Z

High-Z(8)

tCW(3)

tWP(2)tAS(4)

tWC

tWR(5)

High-Z

High-Z

tLZ

tWHZ(6)

K6R1008C1A-C, K6R1008C1A-I

CMOS SRAM

PRELIMINARY

Rev 4.0

- 8 -

February 1998

#1

32-SOJ-400

#32

20.95 ±0.12

0.825 ±0.005

10.16

0.400

+0.10

MAX

21.36

0.841

0.20

-0.05

+0.004

0.008

-0.002

9.40 ±0.25

0.370 ±0.010

MAX

0.148

3.76

MIN

0.69

0.027

1.30

( )

0.051

1.30

( )

0.051

0.95

( )

0.0375

+0.10

0.43

-0.05

+0.004

0.017

-0.002

+0.10

0.71

-0.05

+0.004

0.028

-0.002

1.27

0.050

#16

#17

0.004

0.10

MAX

11.18 ±0.12

0.440 ±0.005

PACKAGE DIMENSIONS

Units:millimeters/Inches

32-TSOP2-400CF

#32

20.95 ±0.10

0.825 ±0.004

MAX

21.35

0.841

MAX

1.00 ±0.10

0.039 ±0.004

1.20

0.047

MIN

0.002

0.05

0.004 MAX

0.10 MAX

#1

0.95

( )

0.037

10.16

0.400

+0.10

0.15

-0.05
+0.004

0.006

-0.002

11.76 ±0.20

0.463 ±0.008

#17

#16

0.50

( )

0.020

0.45 ~0.75

0.018 ~ 0.030

0.25

( )

0.010

1.27

0.050

0.40 ±0.10

0.016 ±0.004

0~8°