Datasheet K4S643233F-S Datasheet (SAMSUNG)

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K4S643233F-S(D)E/N/I/P

Mobile SDRAM

(VDD/VDDQ 3.0V/3.0V or 3.3V/3.3V)

CMOS SDRAM

2Mx32

90FBGA

Revision 1.5

December 2002

Rev. 1.5 Dec. 2002

K4S643233F-S(D)E/N/I/P

512K x 32Bit x 4 Banks SDRAM

• 3.0V & 3.3 power supply.

• LVCMOS compatible with multiplexed address.

• Four banks operation.

• MRS cycle with address key programs.

-. CAS latency (1, 2 & 3).

-. Burst length (1, 2, 4, 8 & Full page).

-. Burst type (Sequential & Interleave).

• All inputs are sampled at the positive going edge of the system
clock .

• Burst read single-bit write operation.

• DQM for masking.

• Auto & self refresh.

• 64ms refresh period (4K cycle).

• Extended temperature operation (-25°C to 85°C).
Industrial temperature operation ( -40°C to 85°C).

• 90balls FBGA(-SXXX -Pb, -DXXX -Pb Free).

FUNCTIONAL BLOCK DIAGRAM

CMOS SDRAM

GENERAL DESCRIPTIONFEATURES

The K4S643233F is 67,108,864 bits synchronous high data rate
Dynamic RAM organized as 4 x 524,288 words by 32 bits, fabri­cated with SAMSUNG′s high performance CMOS technology.
Synchronous design allows precise cycle control with the use of
system clock. I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable burst lengths and
programmable latencies allow the same device to be useful for a
variety of high bandwidth and high performance memory system
applications.

ORDERING INFORMATION

Part No. Max Freq. Interface Package

K4S643233F-SE/N/I/P75

K4S643233FSE/N/I/P1H 105MHz(CL=2)

K4S643233F-SE/N/I/P1L
K4S643233F-DE/N/I/P75

K4S643233F-DE/N/I/P1H 105MHz(CL=2)

K4S643233F-DE/N/I/P1L

-S(D)E/N ; Normal/Low Power, Temp : -25°C ~ 85°C.

-S(D)I/P ; Normal/Low Power, Temp : -40°C ~ 85°C.

Note :

1. In case of 40MHz Frequency, CL1 can be supported.

133MHz(CL=3)
105MHz(CL=2)

105MHz(CL=3)

133MHz(CL=3)
105MHz(CL=2)

105MHz(CL=3)

90FBGA

Pb

*1

LVCMOS

90FBGA

Pb Free

*1

CLK

ADD

LCKE

Data Input Register

Bank Select

Refresh Counter

Row Buffer

Address Register

LRAS

LCBR

LRAS LCBR LWE LDQM

Row Decoder Col. Buffer

LCAS LWCBR

Timing Register

512K x 32
512K x 32
512K x 32
512K x 32

Column Decoder

Latency & Burst Length

Programming Register

Sense AMP

LWE

LDQM

Output BufferI/O Control

DQi

CLK CKE CS RAS CAS WE DQM

*Samsung Electronics reserves the right to change products or specification without notice.

Rev. 1.5 Dec. 2002

K4S643233F-S(D)E/N/I/P

90-Ball FBGA Package Dimension and Pin Configuration

CMOS SDRAM

1

D

Substrate(4Layer)

< Bottom View*1 >

E

1

5 2 16 3489 7
A
B
C
D
E

F
G
H
J
K
L
M
N
P
R

E

*2: Top View

*1: Bottom View

< Top View*2 >

#A1 Ball Origin Indicator

K4S643233F-XXXX

E/2

< Top View*2 >

90Ball(6x15) CSP

e

D

D/2

A

A1

z

b

A DQ26 DQ24 VSS VDD DQ23 DQ21
B DQ28 VDDQ VSSQ VDDQ VSSQ DQ19
C VSSQ DQ27 DQ25 DQ22 DQ20 VDDQ
D VSSQ DQ29 DQ30 DQ17 DQ18 VDDQ
E VDDQ DQ31 NC NC DQ16 VSSQ
F VSS DQM3 A3 A2 DQM2 VDD

G A4 A5 A6 A10 A0 A1

H A7 A8 NC NC BA1 NC

J CLK CKE A9 BA0 CS RAS

K DQM1 NC NC CAS WE DQM0

L VDDQ DQ8 VSS VDD DQ7 VSSQ

M VSSQ DQ10 DQ9 DQ6 DQ5 VDDQ

N VSSQ DQ12 DQ14 DQ1 DQ3 VDDQ
P DQ11 VDDQ VSSQ VDDQ VSSQ DQ4
R DQ13 DQ15 VSS VDD DQ0 DQ2

DQM0 ~ DQM3 Data Input/Output Mask

SAMS UNG Week

VDDQ/VSSQ Data Output Power/Ground

1 2 3 7 8 9

Pin Name Pin Function

CLK System Clock

CS Chip Select

CKE Clock Enable

A0 ~ A10 Address

BA0 ~ BA1 Bank Select Address

RAS Row Address Strobe
CAS Column Address Strobe

WE Write Enable

DQ 0 ~ 31 Data Input/Output

VDD /VSS Power Supply/Ground

[Unit:mm]

Symbol Min Typ Max

A - 1.30 1.40

A

1

E - 11.00 -

E

1

D - 13.00 -

D

1

e - 0.80 ­b 0.40 0.45 0.50
z - - 0.10

0.30 0.35 0.40

- 6.40 -

- 11.20 -

Rev. 1.5 Dec. 2002

K4S643233F-S(D)E/N/I/P

CMOS SDRAM

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Value Unit

Voltage on any pin relative to Vss VIN, VOUT -1.0 ~ 4.6 V
Voltage on VDD supply relative to Vss VDD , VDDQ -1.0 ~ 4.6 V
Storage temperature TSTG -55 ~ +150 °C
Power dissipation PD 1 W
Short circuit current IOS 50 mA

Notes :

Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

DC OPERATING CONDITIONS

Recommended operating conditions (Voltage referenced to VSS = 0V, TA = -25°C to 85°C for Extended, -40°C to 85 °C for Industrial)

Parameter Symbol Min Typ Max Unit Note

Supply voltage

Input logic high voltage VIH 2.2 3.0 VDDQ+0.3 V 1
Input logic low voltage VIL -0.3 0 0.5 V 2
Output logic high voltage VOH 2.4 - - V IOH = -2mA
Output logic low voltage VOL - - 0.4 V IOL = 2mA
Input leakage current ILI -10 - 10 uA 3

VDD 2.7 3.0 3.6 V

VDDQ 2.7 3.0 3.6 V

Notes :

1. VIH (max) = 5.3V AC. The overshoot voltage duration is ≤ 3ns.

2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns.

3. Any input 0V ≤ VIN ≤ VDDQ.
Input leakage currents include HI-Z output leakage for all bi-directional buffers with Tri-State outputs.

4. Dout is disabled, 0V ≤ VOUT ≤ VDDQ.

CAPACITANCE (VDD = 3.0V & 3.3, TA = 23°C, f = 1MHz, VREF =0.9V ± 50 mV)

Pin Symbol Min Max Unit Note

Clock CCLK - 4.0 pF
RAS, CAS, WE, CS, CKE, DQM0~ DQM3 CIN - 4.0 pF
Address(A0 ~ A10, BA0 ~ BA1) CADD - 4.0 pF
DQ0 ~ DQ31 COUT - 6.0 pF

Rev. 1.5 Dec. 2002

K4S643233F-S(D)E/N/I/P

CMOS SDRAM

DC CHARACTERISTICS

Recommended operating conditions (Voltage referenced to VSS = 0V, TA = -25°C to 85°C for Extended, -40°C to 85°C for Industrial)

Parameter Symbol Test Condition

Operating Current
(One Bank Active)

Precharge Standby Current
in power-down mode

Precharge Standby Current
in non power-down mode

Active Standby Current
in power-down mode

Active Standby Current
in non power-down mode
(One Bank Active)

Operating Current ICC4 IO = 0 mA ,Page burst 95 75 75 mA 1
Refresh Current ICC5 tRC ≥ tRC (min) 135 120 120 mA 2

Self Refresh Current ICC6 CKE ≤ 0.2V

Notes :

1. Measured with outputs open.

2. Refresh period is 64ms.

3. K4S643233F-S(D)E/I**

4. K4S643233F-S(D)N/P**

5. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ).

ICC2P CKE ≤ VIL(max), tCC = 10ns 0.5

ICC2 PS CKE & CLK ≤ VIL(max), tCC = ∞ 0.5

ICC2N

ICC2NS

ICC3P CKE ≤ VIL(max), tCC = 10ns 5

ICC3 PS CKE & CLK ≤ VIL(max), tCC = ∞ 5

ICC3N

ICC3NS

ICC1

Burst length = 1
tRC ≥ tRC(min)
IO = 0 mA

CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns

CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable

CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns

CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable

-S(D)E/I 2

-S(D)N/P 0.4 4

Version

-75 -1H -1L

80 75 75 mA 1

11

8

22 mA

22 mA

Unit Note

mA

mA

mA

mA

3

Rev. 1.5 Dec. 2002

K4S643233F-S(D)E/N/I/P

CMOS SDRAM

AC OPERATING TEST CONDITIONS (VDD = 2.7V ~ 3.6V, TA = -25°C to 85°C for Extended, -40°C to 85°C for Industrial)

Parameter Value Unit

AC input levels (Vih/Vil) 2.4 / 0.4 V
Input timing measurement reference level 0.5 x VDDQ V
Input rise and fall time tr/tf = 1/1 ns
Output timing measurement reference level 0.5 x VDDQ V
Output load condition See Fig. 2

Output

870Ω

VDDQ

1200 Ω

30pF

VOH (DC) = 2.4V, IOH = -2mA
VOL (DC) = 0.4V, I OL = 2mA

Output

Z0 = 50Ω

(Fig. 2) AC output load circuit (Fig. 1) DC output load circuit

Vtt = 0.5 x VDDQ

50Ω

30pF

OPERATING AC PARAMETER (AC operating conditions unless otherwise noted)

Parameter Symbol

Row active to row active delay tRRD (min) 15 19 19 ns 1
RAS to CAS delay tRCD(min) 19 19 24 ns 1
Row precharge time tRP(min) 19 19 24 ns 1

Row active time

Row cycle time tRC(min) 65 70 84 ns 1
Last data in to row precharge tRDL(min) 2 CLK 2,3
Last data in to Active delay tDAL (min) tRDL + tRP - 3
Last data in to new col. address delay tCDL(min) 1 CLK 2
Last data in to burst stop tBDL (min) 1 CLK 2
Col. address to col. address delay tCCD(min) 1 CLK 4

CAS latency=3 2

Number of valid output data

Notes :

1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
and then rounding off to the next higher integer.

2. Minimum delay is required to complete write.

3. Minimum tRDL=2CLK and tDAL(=tRDL + tRP) is required to complete both of last data wite command(tRDL) and precharge
command(tRP). tRDL=1CLK can be supported only in the case under 100MHz with manual precharge mode.

4. All parts allow every cycle column address change.

5. In case of row precharge interrupt, auto precharge and read burst stop.

CAS latency=2 1
CAS latency=1 - 0

tRAS(min) 45 50 60 ns 1

tRAS(max) 100 us

- 75 -1H -1L

Version

Unit Note

ea 5

Rev. 1.5 Dec. 2002

K4S643233F-S(D)E/N/I/P

AC CHARACTERISTICS (AC operating conditions unless otherwise noted)

CMOS SDRAM

Parameter Symbol

CAS latency=3

CLK cycle time

CLK to valid output delay

Output data hold time

CLK high pulse width tCH 2.5 3 3 ns 3
CLK low pulse width tCL 2.5 3 3 ns 3
Input setup time tSS 2.0 2.5 2.5 ns 3
Input hold time tSH 1.0 1.5 1.5 ns 3
CLK to output in Low-Z tSLZ 1 1 1 ns 2

CLK to output in Hi-Z

CAS latency=2 9.5 9.5 12
CAS latency=1 - - 25
CAS latency=3
CAS latency=2 7 7 8
CAS latency=1 - - 20
CAS latency=3
CAS latency=2 2.5 2.5 2.5
CAS latency=1 - - 2.5

CAS latency=3
CAS latency=2 7 7 8
CAS latency=1 - - 20

tCC

tSAC

tOH

tSHZ

- 75 -1H -1L

Min Max Min Max Min Max

7.5
1000

5.4 7 7

2.5 2.5 2.5

5.4 7 7

9.5
1000

9.5
1000 ns 1

Unit Note

ns 1,2

ns 2

ns

Notes :

1. Parameters depend on programmed CAS latency.

2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.

3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.

Notes :

1. Samsung are not designed or manufactured for use in a device or system that is used under circumstance in which human life
is potentially at stake. Please contact to the memory marketing team in samsung electronics when considering the use of
a product contained herein for any specific purpose, such as medical, aerospace, nuclear, military, vehicular or undersea
repeater use.

Rev. 1.5 Dec. 2002

K4S643233F-S(D)E/N/I/P

CMOS SDRAM

SIMPLIFIED TRUTH TABLE(V=Valid, X=Don′t Care, H=Logic High, L=Logic Low)

COMMAND CKEn-1 CKEn CS RAS CAS WE DQM BA0,1 A10/AP A9 ~ A 0 Note

Register Mode Register Set H X L L L L X OP CODE 1, 2

Auto Refresh

Refresh

Bank Active & Row Addr. H X L L H H X V Row Address
Read &

Column Address
Write &

Column Address
Burst Stop H X L H H L X X 6

Precharge

Clock Suspend or
Active Power Down

Precharge Power Down Mode

DQM H X V X 7

No Operation Command H X

Self
Refresh

Auto Precharge Disable
Auto Precharge Enable H 4, 5
Auto Precharge Disable
Auto Precharge Enable H 4, 5

Bank Selection
All Banks X H

Entry L 3

Exit L H

Entry H L

Exit L H X X X X X

Entry H L

Exit L H

H

H X L H L H X V

H X L H L L X V

H X L L H L X

H

L L L H X X

L H H H

H X X X 3

H X X X

H X X X

L H H H

H X X X

L V V V

H X X X

L H H H

X X

L

L

V L

X

X

X

X X

XL V V V

X

Column

Address

(A0~A7)

Column

Address

(A0~A7)

X

3

3

4

4

Notes :

1. OP Code : Operand Code
A0 ~ A10 & BA0 ~ BA 1 : Program keys. (@MRS)

2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.

3. Auto refresh functions are the same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.

4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If BA0 is "Low" and BA 1 is "High" at read, write, row active and precharge, bank B is selected.
If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected.

5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.

6. Burst stop command is valid at every burst length.

7. DQM sampled at the positive going edge of CLK masks the data-in at that same CLK in write operation (Write DQM latency
is 0), but in read operation it makes the data-out Hi-Z state after 2 CLK cycles. (Read DQM latency is 2).

Rev. 1.5 Dec. 2002