Datasheet K4E170412D-B, K4E160412D-F, K4E160412D-B, K4E160411D-F, K4E160411D-B Datasheet (Samsung)

K4E170411D, K4E160411D

CMOS DRAMK4E170412D, K4E160412D

This is a family of 4.194,304 x 4 bit Extended Data Out CMOS DRAMs. Extended Data Out Mode offers high speed random access of
memory cells within the same row, so called Hyper Page Mode. Power supply voltage (+5.0V or +3.3V), refresh cycle (2K Ref. or 4K
Ref.), access time (-50 or -60), power consumption(Normal or Low power) and package type(SOJ or TSOP-II) are optional features of
this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh
operation is available in L-version. This 4Mx4 EDO DRAM family is fabricated using Samsung′s advanced CMOS process to realize high
band-width, low power consumption and high reliability. It may be used as main memory unit for high level computer, microcomputer and
personal computer.

• Part Identification

- K4E170411D-B(F) (5V, 4K Ref.)

- K4E160411D-B(F) (5V, 2K Ref.)

- K4E170412D-B(F) (3.3V, 4K Ref.)

- K4E160412D-B(F) (3.3V, 2K Ref.)

• Extended Data Out Mode operation
(Fast Page Mode with Extended Data Out)

• CAS-before-RAS refresh capability

• RAS-only and Hidden refresh capability

• Self-refresh capability (L-ver only)

• Fast parallel test mode capability

• TTL(5V)/LVTTL(3.3V) compatible inputs and outputs

• Early Write or output enable controlled write

• JEDEC Standard pinout

• Available in Plastic SOJ and TSOP(II) packages

• Single +5V±10% power supply (5V product)

• Single +3.3V±0.3V power supply (3.3V product)

Control
Clocks

RAS
CAS

W

Vcc
Vss

DQ0

to

DQ3

A0-A11

(A0 - A10)*1

A0 - A9

(A0 - A10)*1

Memory Array

4,194,304 x4

Cells

SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.

4M x 4Bit CMOS Dynamic RAM with Extended Data Out

DESCRIPTION

FEATURES

FUNCTIONAL BLOCK DIAGRAM

• Refresh Cycles
Part

NO.

VCC

Refresh

cycle

Refresh period

Normal L-ver

K4E170411D 5V

4K 64ms

128ms

K4E170412D 3.3V
K4E160411D 5V

2K 32ms

K4E160412D 3.3V

• Performance Range

Speed

tRAC tCAC tRC tHPC

Remark

-50 50ns 15ns 84ns 20ns 5V/3.3V

-60 60ns 17ns 104ns 25ns 5V/3.3V

• Active Power Dissipation

Speed

3.3V 5V

4K 2K 4K 2K

-50 324 396 495 605

-60 288 360 440 550

Unit : mW

Sense Amps & I/O

Data out

Buffer

Data in

Buffer

OE

Note) *1 : 2K Refresh

Col. Address Buffer

Row Address Buffer

Refresh Counter

Refresh Control

Refresh Timer

Column Decoder

Row Decoder

VBB Generator

K4E170411D, K4E160411D

CMOS DRAMK4E170412D, K4E160412D

PIN CONFIGURATION (Top Views)

Pin Name Pin Function

A0 - A11 Address Inputs (4K Product)
A0 - A10 Address Inputs (2K Product)

DQ0 - 3 Data In/Out

VSS Ground
RAS Row Address Strobe
CAS Column Address Strobe

W Read/Write Input

OE Data Output Enable

VCC

Power(+5.0V)
Power(+3.3V)

N.C No Connection (2K Ref. product)

VCC
DQ0
DQ1

W

RAS

*A11(N.C)

A10

A0
A1
A2
A3

VCC

VSS
DQ3
DQ2
CAS
OE
A9

A8
A7
A6
A5
A4
VSS

1
2
3
4
5
6

7
8
9
10
11
12

24
23
22
21
20
19

18
17
16
15
14
13

VCC
DQ0
DQ1

W

RAS

*A11(N.C)

A10

A0
A1
A2
A3

VCC

VSS
DQ3
DQ2
CAS
OE
A9

A8
A7
A6
A5
A4
VSS

1
2
3
4
5
6

7
8
9
10
11
12

24
23
22
21
20
19

18
17
16
15
14
13

*A11 is N.C for K4E160411(2)D(5V/3.3V, 2K Ref. product)
B : 300mil 26(24) SOJ

F: 300mil 26(24) TSOP II

• K4E17(6)0411(2)D-B

• K4E17(6)0411(2)D-F

K4E170411D, K4E160411D

CMOS DRAMK4E170412D, K4E160412D

ABSOLUTE MAXIMUM RATINGS

* Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to

the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

Parameter Symbol

Rating

Units

3.3V 5V

Voltage on any pin relative to VSS VIN,VOUT -0.5 to +4.6 -1.0 to +7.0 V
Voltage on VCC supply relative to VSS VCC -0.5 to +4.6 -1.0 to +7.0 V
Storage Temperature Tstg -55 to +150 -55 to +150 °C
Power Dissipation PD 1 1 W
Short Circuit Output Current IOS Address 50 50 mA

RECOMMENDED OPERATING CONDITIONS (Voltage referenced to Vss, TA= 0 to 70°C)

*1 : VCC+1.3V/15ns(3.3V), VCC+2.0/20ns(5V), Pulse width is measured at VCC
*2 : -1.3V/15ns(3.3V), -2.0/20ns(5V), Pulse width is measured at VSS

Parameter Symbol

3.3V 5V
Units

Min Typ Max Min Typ Max

Supply Voltage VCC 3.0 3.3 3.6 4.5 5.0 5.5 V
Ground VSS 0 0 0 0 0 0 V
Input High Voltage VIH 2.0 -

VCC+0.3

*1

2.4 -

VCC+1.0

*1

V

Input Low Voltage VIL

-0.3

*2

- 0.8

-1.0

*2

- 0.8 V

DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.)

Max Parameter Symbol Min Max Units

3.3V

Input Leakage Current (Any input 0≤VIN≤VIN+0.3V,
all other input pins not under test=0 Volt)

II(L) -5 5 uA

Output Leakage Current
(Data out is disabled, 0V≤VOUT≤VCC)

IO(L) -5 5 uA

Output High Voltage Level(IOH=-2mA) VOH 2.4 - V
Output Low Voltage Level(IOL=2mA) VOL - 0.4 V

5V

Input Leakage Current (Any input 0≤VIN≤VIN+0.5V,
all other input pins not under test=0 Volt)

II(L) -5 5 uA

Output Leakage Current
(Data out is disabled, 0V≤VOUT≤VCC)

IO(L) -5 5 uA

Output High Voltage Level(IOH=-5mA) VOH 2.4 - V
Output Low Voltage Level(IOL=4.2mA) VOL - 0.4 V

K4E170411D, K4E160411D

CMOS DRAMK4E170412D, K4E160412D

*Note :

ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open.
ICC is specified as an average current. In ICC1, ICC3, ICC6 and ICC7, address can be changed maximum once while RAS=VIL. In
ICC4, address can be changed maximum once within one Hyper page mode cycle time, tHPC.

DC AND OPERATING CHARACTERISTICS (Continued)

ICC1* : Operating Current (RAS and CAS cycling @tRC=min.)
ICC2 : Standby Current (RAS=CAS=W=VIH)
ICC3* : RAS-only Refresh Current (CAS=VIH, RAS cycling @tRC=min.)
ICC4* : Hyper Page Mode Current (RAS=VIL, CAS, Address cycling @tHPC=min.)
ICC5 : Standby Current (RAS=CAS=W=VCC-0.2V)
ICC6* : CAS-Before-RAS Refresh Current (RAS and CAS cycling @tRC=min.)
ICC7 : Battery back-up current, Average power supply current, Battery back-up mode
Input high voltage(VIH)=VCC-0.2V, Input low voltage(VIL)=0.2V, CAS=0.2V,
DQ=Don′t care, TRC=31.25us(4K/L-ver), 62.5us(2K/L-ver), TRAS=TRASmin~300ns
ICCS : Self Refresh Current
RAS=CAS=0.2V, W=OE=A0 ~ A11=VCC-0.2V or 0.2V,
DQ0 ~ DQ3=VCC-0.2V, 0.2V or Open

Symbol Power Speed

Max

Units

K4E170412D K4E160412D K4E170411D K4E160411D

ICC1 Don′t care

-50

-60

90
80

110
100

90
80

110
100

mA
mA

ICC2

Normal

L

Don′t care

1
1

1
1

2
1

2
1

mA
mA

ICC3 Don′t care

-50

-60

90
80

110
100

90
80

110
100

mA
mA

ICC4 Don′t care

-50

-60

80
70

90
80

80
70

90
80

mA
mA

ICC5

Normal

L

Don′t care

0.5

200

0.5

200

1

250

1

250

mA

uA

ICC6 Don′t care

-50

-60

90
80

110
100

90
80

110
100

mA
mA

ICC7 L Don′t care 250 250 300 300 uA

ICCS L Don′t care 200 200 250 250 uA

K4E170411D, K4E160411D

CMOS DRAMK4E170412D, K4E160412D

CAPACITANCE (TA=25°C, VCC=5V or 3.3V, f=1MHz)

Parameter Symbol Min Max Units

Input capacitance [A0 ~ A11] CIN1 - 5 pF
Input capacitance [RAS, CAS, W, OE] CIN2 - 7 pF
Output capacitance [DQ0 - DQ3] CDQ - 7 pF

Test condition (5V device) : VCC=5.0V±10%, Vih/Vil=2.4/0.8V, Voh/Vol=2.0/0.8V

Parameter Symbol

-50 -60
Units Notes

Min Max Min Max

Random read or write cycle time

tRC

84 104 ns

Read-modify-write cycle time

tRWC

116 140 ns

Access time from RAS

tRAC

50 60 ns 3,4,10

Access time from CAS

tCAC

13 15 ns 3,4,5

Access time from column address

tAA

25 30 ns 3,10

CAS to output in Low-Z

tCLZ

3 3 ns 3

Output buffer turn-off delay from CAS

tCEZ

3 13 3 15 ns 6,14

OE to output in Low-Z

tOLZ

3 3 ns 3

Transition time (rise and fall)

tT

2 50 2 50 ns 2

RAS precharge time

tRP

30 40 ns

RAS pulse width

tRAS

50 10K 60 10K ns

RAS hold time

tRSH

13 15 ns

CAS hold time

tCSH

38 45 ns

CAS pulse width

tCAS

8 10K 10 10K ns

RAS to CAS delay time

tRCD

20 37 20 45 ns 4

RAS to column address delay time

tRAD

15 25 15 30 ns 10

CAS to RAS precharge time

tCRP

5 5 ns

Row address set-up time

tASR

0 0 ns

Row address hold time

tRAH

10 10 ns

Column address set-up time

tASC

0 0 ns

Column address hold time

tCAH

8 10 ns

Column address to RAS lead time

tRAL

25 30 ns

Read command set-up time

tRCS

0 0 ns

Read command hold time referenced to CAS

tRCH

0 0 ns 8

Read command hold time referenced to RAS

tRRH

0 0 ns 8

Write command hold time

tWCH

10 10 ns

Write command pulse width

tWP

10 10 ns

Write command to RAS lead time

tRWL

13 15 ns

Write command to CAS lead time

tCWL

8 10 ns

AC CHARACTERISTICS (0°C≤TA≤70°C, See note 1,2)

Test condition (3.3V device) : VCC=3.3V±0.3V, Vih/Vil=2.0/0.8V, Voh/Vol=2.0/0.8V

K4E170411D, K4E160411D

CMOS DRAMK4E170412D, K4E160412D

AC CHARACTERISTICS (Continued)

Parameter Symbol

-50 -60
Units Notes

Min Max Min Max

Data set-up time

tDS

0 0 ns 9

Data hold time

tDH

8 10 ns 9

Refresh period (2K, Normal)

tREF

32 32 ms

Refresh period (4K, Normal)

tREF

64 64 ms

Refresh period (L-ver)

tREF

128 128 ms

Write command set-up time

tWCS

0 0 ns 7

CAS to W delay time

tCWD

30 34 ns 7

RAS to W delay time

tRWD

67 79 ns 7

Column address to W delay time

tAWD

42 49 ns 7

CAS precharge to W delay time

tCPWD

47 54 ns

CAS set-up time (CAS -before-RAS refresh)

tCSR

5 5 ns

CAS hold time (CAS -before-RAS refresh)

tCHR

10 10 ns

RAS to CAS precharge time

tRPC

5 5 ns

Access time from CAS precharge

tCPA

28 35 ns 3

Hyper Page cycle time

tHPC

20 25 ns 13

Hyper Page read-modify-write cycle time

tHPRWC

47 56 ns 13

CAS precharge time (Hyper Page cycle)

tCP

8 10 ns

RAS pulse width (Hyper Page cycle)

tRASP

50 200K 60 200K ns

RAS hold time from CAS precharge

tRHCP

30 35 ns

OE access time

tOEA

13 15 ns

OE to data delay

tOED

13 15 ns

Output buffer turn off delay time from OE

tOEZ

3 13 3 15 ns 6

OE command hold time

tOEH

13 15 ns

Write command set-up time (Test mode in)

tWTS

10 10 ns 11

Write command hold time (Test mode in)

tWTH

10 10 ns 11

W to RAS precharge time(C-B-R refresh)

tWRP

10 10 ns

W to RAS hold time(C-B-R refresh)

tWRH

10 10 ns

Output data hold time

tDOH

5 5 ns

Output buffer turn off delay from RAS

tREZ

3 13 3 15 ns 6,14

Output buffer turn off delay from W

tWEZ

3 13 3 15 ns 6

W to data delay

tWED

15 15 ns

OE to CAS hold time

tOCH

5 5 ns

CAS hold time to OE

tCHO

5 5 ns

OE precharge time

tOEP

5 5 ns

W pulse width (Hyper Page Cycle)

tWPE

5 5 ns

RAS pulse width (C-B-R self refresh)

tRASS

100 100 us 15,16,17

RAS precharge time (C-B-R self refresh)

tRPS

90 110 ns 15,16,17

CAS hold time (C-B-R self refresh)

tCHS

-50 -50 ns 15,16,17

K4E170411D, K4E160411D

CMOS DRAMK4E170412D, K4E160412D

TEST MODE CYCLE

Parameter Symbol

-50 -60
Units Note

Min Max Min Max

Random read or write cycle time

tRC

89 109 ns

Read-modify-write cycle time

tRWC

121 145 ns

Access time from RAS

tRAC

55 65 ns 3,4,10,12

Access time from CAS

tCAC

18 20 ns 3,4,5,12

Access time from column address

tAA

30 35 ns 3,10,12

RAS pulse width

tRAS

55 10K 65 10K ns

CAS pulse width

tCAS

13 10K 15 10K ns

RAS hold time

tRSH

18 20 ns

CAS hold time

tCSH

43 50 ns

Column address to RAS lead time

tRAL

30 35 ns

CAS to W delay time

tCWD

35 39 ns 7

RAS to W delay time

tRWD

72 84 ns 7

Column address to W delay time

tAWD

47 54 ns 7

CAS precharge to W delay time

tCPWD

52 59 ns

Hyper Page cycle time

tHPC

25 30 ns 13

Hyper Page read-modify-write cycle time

tHPRWC

53 61 ns 13

RAS pulse width (Hyper Page cycle)

tRASP

55 200K 65 200K ns

Access time from CAS precharge

tCPA

33 40 ns 3

OE access time

tOEA

18 20 ns

OE to data delay

tOED

18 20 ns

OE command hold time

tOEH

18 20 ns

( Note 11 )

K4E170411D, K4E160411D

CMOS DRAMK4E170412D, K4E160412D

NOTES

An initial pause of 200us is required after power-up followed by any 8 RAS-only refresh or CAS-before-RAS refresh cycles
before proper device operation is achieved.
VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition times are measured between
VIH(min) and VIL(max) and are assumed to be 2ns for all inputs.
Measured with a load equivalent to 2 TTL(5V)/1 TTL(3.3V) loads and 100pF.
Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only.
If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC.
Assumes that tRCD≥tRCD(max).
This parameter defines the time at which the output achieves the open circuit condition and is not referenced to Voh or Vol.

tWCS, tRWD, tCWD and tAWD are non restrictive operating parameters. They are included in the data sheet as electrical charac-

teristics only. If tWCS≥tWCS(min), the cycle is an early write cycle and the data output will remain high impedance for the dura­tion of the cycle. If tCWD≥tCWD(min), tRWD≥tRWD(min) and tAWD≥tAWD(min), then the cycle is a read-modify-write cycle and the
data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the condition
of the data out is indeterminate.
Either tRCH or tRRH must be satisfied for a read cycle.
These parameters are referenced to CAS falling edge in early write cycles and to W falling edge in OE controlled write cycle
and read-modify-write cycles.
Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference point only. If

tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA.

These specifications are applied in the test mode.
In test mode read cycle, the value of tRAC, tAA, tCAC is delayed by 2ns to 5ns for the specified values. These parameters
should be specified in test mode cycles by adding the above value to the specified value in this data sheet.

tASC≥6ns, Assume tT = 2.0ns

If RAS goes high before CAS high going, the open circuit condition of the output is achieved by CAS high going. If CAS goes
high before RAS high going, the open circuit condition of the output is achieved by RAS high going.
If tRASS≥100us, then RAS precharge time must use tRPS instead of tRP.
For RAS-only refresh and burst CAS-before-RAS refresh mode, 4096(4K)/2048(2K) cycles of burst refresh must be exe­cuted within 64ms/32ms before and after self refresh, in order to meet refresh specification.
For distributed CAS-before-RAS with 15.6us interval CAS-before-RAS refresh should be executed with in 15.6us immedi­ately before and after self refresh in order to meet refresh specification.

5.

6.

7.

8.

9.

10.

11.

12.

13.

14.

15.

16.

1.

2.

3.

4.

17.

K4E170411D, K4E160411D

CMOS DRAMK4E170412D, K4E160412D

RAS

VIH -
VIL -

CAS

VIH -
VIL -

A

VIH -
VIL -

W

VIH -
VIL -

OE

VIH -
VIL -

VOH -
VOL -

COLUMN

ADDRESS

ROW

ADDRESS

tRAS

tRC

tCRP

tRP

tCSH

tRSHtRCD

tCAS

tRAL

tASR tRAH tASC

tCAH

tCRP

tAA

tOEA

tCLZ

tRAC

OPEN

tRCH

Don′t care

Undefined

tRAD

tRRH

DATA-OUT

tREZ

tRCS

READ CYCLE

tOEZ

tCEZ

tWEZ

DQ0 ~ DQ3(7)

tOLZ

tCAC

K4E170411D, K4E160411D

CMOS DRAMK4E170412D, K4E160412D

tWCS

NOTE : DOUT = OPEN

WRITE CYCLE ( EARLY WRITE )

RAS

VIH -
VIL -

VIH -
VIL -

A

VIH -
VIL -

W

VIH -
VIL -

OE

VIH -
VIL -

VIH -
VIL -

COLUMN

ADDRESS

ROW

ADDRESS

tRAS

tRC

tCRP

tRP

tCSH

tRSHtRCD

tCAS

tRAL

tRAD

tASR tRAH tASC

tCAH

tCRP

Don′t care

Undefined

tWCH

tWP

CAS

tRWL

tCWL

tDS

tDH

DATA-IN

DQ0 ~ DQ3(7)

K4E170411D, K4E160411D

CMOS DRAMK4E170412D, K4E160412D

NOTE : DOUT = OPEN

WRITE CYCLE ( OE CONTROLLED WRITE )

RAS

VIH -
VIL -

A

VIH -
VIL -

W

VIH -
VIL -

OE

VIH -
VIL -

VIH -
VIL -

DQ0 ~ DQ3(7)

COLUMN

ADDRESS

ROW

ADDRESS

tRAS

tRC

tCRP

tRP

tCSH

tRSHtRCD
tCAS

tRAL

tRAD

tASR tRAH tASC

tCAH

tCRP

tWP

Don′t care

Undefined

CAS

VIH -
VIL -

tRWL

tCWL

tDH

tOEH

tOED

DATA-IN

tDS

K4E170411D, K4E160411D

CMOS DRAMK4E170412D, K4E160412D

READ - MODIFY - WRITE CYCLE

RAS

VIH -
VIL -

CAS

VIH -
VIL -

A

VIH -
VIL -

W

VIH -
VIL -

OE

VIH -
VIL -

VI/OH -
VI/OL -

DQ0 ~ DQ3(7)

ROW

ADDR

tRAS

tRWC

tRP

tRSHtRCD

tCAS

tCSH

tRAD

tASR tRAH tASC tCAH

tCRP

VALID

tWP

Don′t care

tRWL

tCWL

tOEZ

tOEA

tOED

tAWD
tCWD

tRWD

DATA-OUT

Undefined

VALID

DATA-IN

tRAC

tAA

tCAC

tCLZ

tDS tDH

COLUMN

ADDRESS

tOLZ

K4E170411D, K4E160411D

CMOS DRAMK4E170412D, K4E160412D

tDOH

HYPER PAGE READ CYCLE

RAS

VIH -
VIL -

CAS

VIH -
VIL -

A

VIH -
VIL -

W

VIH -
VIL -

OE

VIH -
VIL -

COLUMN

ADDRESS

ROW

ADDR

tRASP

tRP

tRCD

tASR

tCRP

Don′t care

Undefined

VOH -
VOL -

DQ0 ~ DQ3(7)

tOEP

COLUMN

ADDRESS

tCAS tCAS tCAS tCAS

tCP tCP tCP

tHPC tHPC tHPC

tRHCP

tCSH

tRAD

tRAH tASC tCAH tCAH tCAH tASC tCAH

tRCS

tAA

tRCH

tASC

COLUMN

ADDRESS

COLUMN

ADDR

VALID

DATA-OUT

tOEZ

tOEA

tOEP

tAA

tCAC

tAA

tCPA

tCPA

VALID

DATA-OUT

VALID

DATA-OUT

tOEZ

tCLZ

tRAC

tOEA

tOLZ

tCAC

tRRH

tCHO

tREZ

tOEZ

tCAC

tOCH

tCPA

tCAC

VALID

DATA-OUT

¡ó

tASC

tAA

tRAL

tOEA

K4E170411D, K4E160411D

CMOS DRAMK4E170412D, K4E160412D

RAS

VIH -
VIL -

CAS

VIH -
VIL -

A

VIH -
VIL -

W

VIH -
VIL -

OE

VIH -
VIL -

COLUMN

ADDRESS

ROW

ADDR.

tRASP

tRP

tRCD

tASR

tCRP

Don′t care

HYPER PAGE WRITE CYCLE ( EARLY WRITE )

Undefined

VIH -
VIL -

DQ0 ~ DQ3(7)

tRHCP

tRAD

tRAH tCAH tCAH tASC tCAHtASC

VALID

DATA-IN

tDS

¡ó

COLUMN

ADDRESS

COLUMN

ADDRESS

tCAS

tCP

tCAS

tCP

tCAS

tRSH

¡ó

tCSH

tASC

¡ó

¡ó

tWP

tWCS

tWCH

tWP

tWCS

tWCH

tWP

tWCH

¡ó

¡ó

¡ó

VALID

DATA-IN

VALID

DATA-IN

¡ó

¡ó

tDH tDS tDH tDS tDH

tCWL tCWL tCWL

tRWL

NOTE : DOUT = OPEN

tHPC tHPC

tWCS

tRAL

K4E170411D, K4E160411D

CMOS DRAMK4E170412D, K4E160412D

Don′t care

HYPER PAGE READ-MODIFY-WRITE CYCLE

Undefined

RAS

VIH -
VIL -

CAS

VIH -
VIL -

A

VIH -
VIL -

W

VIH -
VIL -

OE

VIH -
VIL -

VI/OH -
VI/OL -

ROW

ADDR

tCSH

tRASP

tRP

tASR

tRCD

tCP

tRAD

tCAH

tWP

tDH

COL.

ADDR

COL.

ADDR

tCAS tCAS

tCRP

tASC

tCAH

tRAL

tRCS

tCWL

tCWD

tAWD

tRWD

tWP

tCWD

tAWD

tCWL

tRAC

tOEA

tCLZ

tOEZ

tCPWD

tOED

tASC

tCLZ

tOEA

tCAC

tAA

tDH

tOED

tRWL

tCRP

tDS

tOEZ

VALID

DATA-OUT

VALID

DATA-IN

VALID

DATA-OUT

VALID

DATA-IN

tDS

DQ0 ~ DQ3(7)

tRSH

tOLZ

tOLZ

tHPRWC

tCAC

tAA

tRAH

K4E170411D, K4E160411D

CMOS DRAMK4E170412D, K4E160412D

HYPER PAGE READ AND WRITE MIXED CYCLE

RAS

VIH -
VIL -

CAS

VIH -
VIL -

A

VIH -
VIL -

W

VIH -
VIL -

OE

VIH -
VIL -

COLUMN

ADDRESS

ROW

ADDR

tRASP

tRP

Don′t care

Undefined

VI/OH -
VI/OL -

DQ0 ~ DQ3(7)

tWEZ

tCP tCP

tHPC tHPC tHPC

tRAD

tRAH

tASC tCAH tCAH

tCAH

tASC tCAH

tRCHtRCS tRCS tRCH

tASC

COLUMN

ADDRESS

COL.

ADDR

VALID
DATA-OUT

tREZ

tAA

tWCS

VALID
DATA-OUT

VALID

DATA-OUT

VALID
DATA-IN

tRAC

COL.

ADDR

tCAS

tASR

tCAStCAS

tCAS

tASC

tCP

tRCH tWCH

tWPE

tCLZ

tCPA

tWED

tAA

tWEZ

tDS

tDH

tCAC

tOEA

READ(tCAC) READ(tCPA) WRITE READ(tAA)

tRHCP

tRAL

tCLZ

K4E170411D, K4E160411D

CMOS DRAMK4E170412D, K4E160412D

Don′t care

RAS - ONLY REFRESH CYCLE*

NOTE : W, OE, DIN = Don′t care

Undefined

DOUT = OPEN

RAS

VIH -
VIL -

CAS

VIH -
VIL -

A

VIH -
VIL -

ROW

ADDR

tRC

tRP

tASR

tCRP

tRAS

tRAH

tRPC tCRP

OPEN

CAS - BEFORE - RAS REFRESH CYCLE

NOTE : OE , A = Don′t care

RAS

VIH ­VIL -

CAS

VIH ­VIL -

tRC

tRP

tRAS

tRPC

tCP

tRPC

tCSR

tCHR

tCEZ

VOH ­VOL -

DQ0 ~ DQ3(7)

tWRP

tWRH

W

VIH ­VIL -

tRP

K4E170411D, K4E160411D

CMOS DRAMK4E170412D, K4E160412D

HIDDEN REFRESH CYCLE ( READ )

tOEZ

DATA-OUT

tRP

RAS

VIH -
VIL -

CAS

VIH -
VIL -

A

VIH -
VIL -

W

VIH -
VIL -

OE

VIH -
VIL -

ROW

ADDRESS

tRAS

tRC

tCHRtRCD tRSH

tRAD

tASR tRAH tASC

tCRP

Don′t care

Undefined

VOH -
VOL -

DQ0 ~ DQ3(7)

tWRH

COLUMN

ADDRESS

tOEA

tRAS

tRC

tCAH

tRCS

tAA

tRAC

tCLZ

tCAC

tCEZ

OPEN

tRP

tWEZ

tREZ

tOLZ

tRAL

K4E170411D, K4E160411D

CMOS DRAMK4E170412D, K4E160412D

tCRP

tWCS

tRP

RAS

VIH -
VIL -

A

VIH -
VIL -

W

VIH -
VIL -

OE

VIH -
VIL -

ROW

ADDRESS

tRAS

tRC

tRAD

tASR tRAH tASC

Don′t care

HIDDEN REFRESH CYCLE ( WRITE )

Undefined

CAS

VIH -
VIL -

VIH -
VIL -

DQ0 ~ DQ3(7)

tRSHtRCD

tWRH

COLUMN

ADDRESS

tRAS

tRC

tCHR

tCAH

tWRP

tDS

NOTE : DOUT = OPEN

tWP

tWCH

DATA-IN

tDH

tRP

tRAL

K4E170411D, K4E160411D

CMOS DRAMK4E170412D, K4E160412D

OPEN

CAS - BEFORE - RAS SELF REFRESH CYCLE

NOTE : OE, A = Don′t care

RAS

VIH -

VIL -

CAS

VIH -

VIL -

tRPS

tRASS

tRPC

tCP

tRPC

tCSR

tCEZ

VOH ­VOL -

DQ0 ~ DQ3(7)

tRP

Don′t care
Undefined

tCHS

tWRP tWRH

W

VIH -

VIL -

OPEN

TEST MODE IN CYCLE

NOTE : OE , A = Don′t care

RAS

VIH -

VIL -

CAS

VIH -

VIL -

tRP

tRC

tRPC

tCP

tRPC

tCSR

tOFF

VOH ­VOL -

DQ0 ~ DQ3(7)

tWTS

tWTH

W

VIH -

VIL -

tCHR

tRP

tRAS

K4E170411D, K4E160411D

CMOS DRAMK4E170412D, K4E160412D

0.300 (7.62)

0.330 (8.39)

0.340 (8.63)

0.680 (17.28)

0.670 (17.03)

MAX

0.691 (17.55)
MAX

0.148 (3.76)

0.0375 (0.95)

0.032 (0.81)

0.026 (0.66)

0.021 (0.53)

0.015 (0.38)

0.027 (0.69)

0.012 (0.30)

0.006 (0.15)

0.260 (6.61)

0.280 (7.11)

MIN

#26(24)

0.050 (1.27)

26(24) SOJ 300mil

Units : Inches (millimeters)

PACKAGE DIMENSION

26(24) TSOP(II) 300mil

MAX

0.047 (1.20)

MIN

0.002 (0.05)

0.020 (0.50)

0.012 (0.30)

0.050 (1.27)0.037 (0.95)

0.671 (17.04)

0.679 (17.24)

0.691 (17.54)
MAX

0.010 (0.25)

0.004 (0.10)

0.300 (7.62)

0.371 (9.42)

0.355 (9.02)

Units : Inches (millimeters)

0~8

0.030 (0.75)

0.018 (0.45)

TYP

0.010 (0.25)

O