Formerly Available as FSS913A0R4,
Radiation Hardened, SEGR Resistant,
P-Channel Power MOSFETs
The Discrete Products Operation of Intersil has developeda
series of Radiation Hardened MOSFETs specifically
designed for commercial and military space applications.
Enhanced Power MOSFET immunity to Single Event Effects
(SEE), Single Event Gate Rupture (SEGR) in particular, is
combined with100K RADS of total dose hardness to provide
devices which are ideally suited to harsh space
environments. The dose rate and neutron tolerance
necessary for military applications have not been sacrificed.
The Intersil portfolio of SEGR resistant radiation hardened
MOSFETs includes N-Channel and P-Channel devices in a
variety of voltage, current and on-resistance ratings.
Numerous packaging options are also available.
This MOSFET is an enhancement-mode silicon-gate power
field-effect transistor of the vertical DMOS (VDMOS)
structure. It is specially designed and processed to be
radiation tolerant. The MOSFET is well suited for
applications exposed to radiation environments such as
switching regulation, switching converters, motor drives,
relay drivers and drivers for high-power bipolar switching
transistors requiring high speed and low gate drive power.
This type can be operated directly from integrated circuits.
Also availableat other radiation and screening levels.Seeus
on the web, Intersil’s home page: http://www.intersil.com.
Contact y our local Intersil Sales Office f or additional
information.
Ordering Information
PART NUMBERPACKAGEBRAND
JANSR2N7440TO-257AAJANSR2N7440
Features
• 10A, -100V, r
• Total Dose
- Meets Pre-RAD Specifications to 100K RAD (Si)
• Single Event
- Safe Operating Area Curve for Single Event Effects
- SEE Immunity for LET of 36MeV/mg/cm
V
up to 80% of Rated Breakdown and
DS
V
of 10V Off-Bias
GS
• Dose Rate
- Typically Survives 3E9 RAD (Si)/s at 80% BV
- Typically Survives 2E12 if Current Limited to I
• Photo Current
- 1.5nA Per-RAD(Si)/s Typically
• Neutron
- Maintain Pre-RAD Specifications
for 3E13 Neutrons/cm
- Usable to 3E14 Neutrons/cm
DS(ON)
= 0.280Ω
2
2
with
2
Symbol
D
G
S
Packaging
TO-257AA
S
D
G
DSS
DM
Die Family TA17796.
MIL-PRF-19500/659.
CAUTION: Beryllia Warning per MIL-S-19500
refer to package specifications.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical SpecificationsT
= 25oC, Unless Otherwise Specified
C
4.4
g
PARAMETERSYMBOLTEST CONDITIONSMINTYPMAXUNITS
Drain to Source Breakdown VoltageBV
Gate Threshold VoltageV
Drain to Source Breakdown Volts(Note 3)BV
Gate to Source Threshold Volts(Note 3)V
Gate to Body Leakage(Notes 2, 3)I
Zero Gate Leakage(Note 3)I
Drain to Source On-State Volts(Notes 1, 3)V
Drain to Source On Resistance(Notes 1, 3)r
FIGURE 7. NORMALIZED MAXIMUM TRANSIENT THERMAL RESPONSE
4
Page 5
Performance Curves (Continued)
40
10
, AVALANCHE CURRENT (A)
AS
I
1
Test Circuits and Waveforms
JANSR2N7440
STARTING TJ = 25oC
STARTING TJ = 150oC
IF R = 0
tAV = (L) (IAS) / (1.3 RATED BVDSS - VDD)
IF R ≠ 0
tAV = (L/R) ln [(IAS*R) / (1.3 RATED BVDSS - VDD) + 1]
0.01
0.1
tAV, TIME IN AVALANCHE (ms)
FIGURE 8. UNCLAMPED INDUCTIVE SWITCHING
110
VARY t
TO OBTAIN
P
REQUIRED PEAK I
0V
t
P
VGS≤ 20V
CURRENT
TRANSFORMER
50Ω
AS
ELECTRONIC SWITCH OPENS
WHEN I
V
DS
L
+
I
AS
-
50Ω
DUT
IS REACHED
AS
+
V
DD
-
50V-150V
BV
DSS
t
P
I
AS
t
AV
FIGURE 9. UNCLAMPED ENERGY TEST CIRCUITFIGURE 10. UNCLAMPED ENERGY WAVEFORMS
t
t
d(ON)
90%
ON
t
r
V
DD
R
L
V
DS
V
DS
V
t
d(OFF)
DS
t
OFF
V
DD
t
f
90%
0V
V
GS
= -12V
DUT
R
GS
V
GS
10%
10%
10%
90%
50%50%
PULSE WIDTH
FIGURE 11. RESISTIVE SWITCHING TEST CIRCUITFIGURE 12. RESISTIVE SWITCHING WAVEFORMS
5
Page 6
JANSR2N7440
Screening Information
Screening is performed in accordance with the latest revision in effect of MIL-S-19500, (Screening Information Table).
Delta Tests and Limits (JANS) T
PARAMETERSYMBOLTEST CONDITIONSMAXUNITS
Gate to Source Leakage CurrentI
Zero Gate Voltage Drain CurrentI
Drain to Source On Resistancer
Gate Threshold VoltageV
NOTES:
7. Or 100% of Initial Reading (whichever is greater).
8. Of Initial Reading.
Screening Information
TESTJANS
Unclamped Inductive SwitchingV
Thermal ResponsetH = 100ms; VH = -25V; IH = 1A; Limit = 85mV
Gate StressVGS = -30V, t = 250µs
PindRequired
Pre Burn-In Tests (Note 9)MIL-S-19500 Group A,
Steady State Gate
Bias (Gate Stress)
Interim Electrical Tests (Note 9)All Delta Parameters Listed in the Delta Tests and Limits Table
Steady State Reverse
Bias (Drain Stress)
PDA5%
Final Electrical Tests (Note 9)MIL-S-19500, Group A,
NOTE:
9. Test limits are identical pre and post burn-in.
= 25oC, Unless Otherwise Specified
C
GSS
DSS
DS(ON)
GS(TH)
VGS = ±20V±20 (Note 7)nA
VDS = 80% Rated Value±25 (Note 7)µA
TC = 25oC at Rated I
ID = 1.0mA±20% (Note 8)V
GS(PEAK)
Subgroup 2 (All Static Tests at 25oC)
MIL-STD-750, Method 1042, Condition B
VGS = 80% of Rated Value,
TA = 150oC, Time = 48 hours
MIL-STD-750, Method 1042, Condition A
VDS = 80% of Rated Value,
TA = 150oC, Time = 240 hours
Subgroups 2 and 3
= -15V, L = 0.1mH; Limit = 30A
D
±20% (Note 8)Ω
Additional Screening Tests
PARAMETERSYMBOLTEST CONDITIONSMAXUNITS
Safe Operating AreaSOAVDS = -80V, t = 10ms1.9A
Thermal Impedance∆V
6
SD
tH = 500ms; VH = -25V; IH = 1A125mV
Page 7
JANSR2N7440
Rad Hard Data Packages - Intersil Power Transistors
1. JANS Rad Hard - Standard Data Package
A. Certificate of Compliance
B. Serialization Records
C. Assembly Flow Chart
D. SEM Photos and Report
E. Preconditioning - Attributes Data Sheet
- Hi-Rel Lot Traveler
- HTRB - Hi Temp Gate Stress Post
Reverse Bias Data and Delta Data
- HTRB - Hi Temp Drain Stress Post
Reverse Bias Delta Data
F. Group A- Attributes Data Sheet
G. Group B- Attributes Data Sheet
H. Group C- Attributes Data Sheet
I. Group D- Attributes Data Sheet
2. JANS Rad Hard - Optional Data Package
A. Certificate of Compliance
B. Serialization Records
C. Assembly Flow Chart
D. SEM Photos and Report
E. Preconditioning - Attributes Data Sheet
- Hi-Rel Lot Traveler
- HTRB - Hi Temp Gate Stress Post
Reverse Bias Data and Delta Data
- HTRB - Hi Temp Drain Stress Post
Reverse Bias Delta Data
- X-Ray and X-Ray Report
F. Group A- Attributes Data Sheet
- Hi-Rel Lot Traveler
- Subgroups A2, A3, A4, A5 and A7 Data
G. Group B- Attributes Data Sheet
- Hi-Rel Lot Traveler
- Subgroups B1, B3, B4, B5 and B6 Data
H. Group C- Attributes Data Sheet
- Hi-Rel Lot Traveler
- Subgroups C1, C2, C3 and C6 Data
I. Group D- Attributes Data Sheet
- Hi-Rel Lot Traveler
- Pre and Post Radiation Data
7
Page 8
TO-257AA
3 LEAD JEDEC TO-257AA HERMETIC METAL PACKAGE
JANSR2N7440
E
Q
ØP
H
1
A
A
1
SYMBOL
A0.1900.2004.835.08-
A
1
INCHESMILLIMETERS
NOTESMINMAXMINMAX
0.0350.0450.891.14-
Øb0.0250.0350.640.882, 3
D
Øb
0.0600.0901.532.28-
1
D0.6450.66516.3916.89E0.4100.42010.4210.66-
e0.100 TYP2.54 TYP4
L
1
L
123
0.065 R TYP.
Øb
e
e
1
Øb
1
J
1
e
1
H
1
J
1
L0.6000.65015.2416.51-
L
1
ØP0.1400.1503.563.81-
Q0.1130.1332.883.37-
NOTES:
0.200 BSC5.08 BSC4
0.2300.2505.856.35-
0.1100.1302.803.304
-0.035-0.88-
1. These dimensions are within allowabledimensions of Rev.Bof
JEDEC TO-257AA dated 9-88.
2. Add typically 0.002 inches (0.05mm) for solder coating.
3. Lead dimension (without solder).
4. Positionoflead tobemeasured 0.150 inches(3.81mm)from bottom
of dimension D.
5. Die to base BeO isolated, terminals to case ceramic isolated.
6. Controlling dimension: Inch.
7. Revision 1 dated 1-93.
WARNING!
BERYLLIA WARNING PER MIL-S-19500
Packagescontaining beryllium oxide (BeO) shall not be ground, machined, sandblasted, or subject to any mechanical operation
which will produce dust containing any beryllium compound. Packages containing any beryllium compound shall not be
subjected to any chemical process (etching, etc.) which will produce fumes containing beryllium or its’ compounds.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only.Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (321) 724-7000
FAX: (321) 724-7240
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
ASIA
Intersil (Taiwan) Ltd.
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
8
Loading...
+ hidden pages
You need points to download manuals.
1 point = 1 manual.
You can buy points or you can get point for every manual you upload.