- Safe Operating Area Curve for Single Event Effects
- SEE Immunity for LET of 36MeV/mg/cm
V
up to 80% of Rated Breakdown and
DS
V
of 10V Off-Bias
GS
• Dose Rate
- Typically Survives 3E9 RAD (Si)/s at 80% BV
- Typically Survives 2E12 if Current Limited to I
• Photo Current
- 0.3nA Per-RAD(Si)/s Typically
• Neutron
- Maintain Pre-RAD Specifications
for 3E13 Neutrons/cm
- Usable to 3E14 Neutrons/cm
Ordering Information
PART NUMBERPACKAGEBRAND
JANSR2N7411TO-205AFJANSR2N7411
DS(ON)
= 1.30Ω
2
2
2
with
DSS
DM
2.5A, -100V, 1.30 Ohm, Rad Hard,
P-Channel Power MOSFET
Description
The Discrete Products Operation of Intersil Corporationhas
developed a series of Radiation Hardened MOSFETs specifically designed for commercial and military space applications. Enhanced Power MOSFET immunity to Single Event
Effects (SEE), Single Event Gate Rupture (SEGR) in particular, is combined with 100K RADS of total dose hardness to
provide devices which are ideally suited to harsh space environments. The dose rate and neutron tolerance necessary
for military applications have not been sacrificed.
The Intersil portfolio of SEGR resistant radiation hardened
MOSFETs includes N-Channel and P-Channel devices in a
variety of voltage, current and on-resistance ratings.
Numerous packaging options are also available.
This MOSFET is an enhancement-mode silicon-gate power
field-effect transistor of the vertical DMOS (VDMOS) structure. It is specially designed and processed to be radiation
tolerant. The MOSFET is well suited for applications
exposed to radiation environments such as switching regulation, switching converters, motor drives, relay drivers and
drivers for high-power bipolar switching transistors requiring
high speed and low gate drive power. This type can be
operated directly from integrated circuits.
Also available at other radiation and screening levels. See us
on the web, Intersil’ s home page:http://www.intersil.com. Contact your local Intersil Sales Office for additional information.
Die Family TA17716.
MIL-PRF-19500/639.
Symbol
Package
TO-205AF
G
S
D
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications T
= 25oC, Unless Otherwise Specified
C
1.0
g
PARAMETERSYMBOLTEST CONDITIONSMINTYPMAXUNITS
Drain to Source Breakdown VoltageBV
Gate Threshold VoltageV
Drain to Source Breakdown Volts(Note 3)BV
Gate to Source Threshold Volts(Note 3)V
Gate to Body Leakage(Notes 2, 3)I
Zero Gate Leakage(Note 3)I
Drain to Source On-State Volts(Notes 1, 3)V
Drain to Source On Resistance(Notes 1, 3)r
tH = 10ms; VH = -15V; IH = 1A90mV
tH = 500ms; VH = -15V; IH = 1A230mV
= -15V, L = 0.1mH7.5A
2-105
Page 7
JANSR2N7411
Rad Hard Data Packages - Intersil Power Transistors
1. JANS Rad Hard - Standard Data Package
A. Certificate of Compliance
B. Serialization Records
C. Assembly Flow Chart
D. SEM Photos and Report
E. Preconditioning
F. Group A- Attributes Data Sheet
G. Group B- Attributes Data Sheet
H. Group C- Attributes Data Sheet
I. Group D- Attributes Data Sheet
2. JANS Rad Hard - Optional Data Package
A. Certificate of Compliance
B. Serialization Records
C. Assembly Flow Chart
D. SEM Photos and Report
E. Preconditioning - Attributes Data Sheet
F. Group A- Attributes Data Sheet
G. Group B- Attributes Data Sheet
H. Group C- Attributes Data Sheet
I. Group D- Attributes Data Sheet
Attributes Data Sheet
Hi-Rel Lot Traveler
HTRB - Hi Temp Gate Stress Post Reverse
Bias Data and Delta Data
HTRB - Hi T emp Drain Stress Post Reverse
Bias Delta Data
- Hi-Rel Lot Traveler
- HTRB - Hi Temp Gate Stress Post
Reverse Bias Data and Delta Data
- HTRB - Hi Temp Drain Stress Post
Reverse Bias Delta Data
1. These dimensions are within allowable dimensions of Rev . E of
JEDEC TO-205AF outline dated 11-82.
2. Lead dimension (without solder).
3. Solder coating may vary along lead length, add typically 0.002
inches (0.05mm) for solder coating.
4. Position of lead to be measured 0.100 inches (2.54mm) from bottom
of seating plane.
5. This zone controlled for automatic handling. The variation in
actual diameter within this zone shall not exceed 0.010 inches
(0.254mm).
6. Lead no. 3 butt welded to stem base.
7. Controlling dimension: Inch.
8. Revision 3 dated 6-94.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under an y patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.inter sil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (407) 724-7000
FAX: (407) 724-7240
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
2-107
ASIA
Intersil (Taiwan) Ltd.
Taiwan Limited
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
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