Datasheet JANSR2N7405 Datasheet (Intersil)

JANSR2N7405

Formerly FSF150R4

June 1998

Features

• 25A (Note), 100V, r

• Total Dose

- Meets Pre-RAD Specifications to 100K RAD (Si)

• Single Event

- Safe Operating Area Curve for Single Event Effects

- SEE Immunity for LET of 36MeV/mg/cm
V

up to 80% of Rated Breakdown and

DS

V

of 10V Off-Bias

GS

• Dose Rate

- Typically Survives 3E9 RAD (Si)/s at 80% BV

- Typically Survives 2E12 if Current Limited to I

• Photo Current

- 7.0nA Per-RAD(Si)/s Typically

• Neutron

- Maintain Pre-RAD Specifications
for 3E13 Neutrons/cm

- Usable to 3E14 Neutrons/cm

Ordering Information

PART NUMBER PACKAGE BRAND

JANSR2N7405 TO-254AA JANSR2N7405

Die Family TA17656.

DS(ON)

= 0.070Ω

2

2

2

with

DSS

DM

25A, 100V, 0.070 Ohm, Rad Hard,

N-Channel Power MOSFET

Description

The Discrete Products Operation of Intersil Corporation has
developed a series of Radiation Hardened MOSFETs specif­ically designed for commercial and military space applica­tions. Enhanced Power MOSFET immunity to Single Event
Effects (SEE), Single Event Gate Rupture (SEGR) in particu­lar, is combined with 100K RADS of total dose hardness to
provide devices which are ideally suited to harsh space envi­ronments. The dose rate and neutron tolerance necessary
for military applications have not been sacrificed.

The Intersil portfolio of SEGR resistant radiation hardened
MOSFETs includes N-Channel and P-Channel devices in a
variety of voltage, current and on-resistance ratings.
Numerous packaging options are also available.

This MOSFET is an enhancement-mode silicon-gate power
field-effect transistor of the vertical DMOS (VDMOS) struc­ture. It is specially designed and processed to be radiation
tolerant. The MOSFET is well suited for applications
exposed to radiation environments such as switching regula­tion, switching converters, motor drives, relay drivers and
drivers for high-power bipolar switching transistors requiring
high speed and low gate drive power. This type can be
operated directly from integrated circuits.

Also available at other r adiation and screening le v els . See us
on the web, Intersil’s home page: http://www.intersil.com.
Contact your local Intersil Sales Office for additional
information.

MIL-PRF-19500/634.

NOTE: Current is limited by the package capability.

Symbol

Package

TO-254AA

G

S

CAUTION: Beryllia Warning per MIL-S-19500

refer to package specifications.

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207

| Copyright © Intersil Corporation 1999

2-82

D

File Number 4375.1

JANSR2N7405

Absolute Maximum Ratings T

= 25oC, Unless Otherwise Specified

C

JANSR2N7405 UNITS

Drain to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V

Drain to Gate Voltage (RGS = 20kΩ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

DS

DGR

100 V
100 V

Continuous Drain Current

TC = 25oC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

TC = 100oC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

D
D

DM

GS

25 A
20 A
75 A

±20 V

Maximum Power Dissipation

TC = 25oC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .P

TC = 100oC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .P

T
T

125 W

50 W

Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.00 W/oC

Single Pulsed Avalanche Current, L = 100µH, (See Test Figure) . . . . . . . . . . . . . . . . . . . . . I

Continuous Source Current (Body Diode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Pulsed Source Current (Body Diode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TJ, T

STG

Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T

AS

S

SM

L

75 A
25 A
75 A

-55 to 150
300

o

C

o

C

(Distance >0.063in (1.6mm) from Case, 10s Max)

Weight (Typical) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Electrical Specifications T

= 25oC, Unless Otherwise Specified

C

9.3

g

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Drain to Source Breakdown Voltage BV
Gate Threshold Voltage V

DSSID

GS(TH)VGS

= 1mA, VGS = 0V 100 - - V

= VDS,

ID = 1mA

TC = -55oC - - 5.0 V
TC = 25oC 1.5 - 4.0 V
TC = 125oC 0.5 - - V

Zero Gate Voltage Drain Current I

Gate to Source Leakage Current I

DSS

GSS

VDS = 80V,
VGS = 0V

TC = 25oC--25µA
TC = 125oC - - 250 µA

VGS = ±20V TC = 25oC - - 100 nA

TC = 125oC - - 200 nA
Drain to Source On-State Voltage V
Drain to Source On Resistance r

Turn-On Delay Time t

DS(ON)VGS

DS(ON)12ID

d(ON)

Rise Time t
Turn-Off Delay Time t

d(OFF)

Fall Time t
Total Gate Charge (Not on slash sheet) Q

g(TOT)VGS

Gate Charge at 12V Q
Threshold Gate Charge (Not on slash sheet) Q
Gate Charge Source Q
Gate Charge Drain Q
Thermal Resistance Junction to Case R
Thermal Resistance Junction to Ambient R

r

f

g(12)

g(TH)

gs

gd

JC

θ

JA

θ

= 12V, ID = 25A - - 1.84 V

= 20A,

VGS = 12V

VDD = 50V, ID = 25A,
RL = 2.0Ω, VGS = 12V,
RGS = 2.35Ω

TC = 25oC - 0.045 0.070 Ω

TC = 125oC - - 0.105 Ω

- - 140 ns

- - 310 ns

- - 170 ns

- - 70 ns

= 0V to 20V VDD = 50V,

VGS = 0V to 12V - 130 160 nC

ID = 25A

- - 240 nC

VGS = 0V to 2V - - 8.1 nC

-2331nC

-6788nC

- - 1.00oC/W

--48oC/W

2-83

Source to Drain Diode Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Forward Voltage V
Reverse Recovery Time t

SD
rr

JANSR2N7405

ISD = 25A 0.6 - 1.8 V
ISD = 25A,dISD/dt = 100A/µs - - 400 ns

Electrical Specifications up to 100K RAD T

= 25oC, Unless Otherwise Specified

C

PARAMETER SYMBOL TEST CONDITIONS MIN MAX UNITS

Drain to Source Breakdown Volts (Note 3) BV
Gate to Source Threshold Volts (Note 3) V

GS(TH)

Gate to Body Leakage (Notes 2, 3) I
Zero Gate Leakage (Note 3) I
Drain to Source On-State Volts (Notes 1, 3) V
Drain to Source On Resistance (Notes 1, 3) r

DS(ON)VGS

DS(ON)12VGS

DSS

GSS
DSS

VGS = 0, ID = 1mA 100 - V
VGS = VDS, ID = 1mA 1.5 4.0 V
VGS = ±20V, VDS = 0V - 100 nA
VGS = 0, VDS = 80V - 25 µA

= 12V, ID = 25A - 1.84 V
= 12V, ID = 20A - 0.070 Ω

NOTES:

1. Pulse test, 300µs Max.

2. Absolute value.

3. Insitu Gamma bias must be sampled for both VGS = 12V, VDS = 0V and VGS = 0V, VDS = 80% BV

DSS

.

Single Event Effects (SEB, SEGR) (Note 4)

ENVIRONMENT (NOTE 5)

APPLIED

VGS BIAS

TEST SYMBOL

Single Event Effects Safe Operating
Area

ION

SPECIES

SEESOA Ni 26 43 -20 100

Br 37 36 -10 100

TYPICAL LET

(MeV/mg/cm)

TYPICAL

RANGE (µ)

Br 37 36 -15 80
Br 37 36 -20 50

NOTES:

4. Testing conducted at Brookhaven National Labs; sponsored by Naval Surface Warfare Center (NSWC), Crane, IN.

5. Fluence = 1E5 ions/cm2 (typical), TC = 25oC.

6. Does not exhibit Single Event Burnout (SEB) or Single Event Gate Rupture (SEGR).

(V)

(NOTE 6)

MAXIMUM

VDS BIAS

(V)

Typical Performance Curves

LET = 26MeV/mg/cm

120

100

80

(V)

60

DS

V

40

20

TEMP = 25oC

0

0 -10

LET = 37MeV/mg/cm2, RANGE = 36µ

FLUENCE = 1E5 IONS/cm2 (TYPICAL)

-5
V

(V)

GS

Unless Otherwise Specified

2

, RANGE = 43µ

-15

-20 -25

1E-3

1E-4

1E-5

1E-6

LIMITING INDUCTANCE (HENRY)

1E-7

30

DRAIN SUPPLY (V)

ILM = 10A

30A

100A

300A

30010010

FIGURE 1. SINGLE EVENT EFFECTS SAFE OPERATING AREA FIGURE 2. DRAIN INDUCTANCE REQUIRED TO LIMIT

GAMMA DOT CURRENT TO I

AS

2-84

1000

JANSR2N7405

Typical Performance Curves

40

30

20

, DRAIN (A)

D

I

10

0

TC, CASE TEMPERATURE (oC)

500-50

Unless Otherwise Specified (Continued)

100

FIGURE 3. MAXIMUM CONTINUOUS DRAIN CURRENT vs

CASE TEMPERATURE

150

100

10

1

, DRAIN CURRENT (A)

D

I

0.1

OPERATION IN THIS
AREA MAY BE
LIMITED BY r

1

VDS, DRAIN TO SOURCE VOLTAGE (V)

DS(ON)

10

TC = 25oC

FIGURE 4. FORWARD BIAS SAFE OPERATING AREA

2.5

2.0

PULSE DURATION = 250ms, VGS = 12V, ID = 20A

100µs

1ms

10ms

100ms

100

DS(ON)

12V

V

Q

G

Q

GS

G

Q

GD

CHARGE

1.5

1.0

NORMALIZED r

0.5

0.0

-80 -40 0 40 80 120 160

FIGURE 5. BASIC GATE CHARGE WAVEFORM FIGURE 6. NORMALIZED r

10

)

JC

θ

1

0.5

0.2

0.1

0.1

0.05

0.02

0.01

0.01

NORMALIZED THERMAL RESPONSE (Z

0.001

-5

10

SINGLE PULSE

-4

10

NOTES:
DUTY FACTOR: D = t

PEAK TJ = PDM x Z

-3

10

t, RECTANGULAR PULSE DURATION (s)

-2

10

, JUNCTION TEMPERATURE (oC)

T

J

vs JUNCTION TEMPERA TURE

DS(ON)

P

DM

1/t2

+ T

JC

C

θ

-1

10

0

10

t

1

t

2

1

10

FIGURE 7. NORMALIZED MAXIMUM TRANSIENT THERMAL RESPONSE

2-85

JANSR2N7405

Typical Performance Curves

300

100

10

, AVALANCHE CURRENT (A)

AS

I

1

0.01 0.1 1 10

FIGURE 8. UNCLAMPED INDUCTIVE SWITCHING

Test Circuits and Waveforms

ELECTRONIC SWITCH OPENS

WHEN I

V

DS

Unless Otherwise Specified (Continued)

STARTING TJ = 25oC

STARTING TJ = 150oC

IF R = 0

= (L) (IAS) / (1.3 RATED BV

t

AV

IF R ≠ 0
tAV = (L/R) ln [(IAS*R) /
(1.3 RATED BV

IS REACHED

AS

- VDD) + 1]

DSS

t

, TIME IN AVALANCHE (ms)

AV

DSS

- VDD)

VARY t

TO OBTAIN

P

REQUIRED PEAK I

VGS≤ 20V

t

0V

P

CURRENT

TRANSFORMER

50Ω

AS

L

+

I

AS

-

+

V

DD

-

DUT

50Ω

50V-150V

t

I

AS

BV

DSS

P

t

AV

FIGURE 9. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 10. UNCLAMPED ENERGY WAVEFORMS

t

t

d(ON)

90%

ON

10%

t

r

PULSE WIDTH

0V

VGS = 12V

V

DD

R

L

V

DS

DUT

R

GS

V

DS

V

GS

10%

V

DS

t

d(OFF)

90%

t

OFF

50%50%

V

t

f

10%

DD

90%

FIGURE 11. RESISTIVE SWITCHING TEST CIRCUIT FIGURE 12. RESISTIVE SWITCHING WAVEFORMS

2-86

JANSR2N7405

Screening Information

Screening is performed in accordance with the latest revision in effect of MIL-S-19500, (Screening Information Table).

Delta Tests and Limits (JANS) T

PARAMETER SYMBOL TEST CONDITIONS MAX UNITS

= 25oC, Unless Otherwise Specified

C

Gate to Source Leakage Current I
Zero Gate Voltage Drain Current I
Drain to Source On Resistance r
Gate Threshold Voltage V

NOTES:

7. Or 100% of Initial Reading (whichever is greater).

8. Of Initial Reading.

GSS

DSS

DS(ON)

GS(TH)

VGS = ±20V ±20 (Note 7) nA
VDS = 80% Rated Value ±25 (Note 7) µA
TC = 25oC at Rated I
ID = 1.0mA ±20% (Note 8) V

D

±20% (Note 8) Ω

Screening Information

TEST JANS

Gate Stress VGS = 30V, t = 250µs
Pind Required
Pre Burn-In Tests (Note 9) MIL-S-19500 Group A,

Subgroup 2 (All Static Tests at 25oC)

Steady State Gate
Bias (Gate Stress)

Interim Electrical Tests (Note 9) All Delta Parameters Listed in the Delta Tests and Limits Table
Steady State Reverse

Bias (Drain Stress)

MIL-STD-750, Method 1042, Condition B
VGS = 80% of Rated Value,
TA = 150oC, Time = 48 hours

MIL-STD-750, Method 1042, Condition A
VDS = 80% of Rated Value,

TA = 150oC, Time = 240 hours
PDA 5%
Final Electrical Tests (Note 9) MIL-S-19500, Group A,

Subgroups 2 and 3

NOTE:

9. Test limits are identical pre and post burn-in.

Additional Screening Tests

PARAMETER SYMBOL TEST CONDITIONS MAX UNITS

Safe Operating Area SOA VDS = 80V, t = 10ms 4.50 A
Unclamped Inductive Switching I
Thermal Response ∆V
Thermal Impedance ∆V

AS

SD

SD

V

GS(PEAK)

tH = 100ms; VH = 25V; IH = 4A 136 mV
tH = 500ms; VH = 25V; IH = 4A 187 mV

= 15V, L = 0.1mH 75 A

2-87

JANSR2N7405

Rad Hard Data Packages - Intersil Power Transistors

1. JANS Rad Hard - Standard Data Package
A. Certificate of Compliance
B. Serialization Records
C. Assembly Flow Chart
D. SEM Photos and Report
E. Preconditioning

F. Group A - Attributes Data Sheet
G. Group B - Attributes Data Sheet
H. Group C - Attributes Data Sheet

I. Group D - Attributes Data Sheet

2. JANS Rad Hard - Optional Data Package
A. Certificate of Compliance
B. Serialization Records
C. Assembly Flow Chart
D. SEM Photos and Report
E. Preconditioning - Attributes Data Sheet

F. Group A - Attributes Data Sheet

G. Group B - Attributes Data Sheet

H. Group C - Attributes Data Sheet

I. Group D - Attributes Data Sheet

Attributes Data Sheet
Hi-Rel Lot Traveler
HTRB - Hi Temp Gate Stress Post Reverse
Bias Data and Delta Data
HTRB - Hi T emp Drain Stress Post Reverse
Bias Delta Data

- Hi-Rel Lot Traveler

- HTRB - Hi Temp Gate Stress Post
Reverse Bias Data and Delta Data

- HTRB - Hi Temp Drain Stress Post
Reverse Bias Delta Data

- X-Ray and X-Ray Report

- Hi-Rel Lot Traveler

- Subgroups A2, A3, A4, A5 and A7 Data

- Hi-Rel Lot Traveler

- Subgroups B1, B3, B4, B5 and B6 Data

- Hi-Rel Lot Traveler

- Subgroups C1, C2, C3 and C6 Data

- Hi-Rel Lot Traveler

- Pre and Post Radiation Data

2-88

JANSR2N7405

TO-254AA

3 LEAD JEDEC TO-254AA HERMETIC METAL PACKAGE

A

A

1

J

1

SYMBOL

A 0.249 0.260 6.33 6.60 -

A

1

Øb 0.035 0.045 0.89 1.14 2, 3

D 0.790 0.800 20.07 20.32 ­E 0.535 0.545 13.59 13.84 -

e 0.150 TYP 3.81 TYP 4

e

1

H

1

J

1

L 0.520 0.560 13.21 14.22 -

ØP 0.139 0.149 3.54 3.78 -

Q 0.110 0.130 2.80 3.30 -

NOTES:

1. These dimensions are within allowable dimensions of Rev . A of
JEDEC outline TO-254AA dated 11-86.

2. Add typically 0.002 inches (0.05mm) for solder coating.

3. Lead dimension (without solder).

4. Position of lead to be measured 0.250 inches (6.35mm) from bot­tom of dimension D.

5. Die to base BeO isolated, terminals to case ceramic isolated.

6. Controlling dimension: Inch.

7. Revision 1 dated 1-93.

TYP.

b

Ø

ØP

H

1

E

Q

D

0.065 R MAX.

L

123

e

e

1

INCHES MILLIMETERS

NOTESMIN MAX MIN MAX

0.040 0.050 1.02 1.27 -

0.300 BSC 7.62 BSC 4

0.245 0.265 6.23 6.73 -

0.140 0.160 3.56 4.06 4

WARNING!

BERYLLIA WARNING PER MIL-S-19500

Packages containing beryllium oxide (BeO) shall not be ground, machined, sandblasted, or subject to any mechanical
operation which will produce dust containing any beryllium compound. Packages containing any beryllium compound
shall not be subjected to any chemical process (etching, etc.) which will produce fumes containing beryllium or its’
compounds.

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under an y patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site http://www.inter sil.com

Sales Office Headquarters

NORTH AMERICA

Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: [phone]
FAX: [phone]

EUROPE

Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: [phone]
FAX: [phone]

ASIA

Intersil (Taiwan) Ltd.
Taiwan Limited
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: [phone]
FAX: [phone]

2-89