Datasheet JANSR2N7294 Datasheet (Intersil)

JANSR2N7294

Formerly FRF250R4

June 1998

Features

• 23A, 200V, r

• Total Dose

- Meets Pre-RAD Specifications to 100K RAD (Si)

• Dose Rate

- Typically Survives 3E9 RAD (Si)/s at 80% BV

- Typically Survives 2E12 if Current Limited to I

• Photo Current

- 12nA Per-RAD(Si)/s Typically

• Neutron

- Maintain Pre-RAD Specifications
for 1E13 Neutrons/cm

- Usable to 1E14 Neutrons/cm

Ordering Information

PART NUMBER PACKAGE BRAND

DS(ON)

= 0.115Ω

2

2

DSS

DM

23A, 200V, 0.115 Ohm, Rad Hard,

N-Channel Power MOSFET

Description

The Intersil Corporation has designed a series of SECOND
GENERATION hardened power MOSFETs of both N-Chan­nel and P-Channel enhancement types with ratings from
100V to 500V, 1A to 60A, and on resistance as low as
25mΩ. Total dose hardness is offered at 100K RAD (Si) and
1000K RAD (Si) with neutron hardness ranging from 1E13
for 500V product to 1E14 for 100V product. Dose rate hard­ness (GAMMA DOT) exists for rates to 1E9 without current
limiting and 2E12 with current limiting.

This MOSFET is an enhancement-mode silicon-gate power
field effect transistor of the vertical DMOS (VDMOS) struc­ture. It is specially designed and processed to exhibit mini­mal characteristic changes to total dose (GAMMA) and
neutron (n
also directed to enhance survival to dose rate (GAMMA
DOT) exposure.

Also availableat other radiation and screening levels. See us
on the web, Intersil’ home page: http://www.intersil.com.
Contact your local Intersil Sales Office for additional informa­tion.

o

) exposures. Design and processing efforts are

JANSR2N7294 TO-254AA JANSR2N7294

Die family TA17652.
MIL-PRF-19500/605.

Package

CAUTION: Beryllia Warning per MIL-S-19500

Symbol

TO-254AA

G

S

D

refer to package specifications.

D

G

S

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 2000.

2-23

File Number 4292.1

JANSR2N7294

Absolute Maximum Ratings T

= 25oC, Unless Otherwise Specified

C

JANSR2N7294 UNITS

Drain to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V

Drain to Gate Voltage (RGS = 20kΩ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

DS

DGR

200 V
200 V

Continuous Drain Current

TC = 25oC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

TC = 100oC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V

D
D

DM

GS

23 A
15 A
69 A

±20 V

Maximum Power Dissipation

TC = 25oC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .P

TC = 100oC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .P

T
T

125 W

50 W

Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.00 W/oC

Single Pulsed Avalanche Current, L = 100µH, (See Test Figure). . . . . . . . . . . . . . . . . . . . . . I

Continuous Source Current (Body Diode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Pulsed Source Current (Body Diode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TJ,T

STG

Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T

AS

S

SM

L

69 A
23 A
69 A

-55 to 150
300

o

C

o

C

(Distance >0.063in (1.6mm) from Case, 10s Max)

Weight (Typical) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.3 g

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Electrical Specifications T

= 25oC, Unless Otherwise Specified

C

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Drain to Source Breakdown Voltage BV
Gate Threshold Voltage V

GS(TH)VGS

Zero Gate Voltage Drain Current I

Gate to Source Leakage Current I

Drain to Source On-State Voltage V
Drain to Source On Resistance r

Turn-On Delay Time t

DS(ON)VGS

DS(ON)ID

d(ON)

Rise Time t
Turn-Off Delay Time t

d(OFF)

Fall Time t
Total Gate Charge (Not on slash sheet) Q

g(TOT)VGS

Gate Charge at 10V Q
Threshold Gate Charge (Not on slash sheet) Q
Gate Charge Source Q
Gate Charge Drain Q
Thermal Resistance Junction to Case R
Thermal Resistance Junction to Ambient R

DSSID

DSS

GSS

r

f

g(10)

g(TH)

gs

gd

JC

θ

JA

θ

= 1mA, VGS = 0V 200 - - V

= VDS,

ID = 1mA

VDS = 160V,
VGS = 0V

TC = -55oC - - 5.0 V

= 25oC 2.0 - 4.0 V

T

C

= 125oC 1.0 - - V

T

C

TC = 25oC--25µA

= 125oC - - 250 µA

T

C

VGS = ±20V TC = 25oC - - 100 nA

= 125oC - - 200 nA

T

C

= 10V, ID = 23A - - 2.78 V

= 15A,

VGS = 10V
VDD = 100V, ID = 23A,

RL = 4.35Ω, VGS = 10V,
RGS = 25Ω

TC = 25oC - - 0.115 Ω

= 125oC - - 0.253 Ω

T

C

- - 156 ns

- - 510 ns

- - 574 ns

- - 280 ns

= 0V to 20V VDD = 100V,

VGS = 0V to 10V - - 298 nC

ID = 23A

- - 558 nC

VGS = 0V to 2V - - 20 nC

- - 66 nC

- - 144 nC

- - 1.0

o

C/W

--48oC/W

Source to Drain Diode Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Forward Voltage V
Reverse Recovery Time t

SD

rr

ISD = 25A 0.6 - 1.8 V
ISD = 25A, dISD/dt = 100A/µs - - 1700 ns

2-24

JANSR2N7294

Electrical Specifications up to 100K RAD T

= 25oC, Unless Otherwise Specified

C

PARAMETER SYMBOL TEST CONDITIONS MIN MAX UNITS

Drainto Source BreakdownVolts (Note 3) BV
Gate to Source Threshold Volts (Note 3) V
Gate to Body Leakage (Notes 2, 3) I
Zero Gate Leakage (Note 3) I
Drain to Source On-State Volts (Notes 1, 3) V
Drain to Source On Resistance (Notes 1, 3) r

DS(ON)

DSS

GS(TH)

GSS

DSS

DS(ON)

VGS = 0, ID = 1mA 200 - V
VGS = VDS, ID = 1mA 2.0 4.0 V
VGS = ±20V, VDS = 0V - 100 nA
VGS = 0, VDS = 160V - 25 µA
VGS = 10V, ID = 23A - 2.78 V
VGS = 10V, ID = 15A - 0.115 Ω

NOTES:

1. Pulse test, 300µs Max.

2. Absolute value.

3. Insitu Gamma bias must be sampled for both VGS = 10V, VDS = 0V and VGS = 0V, VDS = 80% BV

Typical Performance Curves Unless Otherwise Specified

28

24

100

DSS

.

TC = 25oC

20

16

12

, DRAIN (A)

D

I

8

4

0

TC, CASE TEMPERATURE (oC)

FIGURE 1. MAXIMUM CONTINUOUS DRAIN CURRENT vs

CASE TEMPERATURE

10

1

, DRAIN CURRENT (A)

D

I

150100500-50

0.1

OPERATION IN THIS
AREA MAY BE
LIMITED BY r

1

DS(ON)

10

, DRAIN TO SOURCE VOLTAGE (V)

V

DS

100

100µs

1ms

10ms
100ms

FIGURE 2. FORWARD BIAS SAFE OPERATING AREA

2-25

JANSR2N7294

Typical Performance Curves Unless Otherwise Specified (Continued)

10

)

JC

1

θ

NORMALIZED

0.01

THERMAL RESPONSE (Z

0.001

0.1

0.5

0.2

0.1

0.05

0.02

0.01
SINGLE PULSE

-5

10

-4

10

-3

10

t, RECTANGULAR PULSE DURATION (s)

-2

10

FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL RESPONSE

Test Circuits and Waveforms

NOTES:
DUTY FACTOR: D = t
PEAK TJ = PDM x Z

-1

10

P

DM

t

1

t

2

1/t2

+ T

JC

C

θ

0

10

1

10

VARY t

TO OBTAIN

P

REQUIRED PEAK I

VGS≤ 20V

t

0V

P

CURRENT

TRANSFORMER

50Ω

AS

ELECTRONIC SWITCH OPENS

WHEN I

V

DS

L

+

I

AS

-

50Ω

DUT

IS REACHED

AS

+

V

DD

-

50V-150V

BV

DSS

t

P

I

AS

t

AV

FIGURE 4. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 5. UNCLAMPED ENERGY WAVEFORMS

V

DS

V

DD

2-26

Test Circuits and Waveforms

JANSR2N7294

V

DD

R

L

VGS = 10V

DUT

0V

R

GS

FIGURE 6. RESISTIVE SWITCHING TEST CIRCUIT

10V

Q

GS

t

ON

t

d(ON)

t

V

DS

V

DS

V

GS

90%

10%

r

10%

PULSE WIDTH

t

d(OFF)

90%

t

OFF

50%50%

t

f

10%

90%

FIGURE 7. RESISTIVE SWITCHING WAVEFORMS

Q

G

Q

GD

V

G

CHARGE

FIGURE 8. BASIC GATE CHARGE WAVEFORM

2-27

JANSR2N7294

Screening Information

Screening is performed in accordance with the latest revision in effect of MIL-S-19500, (Screening Information Table).

Delta Tests and Limits (JANS) T

PARAMETER SYMBOL TEST CONDITIONS MAX UNITS

= 25oC, Unless Otherwise Specified

C

Gate to Source Leakage Current I
Zero Gate Voltage Drain Current I
Drain to Source On Resistance r
Gate Threshold Voltage V

NOTES:

4. Or 100% of Initial Reading (whichever is greater).

5. Of Initial Reading.

GSS

DSS

DS(ON)

GS(TH)

VGS = ±20V ±20 (Note 4) nA
VDS = 80% Rated Value ±25 (Note 4) µA
TC = 25oC at Rated I
ID = 1.0mA ±20% (Note 5) V

D

±20% (Note 5) Ω

Screening Information

TEST JANS

Gate Stress VGS = 30V, t = 250µs
Pind Required
Pre Burn-In Tests (Note 6) MIL-S-19500 Group A, Subgroup 2 (All Static Tests at 25oC)
Steady State Gate Bias (Gate Stress) MIL-STD-750, Method 1042, Condition B

VGS = 80% of Rated Value, TA = 150oC, Time = 48 hours
Interim Electrical Tests (Note 6) All Delta Parameters Listed in the Delta Tests and Limits Table
Steady State Reverse Bias (Drain Stress) MIL-STD-750, Method 1042, Condition A

VDS = 80% of Rated Value, TA = 150oC, Time = 240 hours
PDA 5%
Final Electrical Tests (Note 6) MIL-S-19500, Group A,

Subgroups 2 and 3

NOTE:

6. Test limits are identical pre and post burn-in.

Additional Screening Tests

PARAMETER SYMBOL TEST CONDITIONS MAX UNITS

Safe Operating Area SOA VDS = 160V, t = 10ms 1.6 A
Unclamped Inductive Switching I
Thermal Response ∆V
Thermal Impedance ∆V

AS

SD

SD

V

GS(PEAK)

tH = 100ms; VH = 25V; IH = 4A 136 mV
tH = 500ms; VH = 25V; IH = 4A 187 mV

= 15V, L = 0.1mH 69 A

Rad Hard Data Packages - Intersil Power Transistors

1. JANS Rad Hard - Standard Data Package

A. Certificate of Compliance
B. Serialization Records
C. Assembly Flow Chart
D. SEM Photos and Report

2-28

JANSR2N7294

TO-254AA

3 LEAD JEDEC TO-254AA HERMETIC METAL PACKAGE

A

A

1

J

1

SYMBOL

A 0.249 0.260 6.33 6.60 -

A

1

Øb 0.035 0.045 0.89 1.14 2, 3

D 0.790 0.800 20.07 20.32 ­E 0.535 0.545 13.59 13.84 ­e 0.150 TYP 3.81 TYP 4

e

1

H

1

J

1

L 0.520 0.560 13.21 14.22 -

ØP 0.139 0.149 3.54 3.78 -

Q 0.110 0.130 2.80 3.30 -

NOTES:

1. These dimensions are within allowable dimensions of Rev. A of
JEDEC outline TO-254AA dated 11-86.

2. Add typically 0.002 inches (0.05mm) for solder coating.

3. Lead dimension (without solder).

4. Positionof lead to be measured 0.250 inches (6.35mm) from bot­tom of dimension D.

5. Die to base BeO isolated, terminals to case ceramic isolated.

6. Controlling dimension: Inch.

7. Revision 1 dated 1-93.

TYP.

b

Ø

ØP

H

1

E

Q

D

0.065 R MAX.

L

123

e

e

1

INCHES MILLIMETERS

NOTESMIN MAX MIN MAX

0.040 0.050 1.02 1.27 -

0.300 BSC 7.62 BSC 4

0.245 0.265 6.23 6.73 -

0.140 0.160 3.56 4.06 4

WARNING!

BERYLLIA WARNING PER MIL-S-19500

Packages containing beryllium oxide (BeO) shall not be ground, machined, sandblasted, or subject to any mechanical
operation which will produce dust containing any beryllium compound. Packages containing any beryllium compound
shall not be subjected to any chemical process (etching, etc.) which will produce fumes containing beryllium or its’
compounds.

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil products are sold by description only.Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice.
Accordingly ,the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reli­able. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may
result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

Sales Office Headquarters

NORTH AMERICA

Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: [phone]
FAX: [phone]

EUROPE

Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: [phone]
FAX: [phone]

ASIA

Intersil (Taiwan) Ltd.
Taiwan Limited
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: [phone]
FAX: [phone]

2-29