Page 1
JANSR2N7292
Formerly FRF150R4
June 1998
Features
• 25A, 100V, r
• Total Dose
- Meets Pre-RAD Specifications to 100K RAD (Si)
• Dose Rate
- Typically Survives 3E9 RAD (Si)/s at 80% BV
- Typically Survives 2E12 if Current Limited to I
• Photo Current
- 7.0nA Per-RAD(Si)/s Typically
• Neutron
- Maintain Pre-RAD Specifications
for 3E13 Neutrons/cm
- Usable to 3E14 Neutrons/cm
Ordering Information
PART NUMBER PACKAGE BRAND
DS(ON)
= 0.070Ω
2
2
DSS
DM
25A, 100V, 0.070 Ohm, Rad Hard,
N-Channel Power MOSFET
Description
The Intersil Corporation has designed a series of SECOND
GENERATION hardened power MOSFETs of both N-Channel and P-Channel enhancement types with ratings from
100V to 500V, 1A to 60A, and on resistance as low as
25mΩ. Total dose hardness is offered at 100K RAD (Si) and
1000K RAD (Si) with neutron hardness ranging from 1E13
for 500V product to 1E14 for 100V product. Dose rate hardness (GAMMA DOT) exists for rates to 1E9 without current
limiting and 2E12 with current limiting.
This MOSFET is an enhancement-mode silicon-gate power
field effect transistor of the vertical DMOS (VDMOS) structure. It is specially designed and processed to exhibit minimal characteristic changes to total dose (GAMMA) and
neutron (n
also directed to enhance survival to dose rate (GAMMA
DOT) exposure.
Also available at other r adiation and screening le v els . See us
on the web, Intersil’s home page: http://www.semi.harris.com. Contact your local Intersil Sales Office for additional
information.
o
) exposures. Design and processing efforts are
JANSR2N7292 TO-254AA JANSR2N7292
Die family TA17651.
MIL-PRF-19500/605.
Pack age
CAUTION: Beryllia Warning per MIL-S-19500
Symbol
TO-254AA
G
S
D
refer to package specifications.
D
G
S
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
| Copyright © Intersil Corporation 1999
2-18
File Number 4293.2
Page 2
JANSR2N7292
Absolute Maximum Ratings T
= 25oC, Unless Otherwise Specified
C
JANSR2N7292 UNITS
Drain to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
Drain to Gate Voltage (RGS = 20kΩ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DS
DGR
100 V
100 V
Continuous Drain Current
TC = 25oC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
TC = 100oC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
D
D
DM
GS
25 A
20 A
75 A
±20 V
Maximum Power Dissipation
TC = 25oC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .P
TC = 100oC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .P
T
T
125 W
50 W
Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.00 W/oC
Single Pulsed Avalanche Current, L = 100µH, (See Test Figure). . . . . . . . . . . . . . . . . . . . . . I
Continuous Source Current (Body Diode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
Pulsed Source Current (Body Diode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TJC, T
STG
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
AS
S
SM
L
75 A
25 A
75 A
-55 to 150
300
o
C
o
C
(Distance >0.063in (1.6mm) from Case, 10s Max)
Weight (Typical) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.3 g
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications T
= 25oC, Unless Otherwise Specified
C
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Drain to Source Breakdown Voltage BV
Gate Threshold Voltage V
DSSID
GS(TH)VGS
= 1mA, VGS = 0V 100 - - V
= VDS,
ID = 1mA
TC = -55oC - - 5.0 V
TC = 25oC 2.0 - 4.0 V
TC = 125oC 1.0 - - V
Zero Gate Voltage Drain Current I
Gate to Source Leakage Current I
DSS
GSS
VDS = 80V,
VGS = 0V
TC = 25oC--25µA
TC = 125oC - - 250 µA
VGS = ±20V TC = 25oC - - 100 nA
TC = 125oC - - 200 nA
Drain to Source On-State Voltage V
Drain to Source On Resistance r
Turn-On Delay Time t
DS(ON)VGS
DS(ON)ID
d(ON)
Rise Time t
Turn-Off Delay Time t
d(OFF)
Fall Time t
Total Gate Charge (Not on slash sheet) Q
g(TOT)
Gate Charge at 10V Q
Threshold Gate Charge (Not on slash sheet) Q
Gate Charge Source Q
Gate Charge Drain Q
Thermal Resistance Junction to Case R
Thermal Resistance Junction to Ambient R
r
f
g(10)
g(TH)
gs
gd
JC
θ
JA
θ
= 10V, ID = 25A - - 1.84 V
= 20A,
VGS = 10V
VDD = 50V, ID = 25A,
RL = 2.0Ω, VGS = 10V,
RGS = 25Ω
TC = 25oC - - 0.070 Ω
TC = 125oC - - 0.140 Ω
- - 134 ns
- - 628 ns
- - 642 ns
- - 490 ns
VGS = 0V to 20V VDD = 50V,
VGS = 0V to 10V - - 314 nC
ID = 25A
- - 552 nC
VGS = 0V to 2V - - 17 nC
- - 46 nC
- - 164 nC
- - 1.0
o
C/W
--48oC/W
Source to Drain Diode Specifications
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Forward Voltage V
Reverse Recovery Time t
SD
rr
ISD = 25A 0.6 - 1.8 V
ISD = 25A, dISD/dt = 100A/µs - - 1400 ns
2-19
Page 3
JANSR2N7292
Electrical Specifications up to 100K RAD T
= 25oC, Unless Otherwise Specified
C
PARAMETER SYMBOL TEST CONDITIONS MIN MAX UNITS
Drain to Source Breakdown Volts (Note 3) BV
Gate to Source Threshold Volts (Note 3) V
Gate to Body Leakage (Notes 2, 3) I
Zero Gate Leakage (Note 3) I
Drain to Source On-State Volts (Notes 1, 3) V
Drain to Source On Resistance (Notes 1, 3) r
DS(ON)
DS(ON)
DSS
GS(TH)
GSS
DSS
VGS = 0, ID = 1mA 100 - V
VGS = VDS, ID = 1mA 2.0 4.0 V
VGS = ±20V, VDS = 0V - 100 nA
VGS = 0, VDS = 80V - 25 µA
VGS = 10V, ID = 25A - 1.84 V
VGS = 10V, ID = 20A - 0.070 Ω
NOTES:
1. Pulse test, 300µs Max.
2. Absolute value.
3. Insitu Gamma bias must be sampled for both VGS = 10V, VDS = 0V and VGS = 0V, VDS = 80% BV
Typical Performance Curves
40
30
20
, DRAIN (A)
D
I
10
0
TC, CASE TEMPERATURE (oC)
500-50
Unless Otherwise Specified
100
150
100
10
, DRAIN CURRENT (A)
1
D
I
0.1
OPERATION IN THIS
AREA MAY BE
LIMITED BY r
1
V
DS(ON)
, DRAIN TO SOURCE VOLTAGE (V)
DS
.
DSS
TC = 25oC
10 100
100ms
1ms
10ms
100ms
FIGURE 1. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
10
)
JC
1
θ
0.5
0.2
0.1
0.1
0.05
0.01
0.02
0.01
-5
10
SINGLE PULSE
-4
10
-3
10
t, RECTANGULAR PULSE DURATION (s)
NORMALIZED
THERMAL RESPONSE (Z
0.001
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL RESPONSE
2-20
FIGURE 2. FORWARD BIAS SAFE OPERATING AREA
P
DM
t
1
t
NOTES:
DUTY FACTOR: D = t
PEAK TJ = PDM x Z
-2
10
1/t2
+ T
JC
C
θ
-1
10
2
0
10
1
10
Page 4
JANSR2N7292
Test Circuits and Waveforms
ELECTRONIC SWITCH OPENS
WHEN I
V
DS
L
50Ω
+
I
AS
-
TRANSFORMER
VARY t
TO OBTAIN
P
REQUIRED PEAK I
CURRENT
AS
VGS≤ 20V
50Ω
0V
t
P
FIGURE 4. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 5. UNCLAMPED ENERGY WAVEFORMS
DUT
IS REACHED
AS
+
V
DD
-
50V-150V
BV
DSS
t
P
I
AS
t
AV
V
DS
V
DD
t
t
d(ON)
90%
ON
t
r
V
DD
R
L
V
DS
V
DS
t
d(OFF)
t
OFF
VGS = 10V
10%
90%
50%50%
PULSE WIDTH
0V
DUT
R
GS
V
GS
10%
FIGURE 6. RESISTIVE SWITCHING TEST CIRCUIT FIGURE 7. RESISTIVE SWITCHING WAVEFORMS
10V
Q
GS
Q
G
Q
GD
t
f
10%
90%
V
G
CHARGE
FIGURE 8. BASIC GATE CHARGE WAVEFORM
2-21
Page 5
JANSR2N7292
Screening Information
Screening is performed in accordance with the latest revision in effect of MIL-S-19500, (Screening Information Table).
Delta Tests and Limits (JANS) T
PARAMETER SYMBOL TEST CONDITIONS MAX UNITS
= 25oC, Unless Otherwise Specified
C
Gate to Source Leakage Current I
Zero Gate Voltage Drain Current I
Drain to Source On Resistance r
Gate Threshold Voltage V
NOTES:
4. Or 100% of Initial Reading (whichever is greater).
5. Of Initial Reading.
GSS
DSS
DS(ON)
GS(TH)
VGS = ±20V ±20 (Note 4) nA
VDS = 80% Rated Value ±25 (Note 4) µA
TC = 25oC at Rated I
ID = 1.0mA ±20% (Note 5) V
D
±20% (Note 5) Ω
Screening Information
TEST JANS
Gate Stress VGS = 30V, t = 250µs
Pind Required
Pre Burn-In Tests (Note 6) MIL-S-19500 Group A, Subgroup 2 (All Static Tests at 25oC)
Steady State Gate Bias (Gate Stress) MIL-STD-750, Method 1042, Condition B
VGS = 80% of Rated Value, TA = 150oC, Time = 48 hours
Interim Electrical Tests (Note 6) All Delta Parameters Listed in the Delta Tests and Limits Table
Steady State Reverse Bias (Drain Stress) MIL-STD-750, Method 1042, Condition A
VDS = 80% of Rated Value, TA = 150oC, Time = 240 hours
PDA 5%
Final Electrical Tests (Note 6) MIL-S-19500, Group A,
Subgroups 2 and 3
NOTE:
6. Test limits are identical pre and post burn-in.
Additional Screening Tests
PARAMETER SYMBOL TEST CONDITIONS MAX UNITS
Safe Operating Area SOA VDS = 80V, t = 10ms 5 A
Unclamped Inductive Switching I
Thermal Response ∆V
Thermal Impedance ∆V
AS
SD
SD
V
GS(PEAK)
tH = 100ms; VH = 25V; IH = 4A 136 mV
tH = 500ms; VH = 25V; IH = 4A 187 mV
= 15V, L = 0.1mH 75 A
2-22
Page 6
JANSR2N7292
Rad Hard Data Packages - Intersil Power Transistors
1. JANS Rad Hard - Standard Data Package
A. Certificate of Compliance
B. Serialization Records
C. Assembly Flow Chart
D. SEM Photos and Report
E.
Preconditioning Attributes Data Sheet
Hi-Rel Lot Traveler
HTRB - Hi Temp Gate Stress Post Reverse
Bias Data and Delta Data
HTRB - Hi T emp Drain Stress Post Reverse
Bias Delta Data
F. Group A - Attributes Data Sheet
G. Group B - Attributes Data Sheet
H. Group C - Attributes Data Sheet
I. Group D - Attributes Data Sheet
2. JANS Rad Hard - Optional Data Package
A. Certificate of Compliance
B. Serialization Records
C. Assembly Flow Chart
D. SEM Photos and Report
E. Preconditioning - Attributes Data Sheet
F. Group A - Attributes Data Sheet
G. Group B - Attributes Data Sheet
H. Group C - Attributes Data Sheet
I. Group D - Attributes Data Sheet
- Hi-Rel Lot Traveler
- HTRB - Hi Temp Gate Stress Post
Reverse Bias Data and Delta Data
- HTRB - Hi Temp Drain Stress Post
Reverse Bias Delta Data
- X-Ray and X-Ray Report
- Hi-Rel Lot Traveler
- Subgroups A2, A3, A4, A5 and A7 Data
- Hi-Rel Lot Traveler
- Subgroups B1, B3, B4, B5 and B6 Data
- Hi-Rel Lot Traveler
- Subgroups C1, C2, C3 and C6 Data
- Hi-Rel Lot Traveler
- Pre and Post Radiation Data
2-23
Page 7
JANSR2N7292
TO-254AA
3 LEAD JEDEC TO-254AA HERMETIC METAL PACKAGE
A
A
1
J
1
SYMBOL
A 0.249 0.260 6.33 6.60 -
A
1
Øb 0.035 0.045 0.89 1.14 2, 3
D 0.790 0.800 20.07 20.32 E 0.535 0.545 13.59 13.84 e 0.150 TYP 3.81 TYP 4
e
1
H
1
J
1
L 0.520 0.560 13.21 14.22 -
ØP 0.139 0.149 3.54 3.78 -
Q 0.110 0.130 2.80 3.30 -
NOTES:
1. These dimensions are within allowable dimensions of Rev . A of
JEDEC outline TO-254AA dated 11-86.
2. Add typically 0.002 inches (0.05mm) for solder coating.
3. Lead dimension (without solder).
4. Position of lead to be measured 0.250 inches (6.35mm) from bottom of dimension D.
5. Die to base BeO isolated, terminals to case ceramic isolated.
6. Controlling dimension: Inch.
7. Revision 1 dated 1-93.
TYP.
b
Ø
ØP
H
1
E
Q
D
0.065 R MAX.
L
123
e
e
1
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
0.040 0.050 1.02 1.27 -
0.300 BSC 7.62 BSC 4
0.245 0.265 6.23 6.73 -
0.140 0.160 3.56 4.06 4
WARNING!
BERYLLIA WARNING PER MIL-S-19500
Packages containing beryllium oxide (BeO) shall not be ground, machined, sandblasted, or subject to any mechanical
operation which will produce dust containing any beryllium compound. Packages containing any beryllium compound
shall not be subjected to any chemical process (etching, etc.) which will produce fumes containing beryllium or its’
compounds.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under an y patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (407) 724-7000
FAX: (407) 724-7240
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
ASIA
Intersil (Taiwan) Ltd.
Taiwan Limited
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
2-24
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