Datasheet JANSR2N7281 Datasheet (Intersil)

JANSR2N7281

Formerly FRL430R4

Data Sheet November 1998 File Number

Radiation Hardened, N-Channel
Power MOSFET

The Intersil has designed a series of SECOND
GENERATION hardened power MOSFETs of both N­Channel and P-Channel enhancement types with ratings
from 100V to 500V, 1A to 60A, and on resistance as low as
25mΩ. Total dose hardness is offered at 100K RAD (Si) and
1000K RAD (Si) with neutron hardness ranging from 1E13
for 500V product to 1E14 for 100V product. Dose rate
hardness (GAMMA DOT) exists for rates to 1E9 without
current limiting and 2E12 with current limiting.

This MOSFET is an enhancement-mode silicon-gate power
field effect transistor of the vertical DMOS (VDMOS)
structure. It is specially designed and processed to exhibit
minimal characteristic changes to total dose (GAMMA) and
neutron (n
also directed to enhance survival to dose rate (GAMMA
DOT) exposure.

Also availableatotherradiation and screening levels.Seeus
on the web, Intersil’ home page: www.semi.intersil.com.
Contact your local Intersil Sales Office for additional
information.

o

) exposures. Design and processing efforts are

Ordering Information

Features

• 2A, 500V, r

• Total Dose

- Meets Pre-RAD Specifications to 100K RAD (Si)

• Dose Rate

- Typically Survives 3E9 RAD (Si)/s at 80% BV

- Typically Survives 2E12 if Current Limited to I

• Photo Current

- 8nA Per-RAD (Si)/s Typically

• Neutron

- Maintain Pre-RAD Specifications for 3E12
Neutrons/cm

- Usable to 3E13 Neutrons/cm

DS(ON)

2

= 2.50Ω

2

Symbol

D

G

S

4294

DSS

DM

PART NUMBER PACKAGE BRAND

JANSR2N7281 TO-205AF JANSR2N7281

Die family TA17635.
MIL-PRF-19500/604.

Package

TO-205AF

G

S

D

4-1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

www.intersil.com or 407-727-9207

| Copyright © Intersil Corporation 1999

JANSR2N7281

Absolute Maximum Ratings T

= 25oC, Unless Otherwise Specified

C

JANSR2N7281 UNITS

Drain to Source Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V

Drain to Gate Voltage (RGS = 20kΩ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V

DS

DGR

500 V
500 V

Continuous Drain Current

TC = 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I

TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I

Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I

Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V

D
D

DM

GS

2A
1A
6A

±20 V

Maximum Power Dissipation

TC = 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P

TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P

T
T

25 W
10 W

Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.20 W/oC

Single Pulsed Avalanche Current, L = 100µH, (See Test Figure) . . . . . . . . . . . . . . . . . . . . . .I

Continuous Source Current (Body Diode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I

Pulsed Source Current (Body Diode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TJC, T

STG

Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T

AS

S

SM

L

6A
2A
6A

-55 to 150
300

o

C

o

C

(Distance >0.063in (1.6mm) from Case, 10s Max)

Weight (Typical) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0 g

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Electrical Specifications TC = 25oC, Unless Otherwise Specified

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Drain to Source Breakdown Voltage BV
Gate Threshold Voltage V

GS(TH)VGS

Zero Gate Voltage Drain Current I

Gate to Source Leakage Current I

Drain to Source On-State Voltage V
On Resistance r

Turn-On Delay Time t

DS(ON)VGS

DS(ON)ID

d(ON)

Rise Time t
Turn-Off Delay Time t

d(OFF)

Fall Time t
Total Gate Charge Q

g(TOT)VGS

Gate Charge at 10V Q
Threshold Gate Charge Q
Gate Charge Source Q
Gate Charge Drain Q
Thermal Resistance Junction to Case R
Thermal Resistance Junction to Ambient R

DSSID

DSS

GSS

r

f

g(10)

g(TH)

gs

gd

JC

θ

JA

θ

= 1mA, VGS = 0V 500 - - V

= VDS,

ID = 1mA

VDS = 400V,
VGS = 0V

TC = -55oC - - 5.0 V

= 25oC 2.0 - 4.0 V

T

C

= 125oC 1.0 - - V

T

C

TC = 25oC--25µA

= 125oC - - 250 µA

T

C

VGS = ±20V TC = 25oC - - 100 nA

= 125oC 200 nA

T

C

= 10V, ID = 2A 5.25 V

= 1A,

VGS = 10V
VDD = 250V, ID = 2A,

RL = 125Ω, VGS = 10V,
RGS =25Ω

TC = 25oC - - 2.50 Ω

= 125oC - - 6.50 Ω

T

C

- - 46 ns

- - 58 ns

- - 208 ns

- - 54 ns

= 0V to 20V VDD = 250V,

VGS = 0V to 10V - - 64 nC

ID = 2A,
RL = 125Ω

- - 130 nC

VGS = 0V to 2V - - 4 nC

- - 12 nC

- - 32 nC

- - 5.0

- - 175

o
o

C/W
C/W

Source to Drain Diode Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Forward Voltage V
Reverse Recovery Time t

4-2

SD

rr

ISD = 2A 0.6 - 1.8 V
ISD = 2A, dISD/dt = 100A/µs - - 900 ns

JANSR2N7281

Electrical Specifications up to 100K RAD T

= 25oC, Unless Otherwise Specified

C

PARAMETER SYMBOL TEST CONDITIONS MIN MAX UNITS

Drain to Source Breakdown Volts (Note 3) BV
Gate to Source Threshold Volts (Note 3) V
Gate to Body Leakage (Notes 2, 3) I
Zero-Gate Leakage (Note 3) I
Drain to Source On-State Volts (Notes 1, 3) V
Drain to Source On Resistance (Notes 1, 3) r

DS(ON)VGS

DS(ON)VGS

DSS

GS(TH)VGS

GSS
DSS

VGS = 0, ID = 1mA 500 - V

= VDS, ID = 1mA 2.0 4.0 V
VGS = ±20V, VDS = 0V - 100 nA
VGS = 0, VDS = 400V - 25 µA

= 10V, ID = 2A - 5.25 V

= 10V, ID = 1A - 2.5 Ω

NOTES:

1. Pulse test, 300µs Max.

2. Absolute value.

3. Insitu Gamma bias must be sampled for both VGS = 10V, VDS = 0V and VGS = 0V, VDS = 80% BV

Typical Performance Curves

2

, DRAIN (A)

D

1

I

0

TC, CASE TEMPERATURE (oC)

Unless Otherwise Specified

150100500-50

30

10

1

, DRAIN CURRENT (A)

0.1

D

I

0.01

OPERATION IN THIS
AREA MAY BE
LIMITED BY r

1

VDS, DRAIN TO SOURCE VOLTAGE (V)

DSS

DS(ON)

10

.

TC = 25oC

100µs

1ms

10ms

100ms

100

1000

FIGURE 1. MAXIMUMCONTINUOUSDRAIN CURRENT vs

CASE TEMPERATURE

1.0

0.5

)

qJC

0.01

NORMALIZED

THERMAL RESPONSE (Z

0.001

0.1

0.2

0.1

0.05

0.02

0.01

SINGLE PULSE

-5

10

-4

10

-3

10

t, RECTANGULAR PULSE DURATION (s)

FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL RESPONSE

FIGURE 2. FORWARD BIAS SAFE OPERATING AREA

P

+ T

10

DM

C

0

NOTES:
DUTY FACTOR: D = t
PEAK TJ = PDM x Z

-2

10

-1

10

1/t2

qJC

t

1

t

2

1

10

4-3

Test Circuits and Waveforms

JANSR2N7281

ELECTRONIC SWITCH OPENS

WHEN I

V

DS

IS REACHED

AS

L

BV

DSS

P

t

AV

VARY t

TO OBTAIN

P

REQUIRED PEAK I

VGS≤ 20V

t

0V

P

CURRENT

TRANSFORMER

50Ω

AS

+

I

AS

-

t

I

AS

+

V

DD

-

DUT

50V-150V

50Ω

FIGURE 4. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 5. UNCLAMPED ENERGY WAVEFORMS

t

t

d(ON)

90%

ON

10%

t

r

PULSE WIDTH

0V

VGS = 10V

V

DD

R

L

V

DS

V

DS

DUT

R

GS

V

GS

10%

V

DS

t

d(OFF)

90%

t

OFF

50%50%

V

t

f

10%

DD

90%

FIGURE 6. RESISTIVE SWITCHING TEST CIRCUIT FIGURE 7. RESISTIVE SWITCHING WAVEFORMS

10V

V

Q

GS

G

BASIC GATE CHARGE WAVEFORM

Q

G

Q

GD

CHARGE

FIGURE 8. BASIC GATE CHARGE WAVEFORM

4-4

JANSR2N7281

Screening Information

Screening is performed in accordance with the latest revision in effect of MIL-S-19500, (Screening Information Table).

Delta Tests and Limits (JANS) T

PARAMETER SYMBOL TEST CONDITIONS MAX UNITS

= 25oC, Unless Otherwise Specified

C

Gate to Source Leakage Current I
Zero Gate Voltage Drain Current I
On Resistance r
Gate Threshold Voltage V

NOTES:

4. Or 100% of Initial Reading (whichever is greater).

5. Of Initial Reading.

DS(ON)

GS(TH)

GSS

DSS

VGS = ±20V ±20 (Note 4) nA
VDS = 80% Rated Value ±25 (Note 4) µA
TC = 125oC at Rated I
ID = 1.0mA ±20% (Note 5) V

D

±20% (Note 5) Ω

Screening Information

TEST JANS

Gate Stress VGS = 30V, t = 250µs
Pind Required
Pre Burn-In Tests (Note 6) MIL-S-19500 Group A, Subgroup 2 (All Static Tests at 25oC)
Steady State Gate Bias (Gate Stress) MIL-STD-750, Method 1042, Condition B

VGS = 80% of Rated Value, TA = 150oC, Time = 48 hours
Interim Electrical Tests (Note 6) All Delta Parameters Listed in the Delta Tests and Limits Table
Steady State Reverse Bias (Drain Stress) MIL-STD-750, Method 1042, Condition A

VDS = 80% of Rated Value, TA = 150oC, Time = 240 hours
PDA 5%
Final Electrical Tests (Note 6) MIL-S-19500, Group A,

Subgroups 2 and 3

NOTE:

6. Test limits are identical pre and post burn-in.

Additional Screening Tests

PARAMETER SYMBOL TEST CONDITIONS MAX UNITS

Safe Operating Area SOA VDS = 200V, t = 10ms 0.50 A
Unclamped Inductive Switching I
Thermal Response ∆V
Thermal Impedance ∆V

AS

SD

SD

V

GS(PEAK)

tH = 10ms; VH = 25V; IH = 2A 92 mV
tH = 500ms; VH = 25V; IH = 1A 190 mV

= 15V, L = 0.1mH 6 A

4-5

JANSR2N7281

Rad Hard Data Packages - Intersil Power Transistors

1. JANS Rad Hard - Standard Data Package

A. Certificate of Compliance
B. Serialization Records
C. Assembly Flow Chart
D. SEM Photos and Report
E. Preconditioning - Attributes Data Sheet

- Hi-Rel Lot Traveler

- HTRB - Hi Temp Gate Stress Post
Reverse Bias Data and Delta Data

- HTRB - Hi Temp Drain Stress Post
Reverse Bias Delta Data

F. Group A - Attributes Data Sheet
G. Group B - Attributes Data Sheet
H. Group C - Attributes Data Sheet

I. Group D - Attributes Data Sheet

2. JANS Rad Hard - Optional Data Package

A. Certificate of Compliance
B. Serialization Records
C. Assembly Flow Chart
D. SEM Photos and Report
E. Preconditioning - Attributes Data Sheet

- Hi-Rel Lot Traveler

- HTRB - Hi Temp Gate Stress Post
Reverse Bias Data and Delta Data

- HTRB - Hi Temp Drain Stress Post
Reverse Bias Delta Data

- X-Ray and X-Ray Report

F. Group A - Attributes Data Sheet

- Hi-Rel Lot Traveler

- Subgroups A2, A3, A4, A5 and A7 Data

G. Group B - Attributes Data Sheet

- Hi-Rel Lot Traveler

- Subgroups B1, B3, B4, B5 and B6 Data

H. Group C - Attributes Data Sheet

- Hi-Rel Lot Traveler

- Subgroups C1, C2, C3 and C6 Data

I. Group D - Attributes Data Sheet

- Hi-Rel Lot Traveler

- Pre and Post Radiation Data

4-6

JANSR2N7281

TO-205AF

3 LEAD JEDEC TO-205AF HERMETIC METAL CAN PACKAGE

ØD

ØD

1

A

P

SYMBOL

A 0.160 0.180 4.07 4.57 -

INCHES MILLIMETERS

NOTESMIN MAX MIN MAX

Øb 0.016 0.021 0.41 0.53 2, 3

h

L

e

1

e

2

45

j

1

o

SEATING
PLANE

Øb

e

o

90

2

3

k

ØD 0.350 0.370 8.89 9.39 -

ØD

0.315 0.335 8.01 8.50 -

1

e 0.095 0.105 2.42 2.66 4

e

1

e

2

0.190 0.210 4.83 5.33 4

0.095 0.105 2.42 2.66 4

h 0.010 0.020 0.26 0.50 -

j 0.028 0.034 0.72 0.86 ­k 0.029 0.045 0.74 1.14 ­L 0.500 0.560 12.70 14.22 3

P 0.075 - 1.91 - 5

NOTES:

1. These dimensions are within allowable dimensions of Rev. E of
JEDEC TO-205AF outline dated 11-82.

2. Lead dimension (without solder).

3. Solder coating may vary along lead length, add typically 0.002
inches (0.05mm) for solder coating.

4. Positionof leadto bemeasured 0.100inches (2.54mm)from bottom
of seating plane.

5. This zone controlled for automatic handling. The variation in
actual diameter within this zone shall not exceed 0.010 inches
(0.254mm).

6. Lead no. 3 butt welded to stem base.

7. Controlling dimension: Inch.

8. Revision 3 dated 6-94.

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changesincircuit design and/or specifications at any time with­out notice. Accordingly,the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For inf ormationregardingIntersil Corporation and its products,see web site www.intersil.com

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TEL: [phone]
FAX: [phone]

4-7

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