• Built using the advantages and compatibility
of CMOS and IXYS HDMOSTM processes.
• Latch-Up Protected
• High Peak Output Current: 14A Peak
• Wide Operating Range: 4.5V to 25V
• Ability to Disable Output under Faults
• High Capacitive Load
Drive Capability: 15nF in <30ns
• Matched Rise And Fall Times
• Low Propagation Delay Time
• Low Output Impedance
• Low Supply Current
Applications
• Driving MOSFETs and IGBTs
• Limiting di/dt under Short Circuit
• Motor Controls
• Line Drivers
• Pulse Generators
• Local Power ON/OFF Switch
• Switch Mode Power Supplies (SMPS)
• DC to DC Converters
• Pulse Transformer Driver
• Class D Switching Amplifiers
General Description
The IXDD414 is a high speed high current gate driver
specifically designed to drive the largest MOSFETs and
IGBTs to their minimum switching time and maximum
practical frequency limits. The IXDD414 can source and
sink 14A of peak current while producing voltage rise and
fall times of less than 30ns. The input of the driver is
compatible with TTL or CMOS and is fully immune to
latch up over the entire operating range. Designed with
small internal delays, cross conduction/current shootthrough is virtually eliminated in the IXDD414. Its features
and wide safety margin in operating voltage and power
make the IXDD414 unmatched in performance and value.
The IXDD414 incorporates a unique ability to disable the
output under fault conditions. When a logical low is
forced into the Enable input, both final output stage
MOSFETs (NMOS and PMOS) are turned off. As a
result, the output of the IXDD414 enters a tristate mode
and achieves a Soft Turn-Off of the MOSFET/IGBT when
a short circuit is detected. This helps prevent damage
that could occur to the MOSFET/IGBT if it were to be
switched off abruptly due to a dv/dt over-voltage transient.
The IXDD414 is available in the standard 8-pin P-DIP (PI),
5-pin TO-220 (CI) and in the TO-263 (YI) surface-mount
package.
Positiv e power-supply v oltage input. This pin provides power to the
entire chip. T he r ange f or this voltage is from 4.5V to 25V.
IN Input Input signal-T TL or CMOS compatible.
EN Enable
OUT Output
The system enabl e pin. This pi n, when driven low, di sables the chi p,
forcing high im pedance stat e to the output.
Driver Output. For application purposes, this pin is connected,
through a resistor, to Gate of a MOSFET/IGBT.
The system ground pin. Inter nally connected t o all circuit ry, this pin
GND Ground
provides ground reference for the entire chip. This pin should be
connected to a low noise analog ground plane for optimum
performance.
Note 1: Operating the device beyond parameters with listed “absolute maximum ratings” may cause permanent
damage to the device. Typical values indicate conditions for which the device is intended to be functional, but do not
guarantee specific performance limits. The guaranteed specifications apply only for the test conditions listed.
Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD procedures
when handling and assembling this component.
Figure 2 - Characteristics Test Diagram
IN
V
3
Page 4
)
Typical Performance Characteristics
IXDD414PI/414YI/414CI
Fig. 3
40
30
20
Rise Time vs. Supply Voltage
CL=15,000 pF
7,500 pF
Rise Time (ns)
10
0
81012141618
3,600 pF
Supply Voltage (V)
Fig. 5
40
35
30
25
20
Rise And Fall Times vs. Temperature
= 15 nF, Vcc = 18V
C
L
t
R
t
F
Fig. 4
40
30
20
Fall Time (ns)
10
0
81012141618
Fall Time vs. Supply Voltage
CL=15,000 pF
7,500 pF
3,600 pF
Supply Voltage (V)
Fig. 6
50
40
30
Rise Time vs. Load C apacitance
14V
8V
10V
12V
18V
16V
Time (ns)
15
10
5
0
-40-20020406080100120
Temperature (°C
Fig. 7
40
30
20
Fall Time vs. Load Capacitance
14V
12V
Fall Time (ns)
10
0
0k5k10k15k20k
Load Capa citance (pF)
16V
10V
18V
20
Rise Time (ns)
10
0
0k5k10k15k20k
Load Capa citance (pF)
Fig. 8
3.2
8V
3.0
2.8
2.6
2.4
2.2
Max / Min Input (V)
2.0
1.8
1.6
-60-40-20020406080100
Max / Min Input vs. Temperature
=18V CL=15nF
V
CC
Minimum Input High
Maximum Input Low
Temperature (oC)
4
Page 5
IXDD414PI/414YI/414CI
Fig. 9
Supply Current vs. Load Capacitance
Vcc=18V
1000
2 MHz
100
1 MHz
500 kHz
10
Supply Current (mA)
100 kHz
50 kHz
1
1k10k100k
Load Capa citance (pF)
Fig. 11
Supply Current vs. Load Capacitance
Vcc=12V
1000
100
2 MHz
1 MHz
500 kHz
10
Supply Current (mA)
100 kHz
50 kHz
1
1k10k100k
Load Capa citance (pF)
Fig. 10
1000
100
10
Supply Current (mA)
1
0.1
Fig. 12
1000
100
10
Supply Current (mA )
1
0.1
Supply Current vs. Frequency
Vcc=18V
CL= 30 nF
15 nF
5000 pF
2000 pF
10100100010000
Frequency (kHz)
Supply Current vs. Frequency
Vcc=12V
CL = 30 nF
15 nF
5000 pF
2000 pF
10100100010000
Frequency (kHz)
Fig. 13
Supply Current vs. Load Capacitance
Vcc=8V
1000
100
2 MHz
1 MHz
10
500 kHz
Supply Current (mA)
100 kHz
1
50 kHz
1k10k100k
Load Capa citance (pF)
Fig. 14
Supply Current vs. Frequency
Vcc=8V
1000
100
10
Supply Current (mA)
1
0.1
10100100010000
5
CL= 30 nF
15 nF
5000 pF
2000 pF
Frequency (kHz)
Page 6
IXDD414PI/414YI/414CI
(
)
)
Fig. 15
50
40
30
20
Propagation Delay (ns)
10
Propagation Delay vs. Supply Voltage
=15nF VIN=5V@1kHz
C
L
t
OFFDLY
t
ONDLY
0
8 1012141618
Supply Voltage (V)
Fig. 17
50
45
40
35
30
Time (ns)
25
Propagation Delay Times vs. Temperature
= 2500pF, VCC = 18V
C
L
t
ONDLY
t
OFFDLY
Fig. 16
50
40
30
20
Propagation Delay (ns)
10
0
Propagation Delay vs. Input Voltage
=15nF VCC=15V
C
L
t
ONDLY
t
OFFDLY
24681012
Input Voltage (V)
Fig. 18
0.60
0.58
0.56
0.54
Quiescent Supply Current vs. Temperature
=18V VIN=5V@1kHz
V
CC
20
15
10
-40-200 20406080100120
Temperature (°C
Fig. 19
16
15
14
13
P channel Output Current Vs. Temperature
V
=18V CL=.1uF
CC
P Channel Output Current (A)
12
-40-200 20406080100
Temperature (oC)
0.52
Quiescent Supply Current (mA)
0.50
-40-200 20406080
o
C
Fig. 20
17
16
15
Temperature
N C hannel Output Current vs. Temperature
V
=18V CL=.1uF
CC
N C hannel Output Current (A)
14
-40-200 20406080100
Temperature (oC)
6
Page 7
IXDD414PI/414YI/414CI
Fig. 21
14
12
10
8
6
4
Enable Threshold (V)
2
0
Enable Threshold vs. Supply Voltage
8 101214161820222426
Supply Voltage (V)
Fig. 23
Low-State Output Resistance
Vs. Supply Voltage
1.0
0.8
0.6
0.4
0.2
Low-State Output Resistance (Ohm s)
0.0
8
10152025
Supply Voltage (V)
Fig. 22
1.0
0.8
0.6
0.4
0.2
High State Output Resistance (Ohm )
0.0
8
Fig. 24
0
-2
-4
-6
-8
-10
-12
-14
-16
-18
-20
P Channel Output Current (A)
-22
-24
8
High State Output Resistance
vs. Supply Voltage
10152025
Supply Voltage (V)
VCC vs. P Channel Output Current
C
=.1uF VIN=0-5V@1kH z
L
10152025
Vcc
Fig. 25
N Channel Output Current (A)
Vcc vs. N Channel Output Current
C
=.1uF VIN=0-5V@ 1kHz
L
24
22
20
18
16
14
12
10
8
6
4
2
0
8
10152025
Vcc
Figure 26 - Typical Application Short Circuit di/dt Limit
7
Page 8
APPLICATIONS INFORMATION
Short Circuit di/dt Limit
IXDD414PI/414YI/414CI
A short circuit in a high-power MOSFET module such as the
VM0580-02F, (580A, 200V), as shown in Figure 26, can cause
the current through the module to flow in excess of 1500A for
10µs or more prior to self-destruction due to thermal runaway.
For this reason, some protection circuitry is needed to turn off
the MOSFET module. However, if the module is switched off
too fast, there is a danger of voltage transients occuring on the
drain due to Ldi/dt, (where L represents total inductance in
series with drain). If these voltage transients exceed the
MOSFET's voltage rating, this can cause an avalanche breakdown.
The IXDD414 has the unique capability to softly switch off the
high-power MOSFET module, significantly reducing these
Ldi/dt transients.
Thus, the IXDD414 helps to prevent device destruction from
both dangers; over-current, and avalanche breakdown due to
di/dt induced over-voltage transients.
The IXDD414 is designed to not only provide ±14A under
normal conditions, but also to allow it's output to go into a high
impedance state. This permits the IXDD414 output to control
a separate weak pull-down circuit during detected overcurrent
shutdown conditions to limit and separately control d
turnoff. This circuit is shown in Figure 27.
VGS
/dt gate
Referring to Figure 27, the protection circuitry should include
a comparator, whose positive input is connected to the source
of the VM0580-02. A low pass filter should be added to the input
of the comparator to eliminate any glitches in voltage caused
by the inductance of the wire connecting the source resistor to
ground. (Those glitches might cause false triggering of the
comparator).
The comparator's output should be connected to a SRFF(Set
Reset Flip Flop). The flip-flop controls both the Enable signal,
and the low power MOSFET gate. Please note that CMOS 4000series devices operate with a V
18 VDC being the maximum allowable limit).
range from 3 to 15 VDC, (with
CC
A low power MOSFET, such as the 2N7000, in series with a
resistor, will enable the VMO580-02F gate voltage to drop
gradually. The resistor should be chosen so that the RC time
constant will be 100us, where "C" is the Miller capacitance of
the VMO580-02F.
For resuming normal operation, a Reset signal is needed at
the SRFF's input to enable the IXDD414 again. This Reset can
be generated by connecting a One Shot circuit between the
IXDD414 Input signal and the SRFF restart input. The One Shot
will create a pulse on the rise of the IXDD414 input, and this
pulse will reset the SRFF outputs to normal operation.
When a short circuit occurs, the voltage drop across the lowvalue, current-sensing resistor, (Rs=0.005 Ohm), connected
between the MOSFET Source and ground, increases. This
triggers the comparator at a preset level. The SRFF drives a low
input into the Enable pin disabling the IXDD408 output. The
SRFF also turns on the low power MOSFET, (2N7000).
In this way, the high-power MOSFET module is softly turned off
by the IXDD414, preventing its destruction.
Figure 27 - Application Test Diagram
One Shot Circuit
NOT1
CD4049A
EN
Ros
1Mohm
Cos
1pF
+
-
NAND
CD4011A
VCC
SR Flip-Flop
+
VIN
-
NOT2
CD4049A
NOT3
CD4049A
Q
VCC
VCCA
IN
EN
GND
SUB
NOR1
CD4001A
NOR2
CD4001A
IXDD414
R
S
OUT
Rcomp
5kohm
Ccomp
+
Rd
0.1ohm
High_Power
VMO58 0-02F
Rs
Ls
20nH
0
VB
-
Ld
10uH
Rg
Low_Power
2N7002/PLP
+
V+
V-
-
REF
1ohm
10kohm
+
-
R+
C+
100pF
Rsh
1600ohm
Comp
LM339
1pF
8
Page 9
IXDD414PI/414YI/414CI
Supply Bypassing and Grounding Practices,
Output Lead inductance
When designing a circuit to drive a high speed MOSFET
utilizing the IXDD414, it is very important to keep certain design
criteria in mind, in order to optimize performance of the driver.
Particular attention needs to be paid to Supply Bypassing,
Grounding, and minimizing the Output Lead Inductance.
Say, for example, we are using the IXDD408 to charge a
5000pF capacitive load from 0 to 25 volts in 25ns.
Using the formula: I= ∆V C / ∆t, where ∆V=25V C=5000pF &
∆t=25ns we can determine that to charge 5000pF to 25 volts
in 25ns will take a constant current of 5A. (In reality, the charging
current won’t be constant, and will peak somewhere around
8A).
SUPPLY BYPASSING
In order for our design to turn the load on properly, the IXDD414
must be able to draw this 5A of current from the power supply
in the 25ns. This means that there must be very low impedance
between the driver and the power supply. The most common
method of achieving this low impedance is to bypass the
power supply at the driver with a capacitance value that is a
magnitude larger than the load capacitance. Usually, this
would be achieved by placing two different types of bypassing
capacitors, with complementary impedance curves, very close
to the driver itself. (These capacitors should be carefully
selected, low inductance, low resistance, high-pulse currentservice capacitors). Lead lengths may radiate at high frequency
due to inductance, so care should be taken to keep the lengths
of the leads between these bypass capacitors and the IXDD414
to an absolute minimum.
GROUNDING
In order for the design to turn the load off properly, the IXDD414
must be able to drain this 5A of current into an adequate
grounding system. There are three paths for returning current
that need to be considered: Path #1 is between the IXDD414
and it’s load. Path #2 is between the IXDD414 and it’s power
supply. Path #3 is between the IXDD414 and whatever logic
is driving it. All three of these paths should be as low in
resistance and inductance as possible, and thus as short as
practical. In addition, every effort should be made to keep these
three ground paths distinctly separate. Otherwise, (for
instance), the returning ground current from the load may
develop a voltage that would have a detrimental effect on the
logic line driving the IXDD414.
OUTPUT LEAD INDUCTANCE
Of equal importance to Supply Bypassing and Grounding are
issues related to the Output Lead Inductance. Every effort
should be made to keep the leads between the driver and it’s
load as short and wide as possible. If the driver must be placed
farther than 2” from the load, then the output leads should be
treated as transmission lines. In this case, a twisted-pair
should be considered, and the return line of each twisted pair
should be placed as close as possible to the ground pin of the
driver, and connect directly to the ground terminal of the load.
TTL to High Voltage CMOS Level Translation
The enable (EN) input to the IXDD414 is a high voltage
CMOS logic level input where the EN input threshold is ½ VCC,
and may not be compatible with 5V CMOS or TTL input levels.
The IXDD414 EN input was intentionally designed for
enhanced noise immunity with the high voltage CMOS logic
levels. In a typical gate driver application, V
EN input threshold at 7.5V, a 5V CMOS logical high input
applied to this typical IXDD414 application’s EN input will be
misinterpreted as a logical low, and may cause undesirable
or unexpected results. The note below is for optional
adaptation of TTL or 5V CMOS levels.
The circuit in Figure 28 alleviates this potential logic level
misinterpretation by translating a TTL or 5V CMOS logic input
to high voltage CMOS logic levels needed by the IXDD414 EN
input. From the figure, VCC is the gate driver power supply,
typically set between 8V to 20V, and VDD is the logic power
supply, typically between 3.3V to 5.5V. Resistors R1 and R2
form a voltage divider network so that the Q1 base is
positioned at the midpoint of the expected TTL logic transition
levels.
A TTL or 5V CMOS logic low, V
the Q1 emitter will drive it on. This causes the level translator
=~<0.8V, input applied to
TTLLOW
output, the Q1 collector output to settle to V
V
=<~2V, which is sufficiently low to be correctly
TTLLOW
interpreted as a high voltage CMOS logic low (<1/3VCC=5V for
VCC =15V given in the IXDD414 data sheet.)
A TTL high, V
V
5VCMOSHIGH
Figure 28 will cause Q1 to be biased off. This results in Q1
=~>3.5V, applied to the EN input of the circuit in
=>~2.4V, or a 5V CMOS high,
TTLHIGH
collector being pulled up by R3 to VCC=15V, and provides a
high voltage CMOS logic high output. The high voltage CMOS
logical EN output applied to the IXDD414 EN input will enable
it, allowing the gate driver to fully function as an 8 Amp output
driver.
The total component cost of the circuit in Figure 28 is less
than $0.10 if purchased in quantities >1K pieces. It is
recommended that the physical placement of the level
translator circuit be placed close to the source of the TTL or
CMOS logic circuits to maximize noise rejection.
Figure 28 - TTL to High Voltage CMOS Level Translator
Directed Energy, Inc.
An IXYS Company
2401 Research Blvd. Ste. 108, Ft. Collins, CO 80526
Tel: 970-493-1901; Fax: 970-493-1903
e-mail: [email protected]
Doc #9200-0228 R5
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